WO2007020677A1 - Appareil de transmission - Google Patents

Appareil de transmission Download PDF

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Publication number
WO2007020677A1
WO2007020677A1 PCT/JP2005/014823 JP2005014823W WO2007020677A1 WO 2007020677 A1 WO2007020677 A1 WO 2007020677A1 JP 2005014823 W JP2005014823 W JP 2005014823W WO 2007020677 A1 WO2007020677 A1 WO 2007020677A1
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WO
WIPO (PCT)
Prior art keywords
bits
dummy
bit
code
information
Prior art date
Application number
PCT/JP2005/014823
Other languages
English (en)
Japanese (ja)
Inventor
Shunji Miyazaki
Tetsuya Yano
Original Assignee
Fujitsu Limited
Obuchi, Kazuhisa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited, Obuchi, Kazuhisa filed Critical Fujitsu Limited
Priority to JP2007530861A priority Critical patent/JP4717072B2/ja
Priority to CN2005800502632A priority patent/CN101208865B/zh
Priority to EP05780307A priority patent/EP1914897A4/fr
Priority to EP12179263A priority patent/EP2521270A1/fr
Priority to PCT/JP2005/014823 priority patent/WO2007020677A1/fr
Publication of WO2007020677A1 publication Critical patent/WO2007020677A1/fr
Priority to US12/068,717 priority patent/US8181099B2/en
Priority to US13/345,969 priority patent/US8234557B2/en
Priority to US13/444,358 priority patent/US8458579B2/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2903—Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6522—Intended application, e.g. transmission or communication standard
    • H03M13/653—3GPP HSDPA, e.g. HS-SCCH or DS-DSCH related

Definitions

  • the present invention relates to a transmission apparatus, and in particular, inserts dummy bits into information bits and encodes them to generate a systematic code, deletes the systematic codes from the systematic code, and transmits them.
  • the present invention relates to a transmission apparatus in a system for decoding by inserting dummy bits with the maximum likelihood.
  • an N-bit code I is formed by signing an information bit I consisting of K bits.
  • a systematic code is a turbo code.
  • the Fabet becomes a block code
  • the information alphabet u is a block code
  • the receiving side estimates the received data force information alphabet U for the code vector X. To do this, the following notity check relation for X
  • FIG. 36 is a block diagram of a communication system that performs block coding for a transmitter and decodes for a receiver.
  • the transmitter 1 codes information u consisting of K bits.
  • a code unit la for generating an N-bit block code X and a modulation unit lb for modulating and transmitting the block code are provided.
  • the receiver 2 includes a demodulator 2a that demodulates the signal received via the transmission path 3, and a decoder 2b that decodes the original transmitted K-bit information from the N-bit received information.
  • the PZS converter Id that outputs the block code X is provided.
  • a code of the code part la for example, a turbo code can be adopted.
  • the decoding unit 2b includes a decoder 2c that performs error detection correction processing on the reception likelihood data y, decodes the originally transmitted K-bit information, and outputs estimated information.
  • the block code X transmitted from the transmitter 1 is not input as it is transmitted to the decoder 2c due to the influence of the transmission path 3, but is input to the decoder 2c as likelihood data.
  • Likelihood data also has confidence that the sign bit is 0 or 1 and a sign (0 if +1, 1 if -1).
  • the decoder 2c performs a prescribed decoding process based on the likelihood data for each code bit and estimates the information bit u. Decoder 2c has maximum a posteriori probability decoding (MAP decoding: Maximu m A Posteriori Pro
  • FIG. 37 is a configuration diagram of the turbo encoding unit la
  • FIG. 38 is a configuration diagram of the turbo decoding unit 2b.
  • a turbo code is a systematic code consisting of several element encoders and an interleaver.
  • Fig. 37 shows an example of a code in which two element encoders are arranged in parallel across one interleaver.
  • U [u0, ul, u2, u3, .., u] is transmitted.
  • Length K information data, xa [u0, ul, u2, u3, .., u] is transmitted.
  • xb, xc are code data obtained by encoding the information data u in the turbo code part la
  • ya, yb, yc are the encoded data xa, xb, xc propagate through the channel 3 and are affected by noise and fading.
  • Received The received signal is a decoding result obtained by decoding the received data ya, yb, yc in the turbo decoding unit 2b.
  • the code data xa is the information data u itself
  • the encoded data xb is data obtained by convolutionally encoding the information data u with the first element encoder ENC 1
  • the code data xc is information.
  • Data u is interleaved ( ⁇ ) and convolutionally encoded by the second element encoder ⁇ NC2. That is, the turbo code is a systematic code synthesized by using two convolutions, where xa is an information bit and xb and xc are parity bits.
  • the P / S converter Id converts the sign key data xa, xb, xc into serial data and outputs it.
  • the first element decoder DEC1 performs decoding using ya and yb among the received signals ya, yb, and yc.
  • the first element decoder DEC1 is a soft-decision output element decoder and outputs the likelihood of the decoding result.
  • the second element decoder DEC2 performs similar decoding using the likelihood and yc output from the first element decoder DEC1.
  • the second element decoder DEC2 is also an element decoder with a soft decision output, and outputs the likelihood of the decoding result.
  • the likelihood output from the first element decoder DEC1 is input to the second element decoder DEC2. Is interleaved ( ⁇ ).
  • the likelihood output from the second element decoder DEC2 is deinterleaved ( ⁇ -and then fed back as an input to the first element decoder DEC1.
  • the result is a hard decision result of “0” and “1”, and the result is a turbo decoding result (decoded data) u ′ After that, by repeating the above decoding operation a predetermined number of times, the error rate of the decoding result is reduced.
  • MAP element decoders can be used as the first and second element decoders DEC1 and DEC2 in the powerful turbo decoding unit.
  • FIG. 39 is a block diagram of a 3GPP W-CDMA mobile communication system, in which the radio base station is the transmitter in FIG. 36 and the mobile station is the receiver.
  • the mobile communication system includes a core network 11, a radio base station controller (RNC) 12, 13, multiple demultiplexers 14, 15, radio base stations (Node B) 16 to 16, mobile stations (UE: User equipment)
  • RNC radio base station controller
  • Node B radio base stations
  • UE User equipment
  • the core network 11 is a network for performing routing within the mobile communication system.
  • the core network 11 includes an ATM switching network, a packet switching network, a router network, and the like. Work can be configured.
  • the core network 11 is also connected to other public networks (PSTN) and the like so that the mobile station 7 can communicate with a fixed telephone or the like.
  • PSTN public networks
  • Radio base station controller (RNC) 12 and 13 are positioned as higher-level equipment of radio base stations 16 to 16.
  • the demultiplexers 14 and 15 are provided between the RNC and the radio base station, demultiplex signals received from the RNCs 12 and 13 to each radio base station, and output the signals to each radio base station. It performs control to multiplex the signals from the base station and deliver them to each RNC side.
  • Radio base stations 16 to 16 are radio resources by RNC12, and radio base stations 16 and 16 are radio resources by RNC13.
  • the wireless communication with the mobile station 17 is performed while the network is managed.
  • the mobile station 17 is located within the radio area of the radio base station 16, thereby establishing a radio line with the radio base station 16 and communicating with other communication devices via the core network 11. I do.
  • the above is a description of a general mobile communication system.
  • the HSDPA High Speed Downlink Packet Access
  • HSDPA adopts an adaptive coding modulation method. For example, the number of bits of transport block Tr BL, the number of multiplexed codes, and the modulation method (QPSK modulation method, 16-value QAM method) between the radio base station and the mobile station. It is characterized by adaptive switching according to the wireless environment.
  • HSDPA adopts H-ARQ (Hybrid Automatic Repeat reQuest) method.
  • H-ARQ Hybrid Automatic Repeat reQuest
  • the mobile station Since the radio base station that has received this retransmission request retransmits the data, the mobile station performs error correction decoding using both the already received data and the retransmitted received data. In this way, in H-ARQ, even if there is an error, the already received data is used effectively, so that the gain of error correction decoding increases, and as a result, the number of retransmissions can be reduced.
  • an ACK signal is received from a mobile station, data transmission is successful, so retransmission is unnecessary and the next data transmission is performed.
  • the main radio channels used in HSDPA are (1) HS-SCCH (High Speed-Shared Control Channel), (2) HS-PDSCH (High Speed-Physical Downlink Shared Channel), and (3) HS-DPCCH (High Speed-Dedicated Physical Control Channel).
  • HS-SCCH High Speed-Shared Control Channel
  • HS-PDSCH High Speed-Physical Downlink Shared Channel
  • HS-DPCCH High Speed-Dedicated Physical Control Channel
  • HS-SCCH and HS-PDSCH are common channels (shared channels) in the downlink direction, that is, in the direction from the radio base station to the mobile station.
  • HS-PDSCH is a common channel (shared channel) that transmits packets in the downlink direction.
  • HS-SCCH is a control channel that transmits various parameters related to data transmitted by HS-PDSCH. In other words, it is a channel that notifies that data transmission is performed via HS-PDSCH, and assigns destination mobile station information, transmission bit rate information, modulation method information, and spreading code as various parameters. Information such as the number (number of codes) and the pattern of rate matching performed on the transmission data.
  • HS-DPCCH is an individual control channel in the uplink direction, that is, mobile station power, radio base station direction, and results of receiving data (ACK signal, NACK signal) received via HS-PDSCH. ) Is transmitted from the mobile station to the radio base station.
  • HS-DPCCH is also used to transmit CQI (Channel Quality Indicator) to the radio base station based on the reception quality of the signal that is also received by the radio base station. Based on the received CQI, the radio base station determines whether the downlink radio environment is good or not. If it is good, the radio base station switches to a modulation method that can transmit data at a higher speed. Switching to a modulation scheme for transmitting data, thereby performing adaptive modulation.
  • CQI Channel Quality Indicator
  • transmitter 1 in FIG. 36 is a radio base station
  • receiver 2 is a mobile station (mobile terminal).
  • FIG. 41 shows a data transmission processing block of the 3GPP W-CDMA radio base station
  • FIG. 42 shows a data format for explaining the transmission processing (see Non-Patent Document 1).
  • the number of code blocks is 2, lstRM and 2nsRM in the physical layer H-ARQ function part are both puncturing and physical
  • the case where the number of channel codes is 2 will be described as an example.
  • Information bits are passed from the upper layer as a transport block (Transport Block) TB.
  • the CRC-added unit 21 performs coding for error detection by CRC (Cyclic Redundancy Check) for each transport block TB. That is, a CRC parity bit having a specified number of bits is generated based on the transport block TB and added after the transport block TB itself. '"Dataset
  • bit scrambling unit 22 performs bit scrambling on the data set D1.
  • the channel coding unit (sign key unit) 24 performs coding on each code block of the data set D3.
  • Physical layer HARQ function unit 25 performs H-ARQ processing (H-ARQ functionality) for data set D5.
  • the bit division unit 25a of the physical layer HARQ function unit 25 divides each code block output from the encoding unit 24 into a systematic bit, a NORITY bit 1, and a NORITY bit 2, and serially connects the same ones. . ... Data set D5
  • the first rate matching unit 25b of the physical layer HARQ function unit 25 checks whether the total bit length of the data set D5 is larger than the specified buffer size NIR, and punctures the data set D5 so that the size becomes NIR when it is larger. Charing is performed, and nothing is done when NIR or less. Puncturing is done for Nority 1 and Nority 2 and not for organizational bits. ⁇ ⁇ • Dataset D61
  • the second rate matching unit 25c of the physical layer HARQ function unit 25 performs rate matching (repetition or puncturing) on the data set D61 according to the designated H-ARQ transmission parameter.
  • rate matching repetition or puncturing
  • Ndata number of codes X physical channel size
  • the physical channel size is 960 for QPSK and 1920 for 16QAM.
  • the second rate matching unit 25c performs repetition so that it becomes the size of Ndata.
  • it is larger than Ndata, it is notched.
  • Repetition is a process of selecting a specified number of sign bits and creating a copy of the code bits to follow up.
  • diversity combining is performed so that the data of the same bit improves SN.
  • Puncturing is a process of selecting a specified number of bits from the sign bit and deleting the bits.
  • a fixed maximum likelihood value is added as bit data at the deletion position.
  • the modulation scheme, number of codes, RV, etc. are reported to the receiver (terminal) via another common channel HS-SCCH.
  • Physical layer HARQ function unit 25 bit combination unit 25d performs bit combination on the data set D62 and outputs the combination result. Next, the bit combining unit 25d replaces the data order in order to map the systematic bits and the parity bits into one modulation signal symbol.
  • This replacement process is a kind of interleaving.
  • Ncol the number of columns
  • Nrow Ndata / Ncol
  • Ncol 2 for QPSK
  • Ncol 4 for 16QAM.
  • the systematic bit arrangement area and the parity bit arrangement area are divided so that the systematic bit is located in the upper row. For example, for 16QAM, this placement process
  • the physical channel separation unit 26 divides the data set D7 into physical channels (Physical Channel Segmentation).
  • the number of divisions is the number of codes. Data set for this number of divisions
  • the HS-DSCH interleaving unit 27 performs H-ARQ interleaving on the data set D8. That is, the interleaving unit 27 performs interleaving on each physical channel with a prescribed interleaving pattern.
  • the constellation rearrangement unit 28 performs symbol rearrangement on the data set D9 whose modulation method is 16QAM. However, nothing when the modulation method is QPS K! /. Symbol rearrangement performs bit substitution and inversion in units of 4 bits for each symbol according to the specified parameters. ⁇ ⁇ 'Dataset D10
  • the physical channel mapping unit 29 maps the data set D10 to a physical channel (Physical Channel Mapping), and passes the physical channel data of the data set D10 as it is to the modulation unit.
  • FIG. 43 is an explanatory diagram of the encoding / decoding method proposed in Patent Document 1.
  • FIG. 43 is an explanatory diagram of the encoding / decoding method proposed in Patent Document 1.
  • Insert K0 dummy bits 200 in K information bits 100 into Kl ( ⁇ + ⁇ ) pieces of first information.
  • the dummy bits are all 1 patterns or alternating 1 and 0. 1010... 10 patterns are not limited, and a predetermined pattern can be used. Further, the dummy bit 200 can be inserted into the information bits before or after the information bits 100 or evenly. In the figure, dummy bit 200 is inserted after information bit 100.
  • the coding rate R K / (K + M).
  • the decoding unit of the receiver inserts dummy bit 200 deleted on the transmission side into demodulated systematic code 500 with maximum likelihood (reliability ⁇ ), and then performs turbo decoding to output information bit 100.
  • 44 is a configuration diagram of a communication system that realizes the encoding / decoding method of FIG. 43, and the same components as those in FIG.
  • the code part la of the transmitter 1 applies forward error correction coding (FEC) to the information bit u in order to perform transmission with high reliability, and the modulation part lb uses the code bit x of the result. Modulate and transmit to the receiver 2 through the wireless transmission path 3.
  • FEC forward error correction coding
  • the demodulator 2a of the receiver 2 demodulates the received data, and the reliability of whether the code bit is 0 or 1 and the likelihood data y with a hard decision code (+ 1 ⁇ 0, — 1 ⁇ 1) power are sent to the decoder 2b. input.
  • the decoding unit 2b performs a prescribed decoding process based on the likelihood data for each code bit, and estimates the information bit u.
  • the dummy bit deletion unit lg outputs N1 information bits X (u, a, p output from the encoder 11 ⁇ ) Power also deletes K0 dummy bits a and N information bits
  • Modulator 12 modulates this information bit x and transmits it.
  • the demodulator 2a of the receiver 20 receives the data added with noise through the transmission path 3 and demodulates it, and the likelihood data of each code bit.
  • the decoder 2e performs turbo decoding on the N1 likelihood data (y, a) and outputs an information bit estimation result.
  • decoding errors can be reduced by appropriately inserting and deleting dummy bits on the transmitting side and the receiving side.
  • the insertion position of the dummy bit Z, the coding rate should be constant or variable, whether the code block should be divided, Z, or the size after inserting the dummy bit, etc. ⁇ It is necessary to configure the device.
  • the object of the present invention is to set the dummy bit insertion Z deletion position, coding rate constant or variable Z, code block division or not Z, size after dummy bit insertion, etc. It is to provide various transmission devices in consideration.
  • Another object of the present invention is to insert dummy bits into information bits so that decoding errors can be effectively reduced.
  • Another object of the present invention is to provide a code for performing interleaving and dingtering when the code is input, for example
  • a code for performing interleaving and dingtering when the code is input for example
  • dummy bits are inserted at information bit positions that effectively reduce decoding errors in consideration of interleaving and dingtering.
  • Another object of the present invention is to insert dummy bits into information bits so that decoding errors can be reduced and the code rate is the required value.
  • Non-Patent Document 1 3GPP, TS25.212v5.9.0
  • Patent Document 1 PCT / JP2005 / 367
  • Patent Document 2 Paragraph 0104 of Special Table 2004-531972 (JP2004-531972)
  • the information bits with dummy bits inserted are systematically coded, the systematic code formed by deleting the dummy bits is transmitted, and the dummy bits deleted on the transmitting side are received on the receiving side. This is achieved by a transmission apparatus in a communication system that inserts and decodes the systematic codes.
  • the first transmission apparatus of the present invention determines the size of dummy bits to be inserted into information bits based on a specified coding rate or based on a transmission rate of a physical channel, and the information bits and the dummy bits are determined.
  • a dividing unit that divides the information bits when the total size is larger than a prescribed size, a dummy bit inserting unit that inserts dummy bits into each divided information bit, and information bits with dummy bits inserted into the systematic code
  • a systematic code generation unit that generates the systematic code by deleting the dummy bits from the systematic bits, and a transmission unit that transmits the systematic code.
  • the second transmission apparatus of the present invention determines the size of dummy bits to be inserted into information bits based on a specified coding rate or based on the transmission rate of a physical channel, and adds dummy bits to the information bits.
  • a systematic code generation unit that generates a systematic code by deleting dummy bits from the systematic bits and a transmission unit that transmits the systematic code are provided.
  • the code characteristics are improved by inserting dummy bits.
  • dummy bits can be inserted so as to obtain the required code rate or the code length corresponding to the transmission rate of the physical channel.
  • the dummy bit insertion unit inserts the same number of dummy bits at the same position of each divided information bit. In this way, the code characteristics can be improved.
  • the dummy bit insertion unit inserts dummy bits into the information bits in a uniform manner, and when the information bits are divided, the same number of dummy bits is placed at the same position of each divided information bit. To be inserted. As a result, the sign characteristic can be improved.
  • the third transmitting apparatus of the present invention is a dummy bit insertion unit that inserts a dummy bit into an information bit, generates a NOTI bit using the information bit in which the dummy bit is inserted, and uses the parity bit as the information bit.
  • a code part for outputting a systematic code in addition, a puncturing part for puncturing the NORMAL bit when the code length is larger than a prescribed size, and a systematic bit of the systematic code in parallel with the puncturing A dummy bit deleting unit for deleting the inserted dummy bits and a transmitting unit for transmitting the systematic code from which the dummy bits are deleted are provided.
  • the dummy bits can be easily deleted from the systematic bits.
  • dummy bit deletion can be performed from the yarn and weaving bits simultaneously with puncturing processing for the normative bits of the system code, so that dummy bit deletion can be prevented from affecting the total transmission processing time.
  • the fourth transmission device of the present invention is a dummy bit insertion unit that inserts a dummy bit into an information bit, generates a NORITY bit using the information bit into which the dummy bit is inserted, and is inserted into the information bit. And a transmission unit that transmits the systematic code from which the dummy bits are deleted, and a code unit that outputs the systematic codes by adding the NORMAL bits to the information bits from which the dummy bits have been deleted. /! When dummy bits are deleted inside the code part in this way, since the systematic bits are already separated, the dummy bits can be easily deleted from the systematic bits.
  • the fifth transmitting apparatus of the present invention calculates the size of the dummy bits based on the designated code rate, and when the total size of the information bits and the dummy bits is larger than a prescribed size, A dummy bit size determining unit that reduces the size of the calculated dummy bit by the difference between the size and the specified size, a dummy bit inserting unit that inserts the determined number of dummy bits into information bits, and an information bit in which dummy bits are inserted And a systematic code generator for deleting dummy bits from the systematic bits, and a transmitter for transmitting the systematic codes.
  • dummy bits can be inserted, and when the code block is divided, the maximum number of dummy bits can be inserted and processed.
  • a sixth transmitting apparatus of the present invention includes a scramble unit that scrambles information bits to which an error correction code is added, a dummy bit that inserts a dummy bit into information bits before or after the scramble process
  • An insertion unit includes a systematic code for the information bit in which the dummy bit is inserted, a systematic code generation unit that generates the systematic code by deleting the dummy bit from the systematic bit, and a transmission unit that transmits the systematic code. ing.
  • dummy bits can be inserted before bit scramble or after bit scramble.
  • a seventh transmission device of the present invention includes a dummy bit insertion unit that inserts dummy bits into information bits.
  • a systematic code generating unit that generates a systematic code by deleting a dummy bit from the systematic bit, and a transmission unit that transmits the systematic code.
  • the dummy bit insertion unit uniformly inserts the dummy bits into the information bits so that the continuous length of the dummy bits is equal to or less than the set length.
  • the decoding characteristics can be improved by uniformly inserting the dummy bits into the information bits so that the continuous length of the dummy bits is less than the set length.
  • the dummy bit insertion unit of the seventh transmitting device controls not to insert dummy bits within this range. Thereby, the decoding characteristic can be improved.
  • the bit positions that fall within the range of the specified number of bits at the beginning and end of the data after interleaving are specified in advance, and the dummy bit insertion unit inserts dummy bits at the bit positions. Control not to. This can improve the decoding characteristics.
  • ⁇ 1 It is a block diagram of the transmission processing unit of the radio base station of the first embodiment.
  • FIG. 4 is a configuration diagram of a code block dividing unit according to the first embodiment.
  • FIG. 5 is a configuration diagram of a turbo coding unit.
  • FIG. 6 is an explanatory diagram of dummy bit insertion processing of the radio base station according to the second embodiment.
  • FIG. 7 is a block diagram of the main part of a second embodiment.
  • FIG. 8 shows a dummy bit insertion process flow of the second embodiment.
  • FIG. 10 is a flowchart of dummy bit insertion processing in the second embodiment.
  • FIG. 13 is a flowchart of dummy bit insertion processing in the third embodiment.
  • FIG. 15 is a flowchart of dummy bit insertion processing in the fourth embodiment.
  • FIG. 17 is a flowchart of dummy bit insertion processing in the fifth embodiment.
  • FIG. 19 is a principal block diagram of a transmission processing unit of a sixth embodiment.
  • FIG. 20 is a flowchart of dummy bit insertion processing in the sixth embodiment.
  • FIG. 22 is a principal block diagram of a transmission processing unit according to the seventh embodiment.
  • FIG. 23 is a flowchart of dummy bit insertion processing in the seventh embodiment.
  • FIG. 24 is an example in which the dummy bit value is a random pattern in the seventh embodiment.
  • FIG. 25 is an example of a dummy bit insertion pattern in the eighth embodiment.
  • FIG. 28 shows required Eb / N0 characteristics (decoding characteristics) with respect to the coding rate.
  • FIG. 29 is a block diagram of a transmission processing unit in a radio base station according to the ninth embodiment.
  • FIG. 30 is an explanatory diagram of dummy bit insertion positions according to the tenth embodiment.
  • FIG. 31 is a flowchart for changing dummy bit positions in the tenth embodiment.
  • FIG. 33 is a block diagram of a turbo encoder of an eleventh embodiment.
  • FIG. 34 is a block diagram of a turbo decoding unit in an eleventh embodiment.
  • FIG. 36 is a configuration diagram of a conventional communication system in which block coding is performed at a transmitter and decoding is performed at a receiver.
  • FIG. 37 is a block diagram of a turbo encoding unit.
  • FIG. 38 is a block diagram of a turbo decoding unit.
  • FIG. 39 is a block diagram of a 3GPP W-CDMA mobile communication system.
  • FIG. 40 is an explanatory diagram of common channels in HSDPA.
  • FIG. 41 is a block diagram of a transmission processing unit of a 3GPP W-CDMA radio base station.
  • FIG. 42 is a data format describing transmission processing.
  • FIG. 43 is an explanatory diagram of an encoding / decoding method using dummy bits.
  • 44 is a configuration diagram of a communication system that realizes the encoding / decoding method of FIG. 43.
  • FIG. 1 is a configuration diagram of the transmission processing unit 30 of the radio base station according to the first embodiment, and the same parts as those of the conventional transmission processing unit of FIG.
  • the transmission processing unit 30 transmits information (packets) to the mobile station using the HSDPA common channel HS-PDSCH.
  • the transmission processing unit 30 includes a CRC adding unit 21, a bit scrambling unit 22, a code block dividing unit 23, a dummy bit inserting unit 31, a channel coding unit (code unit) 24, a physical layer HAR Q function unit 25, and physical channel separation.
  • Unit 26 HS-DSCH interleaving unit 27, constellation rearrangement unit 28, physical channel mapping unit 29, and transmission unit 32 for transmitting information.
  • the dummy bit insertion unit 31 is provided between the code block division unit 23 and the code key unit 24. And dummy bits are inserted into the information bits.
  • the physical layer HARQ function unit 25 includes a bit dividing unit 25a, a first rate matching unit 25b, a second rate matching unit 25c, and a bit combining unit 25d.
  • the first rate matching unit 25b includes a dummy bit deletion unit 25b-3 that deletes a dummy bit from the systematic bits in addition to the rate matching processing units 25b-1 and 25b-2 of the norms 1 and 2.
  • the matching unit 25c includes the rate matching processing units 25c-1 and 25c-2 for the norms 1 and 2, and the rate matching processing unit 25c-3 for the systematic bits.
  • the dummy bit deleting unit 25b-3 deletes the dummy bit bit inserted into the systematic bit by the dummy bit inserting unit 31.
  • the first rate matching unit 25b has passed through the organization bits without any processing.
  • the rate matching processing units 25b-l and 25b-2 puncture the parity bits 1 and 2.
  • dummy bit deletion unit 25b-3 performs dummy bit deletion processing.
  • FIG. 2 is an explanatory diagram of dummy bit insertion processing
  • FIG. 3 is an explanatory diagram of dummy bit deletion processing.
  • the coding rate R when transmitting with the dummy bit deleted is the turbo code.
  • K0 (K-3KR) / 2R (2)
  • the dummy bit insertion unit 31 inserts a dummy bit of size K0 / 2 into each code block ((b) in FIG. 2, the code input unit 24 encodes each code block in which the dummy bit is inserted. For example, turbo coding is performed ((c) in FIG. 2).
  • the bit division unit 25a of the physical layer HARQ function unit 25 converts the code of each code block output from the code unit unit 24 into (1) system bit + dummy bit, (2) parity bit 1, and (3) parity bit 2. The same items are connected serially (see (a) in Fig. 3).
  • the first rate matching unit 25b of the physical layer HARQ function unit 25 checks whether the total bit length of the data set D5 is larger than the specified buffer size NIR, and when it is larger, the parity 1 and the normity are set so that the size becomes NIR. Puncture 2 and simultaneously delete the dummy bits from the systematic bits (Fig. 3 (b)).
  • the second rate matching unit 25c of the physical layer HARQ function unit 25 performs the rate for the data set D6 1 of systematic bits, norities 1 and 2 shown in Fig. 3 (b) according to the specified H-ARQ transmission parameters. Perform matching (repetition or puncturing). Thereafter, the same processing as in the prior art is performed to transmit a systematic code formed by deleting dummy bits. On the receiving side, the systematic code is received, and dummy bits deleted on the transmitting side are inserted into the received systematic code with maximum likelihood, and turbo decoding is performed to obtain information bits.
  • HSDPA High Speed Downlink Packet Access
  • information necessary for reception (destination, modulation method, dummy bit size, dummy bit insertion method, etc.) is notified to the receiving device in advance by the common channel HS-SCCH as necessary. Therefore, since the dummy bit insertion position on the transmission side is known in the receiving apparatus, the dummy bit with the maximum likelihood is inserted into the position for decoding.
  • Fig. 4 is a block diagram of the code block division unit 23.
  • the dummy bit size calculation unit 23a calculates the dummy bit size K0 based on the specified code rate R, and the number of code blocks / code block size
  • the division unit 23c The scrambled data set D2 is divided into the specified number of divisions, the dummy bit insertion unit 31 inserts dummy bits of size K0 / 2 into each code block, and the code part 24 has dummy bits inserted. For each code block Perform B-encoding.
  • dummy bits are inserted into information bits, a parity bit generated from the information bits is added to the information bits, and turbo coding is performed. Is transmitted by receiving the systematic code, and receiving the systematic code on the receiving side, and inserting the dummy bit deleted on the transmitting side with the maximum likelihood into the received systematic code and performing turbo decoding. Decoding errors can be reduced.
  • the dummy bit deleting unit 25b-3 is already separated into yarn and weave bits, so that the dummy bits can be easily deleted from the texture bits.
  • dummy bit deletion can be performed simultaneously with puncturing for parity bits 1 and 2, so dummy bit deletion does not affect the total transmission processing time.
  • Fig. 5 is a block diagram of the turbo encoder 24, where 24a is a first element encoder that encodes information bits with dummy bits inserted, and 24b is an interleaver that interleaves information bits with dummy bits inserted. 24c is a second element encoder that encodes the interleave result, 24d is a dummy bit deletion section that deletes dummy bits, and 24e is the output of each element encoder 24a, 24b and dummy bit deletion section 24c to serial data. It is a P / S converter that converts and outputs. If the dummy bits are deleted in the turbo coding part as described above, the dummy bits can be easily deleted from the systematic bits because they are already separated into systematic bits.
  • Ndata is the number of codes x physical channel size.
  • FIG. 6 is an explanatory diagram of dummy bit processing of the radio base station of the second embodiment, and the configuration of the transmission processing unit has the same configuration as that of the first embodiment of FIG.
  • the first rate matching unit 25b of the physical layer HARQ function unit 25 checks whether the bit length of the code is larger than the specified buffer size NIR, and if it is larger, the first rate matching unit 25b punctures the parity 1 and the norm 2 so that the size becomes NIR. Performs a tour and at the same time deletes the dummy bits from the systematic bits.
  • the second rate matching unit 25c of the physical layer HARQ function unit 25 performs rate matching (repetition or puncturing) so that the code length is Ndata ((d) in FIG. 6).
  • the receiving side receives the systematic code, inserts the dummy bit deleted on the transmitting side with the maximum likelihood into the received systematic code, performs turbo decoding, and obtains information bits.
  • FIG. 7 is a principal block diagram of the transmission processing unit of the second embodiment, and the same reference numerals are given to the same parts as those of the first embodiment of FIG. The difference is that a physical layer HARQ function unit 25 having a dummy bit deletion unit and a second rate matching unit is added.
  • FIG. 8 is a flowchart of dummy bit insertion processing in the second embodiment.
  • FIG. 9 is an explanatory diagram of a dummy bit insertion method after code division. Insert dummy bits In this case, the same number of dummy bits is uniformly allocated for each code block, and the dummy bit insertion position and dummy bit value (0, 1) are made the same.
  • Figure 8 shows the case where dummy bits are inserted after code block division, but dummy bits are inserted before code block division, and when division is necessary, the dummy bits are distributed evenly in each code block. Code blocks can also be divided.
  • Fig. 10 shows the powerful dummy bit insertion processing flow of the second embodiment, in which dummy bit insertion processing (step 511) is arranged before processing step 503 for comparing the size of the total size K1 and the specified size Z. is doing.
  • Fig. 11 is an explanatory diagram of an insertion method for inserting dummy bits before code division. When code blocks are divided, the dummy bit distribution is uniform in each code block and the dummy bit insertion positions are uniform. To be.
  • the dummy bit size is determined so that the required code rate is obtained, and the rate matching is performed so that the Ndata given by the H-ARQ transmission parameter is obtained. be able to.
  • decoding characteristics can be improved by inserting dummy bits uniformly.
  • the dummy bit insertion method shown in FIGS. 9 and 11 is not limited to the second embodiment but can be applied to all embodiments.
  • FIG. 12 is an explanatory diagram of the dummy bit insertion process of the third embodiment
  • FIG. 13 is a dummy bit insertion process flow
  • the configuration of the transmission processing unit is the same as that of the first embodiment of FIG.
  • the code block dividing unit 23 calculates the dummy bit size K0 to be inserted so that the total bit length is equal to Ndata (step 551).
  • the code size when the dummy bit of size K0 is inserted into the information bit of size K to perform turbo coding, and the dummy bit is deleted and transmitted is K + 2 (K + K0). Therefore, the following formula
  • Ndata ⁇ + 2 ( ⁇ + ⁇ 0) (3)
  • the code key unit 24 performs a code key, for example, turbo code key, on each code block in which dummy bits are inserted ((c) in FIG. 12, step 557). Also, the physical layer HARQ function unit 25 deletes the dummy bits from the systematic bits ((d) in FIG. 12, step 558). Since the code length after deleting the dummy bits is equal to Ndata, the physical layer HARQ function unit 25 does not perform rate matching (repetition or puncturing)!
  • a code key for example, turbo code key
  • FIG. 14 is an explanatory diagram of dummy bit insertion processing of the fourth embodiment
  • FIG. 15 is a dummy bit insertion processing flow
  • ⁇ 0 ⁇ 0- ⁇ ⁇
  • Step 605 After that, a dummy bit of size ⁇ 0 is inserted into the information bit of size ⁇ (Fig. 14 (a), step 604).
  • the code unit 24 performs encoding, for example, turbo coding on the code block in which the dummy bits are inserted (FIG. 14 (b), step 606). ).
  • the physical layer HARQ function unit 25 deletes the dummy bits from the systematic bits and performs rate matching processing so that the code length is equal to Ndata ((c) in FIG. 14, step 607).
  • the maximum number of dummy bits can be inserted and the code length can be set to Ndata for transmission. For this reason, the dummy insertion effect can be enhanced without dividing the code block.
  • FIG. 16 is an explanatory diagram of dummy bit insertion processing of the fifth embodiment
  • FIG. 17 is a dummy bit insertion processing flow
  • the configuration of the transmission processing unit is the same as that of the first embodiment of FIG.
  • the code block division unit 23 determines the dummy bit size K0 by the equation (2) so that the prescribed code rate R is obtained (step 651), and the total size of the information bit size K and the dummy bit size K0.
  • step 654 insert a dummy bit of size K0 into the information bit of size K (step 654). Dummy bits can be inserted so that the code block size becomes the specified size.
  • K1> Z the number of code blocks / code block size is determined, and code blocks are divided ((a) in FIG. 16, step 655).
  • filler bits are inserted (step 656), dummy bits are inserted in each code block so that the size is the prescribed size Z ((b) in FIG. 16, step 657), and the dummy bit insertion processing is terminated.
  • the code key unit 24 performs, for example, turbo code keying on each code block in which dummy bits are inserted ((c) of FIG. 16).
  • the physical layer HARQ function unit 25 deletes dummy bits from the systematic bits and performs rate matching processing so that the code length is equal to Ndata. Thereafter, processing similar to that in the prior art is performed, and a systematic code not including dummy bits is transmitted. On the receiving side, the systematic code is received, and a dummy bit deleted on the transmitting side is inserted into the received systematic code with maximum likelihood, and turbo decoding is performed to obtain information bits.
  • dummy bits are inserted and signed so that the total size of the dummy bits and the information bits becomes the specified size Z, and the dummy bits are deleted. Can be sent.
  • the dummy bit size to be inserted can be increased, the dummy insertion effect can be enhanced.
  • the sixth embodiment is an embodiment in which dummy bits are inserted before bit scrambling.
  • FIG. 18 is an explanatory diagram of dummy bit insertion
  • FIG. 19 is a main block diagram of a transmission processing unit
  • FIG. 20 is a dummy bit ⁇ . It is an incoming process flow.
  • the dummy bit size calculation unit 31a of the dummy bit insertion unit 31 determines the dummy bit size K0 according to equation (2) so that the specified coding rate R is obtained (step 701), and the information bit size K and the dummy bit are determined.
  • the bit scrambler 22 bit-scrambles the information bits in which the dummy bits are inserted and inputs the information bits to the code block divider 23 ((c) in FIG. 18, step 704).
  • the number of code blocks / code block size determining unit 23b of the code block dividing unit 23 compares the size of the bit-scrambled data set D2 (total size of information bits and dummy bits) K1 with the size of the specified size ⁇ (step 705).
  • the code is not divided. If ⁇ 1> ⁇ , the number of code blocks / code block size is determined, and the dividing unit 23c divides the code block (step 706). Next, a filler bit is inserted (step 707).
  • the code unit 24 performs turbo encoding for each code block in which the dummy bits are inserted, and the physical layer HARQ function unit 25 deletes the dummy bits and performs predetermined encoding.
  • the rate matching process is performed, and the yarn and weaving code including dummy bits is transmitted.
  • the systematic code is received, and dummy bits deleted on the transmitting side are inserted into the received systematic code with maximum likelihood, and turbo decoding is performed to obtain information bits.
  • dummy bits can be inserted before bit scrambling.
  • the seventh embodiment is an embodiment in which dummy bits are inserted after bit scrambling.
  • FIG. 21 is an explanatory diagram of dummy bit insertion
  • FIG. 22 is a main block diagram of a transmission processing unit
  • FIG. 23 is a dummy bit insertion processing flow. is there.
  • the bit scrambler 22 adds a bit scramble process to the information bit ((a) of FIG. 21) CRC-added by the CRC adder 21 ((b) of FIG. 21, step 751).
  • the code block number / code block size determining unit 23b of the code block dividing unit 23 compares the total size K1 of the information bits and the dummy bits with the size of the specified size Z (step 755). If K1 ⁇ Z, code is not divided, while if ⁇ 1> ⁇ , the number of code blocks / code block The division unit 23c divides the code block (step 756). Next, the file bit is inserted (step 757).
  • the code unit 24 performs turbo encoding for each code block in which the dummy bits are inserted, and the physical layer HARQ function unit 25 deletes the dummy bits and performs predetermined encoding.
  • the rate matching process is performed, and a systematic code including dummy bits is transmitted.
  • the systematic code is received, and dummy bits deleted at the transmitting side are inserted into the received systematic code with maximum likelihood and turbo decoding is performed to obtain information bits.
  • all of the dummy bits are inserted by the insertion section 31, but the value of the dummy bits can be a random pattern as shown in FIG. 24 (c).
  • dummy bits can be inserted after bit scrambling.
  • the eighth embodiment is an embodiment of an insertion pattern of dummy bits into information bits. As shown in Fig. 25 (a), the pattern in which the yarn and weave bits and the dummy bits are alternately arranged as the insertion pattern is different from the pattern in which the dummy bits are arranged in one place before and after the information bits. The decoding characteristics can be improved.
  • the alternating pattern is the case where the size of the systematic bit and dummy bit are the same, and cannot be alternately arranged if they are different. Therefore, dummy bits are inserted into systematic bits so as to allow the dummy bits to continue for a specified length. In this way, even if the dummy bits are arranged in a distributed manner by setting the continuous length of the dummy bits to be equal to or less than the set value, decoding characteristics (decoding error characteristics) can be improved. For example, when the information bits and dummy bits are the same size and the continuous length is 2, as shown in Fig. 15 (b), 2 information bits and 2 dummy bits are alternately arranged. When the continuous length is 3, as shown in Fig. 15 (c), 3 information bits and 3 dummy bits are alternately arranged.
  • Dummy bits are input to the STA and TLA around the beginning or end of information as shown in Fig. 26.
  • bit positions A1 to A4 that are located at a specified number of positions at the beginning and the end of the data after interleaving are specified in advance from the internal interleaving pattern of the turbo code.
  • dummy bits are not inserted into these positions A1 to A4. The reason is the same as in Figure 26.
  • the 3GPP turbo code has a feature that when the code rate becomes a specific value due to puncturing, the characteristic degradation locally increases compared to the surrounding code rate.
  • Fig. 28 is an explanatory diagram showing such characteristic degradation, where A is the decoding characteristic without dummy bit insertion, the horizontal axis is the coding rate, and the vertical axis is the required Eb / No for obtaining a predetermined error rate. It is. As is apparent from this decoding characteristic, when the coding rate reaches a specific value (7/11, 7/9, 7/8), the required Eb / No becomes larger than the surrounding coding rate and the characteristic deteriorates. To do.
  • the ninth embodiment it is monitored whether the sign rate after puncturing has become a value close to a specific value (a value in the specific range S1 to S3), and when it becomes a value in the specific range S1 to S3, Dummy bits are inserted before puncturing and the decoding characteristics are shifted as indicated by B, so that the code rate is outside the specific range SI 'to S3' determined by the decoding characteristics B.
  • the dummy bit insertion amount is determined so that it is just outside the peak area of the characteristic B peak after the shift.
  • the transmission processing unit 30 includes a CRC adding unit 21, a bit scramble unit 22, a code block dividing unit 23, a dummy bit insertion control unit 41, Channel coding unit (code unit) 24, physical layer HARQ function unit 25, physical channel separation unit 26, HS-DSCH interleaving unit 27, constellation relocation unit 28, physical channel mapping unit 29, transmission unit (not shown) )).
  • the dummy bit insertion control unit 41 checks whether or not the calculated sign rate R has a value within the range of S1 to S3 with a specific value 7/11, 7/9, 7/8 as the center. (Step 802). If the value is not within the range, the dummy bit insertion control unit 41 does not insert the dummy bit. If the value is within the range, the decoding characteristic is shifted from A to B, and the code rate is within a specific range. Dummy bits are inserted into the information bits so as to have values outside SI 'to S3' (step 803).
  • the deterioration of the decoding characteristics can be prevented.
  • first input When a turbo code is used as a code, dummy bit insertion positions in both the input bits (referred to as “first input” and “second input”, respectively) of the first and second component encoders of the turbo encoder. If the pattern is made as uniform as possible, the decoding characteristics can be improved.
  • An arrangement in which the positions of the information bits of the first and second inputs are equal is the ideal arrangement. If ⁇ 0> ⁇ and there are more dummy bits than information bits, in principle, at least two dummy bits will be adjacent. In this case, the uniformity is achieved by switching the positions of dummy bits and information bits.
  • the position Q (d) ⁇ l on both sides of the position Q (d) is currently an information bit, but the bit position of the second input corresponding to these (P (Q (d) + l ), P (Q (d) -l)), when the dummy bit is inserted, the burst length of the generated dummy bit is short, and the bit position is selected (in the figure, P (Q (d) 30), the dummy bit at position Q (d) and the information bit at position Q (d) +1 at the first input are swapped as shown in FIG.
  • Position Q (d) is changed from a dummy bit to an information bit, and position Q (d) +1 is changed from an information bit to a dummy bit, so that the dummy bit at the second input after interleaving is changed.
  • Continuous length can be 2 or less.
  • Fig. 31 shows the flow of an efficient algorithm for changing dummy bit positions so that the conditions described in Fig. 30 are satisfied.
  • Each bit is associated with a weight variable W (i) as shown in FIG.
  • step 904 it is checked whether W (i) ⁇ Th (step 904). If W (i) ⁇ Th, position i is set as a dummy bit position (step 905), and the weight variable is updated as follows (step 906).
  • the insertion position of the dummy bit is determined by the above algorithm so that the continuous length of the dummy bit does not become long.
  • the dummy bit insertion position is sequentially determined, and the weights immediately adjacent to the determined dummy bit position and the next adjacent weight are increased at both the first and second inputs to obtain dummy bit positions. It is selected so that the continuous length of dummy bits is not increased.
  • the tenth embodiment is not limited to the above algorithm as long as the algorithm makes the dummy bit insertion pattern as uniform as possible in both the first and second inputs. Can be adopted.
  • the size of the dummy bit to be inserted into the information bits is determined based on the designated code rate, as described in the second embodiment.
  • the size K0 of the dummy bit to be inserted is calculated so that the code size is equal to the bit length Ndata determined from the transmission rate of the physical channel.
  • the method of the tenth embodiment has a problem that the position generation algorithm is complicated, and the processing amount and processing time are increased.
  • the dummy bit insertion positions are easily varied as much as possible at both the first and second inputs of the first and second element codes.
  • FIG. 33 is a block diagram of the turbo encoder of the eleventh embodiment.
  • the first element encoder 24a encodes information bits with dummy bits inserted, and the interleave unit 24b has information with dummy bits inserted.
  • the bits are interleaved
  • the second element encoder 24c encodes the interleave result
  • the P / S converter 24e converts the output xb, XC and information bit xa of each element encoder 24a, 24b into serial data.
  • the first and second dummy bit insertion sections 51 and 52 insert dummy bits into the first and second inputs which are the inputs of the first and second element encoders 24a and 24b.
  • it is inserted in such a way that it is as uniform as possible in both the first and second inputs.
  • the dummy bit size K0 to be inserted is based on the specified coding rate according to the expression (2) or as described in the third embodiment. Calculated by Eq. (4) so as to be equal to the bit length Ndata determined by the channel transmission rate
  • the first and second elements are the power element encoders with two element encoders. Code processing can be performed.
  • FIG. 34 shows a turbo on the receiving side that decodes the turbo code encoded by the encoder of FIG. It is a block diagram of a decoding part.
  • the first element decoder 61 uses ya and yb among the received signals ya, yb, and yc to perform decoding.
  • the first element decoder 61 is an element decoder with a soft decision output, and outputs the likelihood of the decoding result.
  • the first dummy bit deleting unit 62 deletes the first dummy bit from the decoding result of the first element decoder 61, and the interleaving unit 63 interleaves the decoding result from which the dummy bit is deleted, and inserts the second dummy bit.
  • Unit 64 inserts the second dummy bit with the maximum likelihood into the interleaved decoding result.
  • the second element decoder 65 performs decoding using the decoding result of the first element decoder 61 subjected to the interleaving and second dummy bit insertion processing and the received signal yc.
  • the second element decoder 65 is also an element decoder with a soft decision output, and outputs the likelihood of the decoding result.
  • the second dummy bit deletion unit 66 deletes the second dummy bit as well as the decoding result power of the second element decoder 65, and the de-interleaving unit 67 de-interleaves the decoding result from which the dummy bit is deleted.
  • the bit insertion unit 68 inserts the first dummy bit having the maximum likelihood into the ding-terminated decoding result and inputs it to the first element decoder 61.
  • the first element decoder 61 repeats the above MAP decoding process using the output signal of the first dummy bit insertion unit 68 instead of the received signal ya. By repeating the above decoding operation a predetermined number of times, the error rate of the decoding result is reduced.
  • the MAP element decoder is used as the first and second element decoder in the powerful turbo element decoder.
  • the first and second element decoding processes can be performed by a power decoder having two element decoders. Similarly, it is possible to perform the first and second dummy bit deletion processing and the first and second dummy bit insertion processing by one dummy bit deletion unit and one dummy bit insertion unit. Monkey.
  • the eleventh embodiment it is possible to take insertion positions independent of each other at both the input of the first element encoder 24a and the second element code 24c. It becomes possible to select. Further, the dummy bit deletion unit is not necessary.
  • a dummy bit is inserted into an information bit, a parity bit created from the information bit is added to the information bit and turbo coding is performed, and the turbo coding power also deletes the dummy bit.
  • the system receives the systematic code, receives the systematic code at the receiving side, inserts dummy bits deleted at the transmitting side into the received systematic code with maximum likelihood, and decodes by decoding the error. Can be reduced.
  • dummy bits can be easily deleted from the systematic bits by providing the dummy bit deletion unit in the physical layer HARQ function unit or the code unit. Further, according to the present invention, it is possible to perform processing for deleting dummy bits from systematic bits at the same time as puncturing processing for notation bits of systematic codes. Therefore, dummy bit deletion can be performed without affecting the total transmission processing time.
  • the present invention it is possible to determine the size of the dummy bits so that the required code rate is obtained, and to perform transmission by rate matching so as to be Ndata given by the H-ARQ transmission parameter. .
  • the decoding characteristics can be improved by inserting dummy bits uniformly.
  • transmission can be performed by inserting dummy bits such that the code rate R is variable and the code length is equal to Ndata.
  • the maximum number of dummy bits can be inserted and the code length can be transmitted as Ndata. For this reason, the dummy insertion effect can be enhanced without dividing the code block.
  • each code block dummy bits are inserted and encoded so that the total size of the dummy bits and the information bits becomes the prescribed size Z, and the dummy bits are deleted and transmitted. Therefore, since the dummy bit size to be inserted can be increased, the dummy insertion effect can be enhanced.
  • dummy bits can be inserted before bit scrambling or after bit scrambling.
  • the dummy bits are distributed by setting the continuous length of the dummy bits below the set value. Decoding characteristics can be improved because it is inserted into the information bits. Also, since the dummy bits are distributed and inserted into the information bits excluding the periphery of the beginning or end of the information bits, the decoding characteristics
  • the decoding characteristics can be improved because the dummy bits are inserted in a distributed manner by excluding the bit positions that follow the information after interleaving.
  • the coding rate must be a specific value that degrades the decoding characteristics! Since dummy bits are inserted like this, decoding characteristics can be prevented from deteriorating.
  • the pattern of the dummy bit insertion position should be the same in both the first and second inputs which are the inputs of the first element encoder and the second element encoder. As a result, the decoding characteristics can be improved.
  • the dummy bit insertion position when the turbo code is employed, the dummy bit insertion position can be determined without depending on the first and second inputs of the first element encoder and the second element code. Therefore, the dummy bit insertion position pattern can be easily made uniform at the first and second inputs, and the decoding characteristics can be improved.
  • a dummy bit is inserted in the turbo encoder to generate a NORITY bit, and a turbo code can be output without inserting a dummy bit into the yarn and weaving bit. It is possible to eliminate the need for a dummy bit deletion unit for deleting.

Abstract

Appareil de transmission d’un système de communication dans lequel des bits d’information parmi lesquels des bits leurre ont été insérés sont codés de façon organisationnelle et où les codes organisationnels dont les bits leurre ont été supprimés sont ensuite transmis ; et dans lequel, à une extrémité de réception, les bits leurre supprimés à l’extrémité de transmission sont insérés dans les codes organisationnels reçus puis décodés. Dans l’appareil de transmission, une partie d’insertion de bits leurre décide, en fonction d’un taux de codage ou d’une vitesse de transmission désignés d’un canal physique, la taille en bits leurre à insérer dans les bits d’information, puis insère uniformément les bits leurre dans les bits d’information selon la taille décidée. Puis, une partie de génération de code organisationnel code de façon organisationnelle les bits d’information parmi lesquels les bits leurre ont été insérés et supprime les bits leurre des bits organisationnels pour générer le code organisationnel à transmettre.
PCT/JP2005/014823 2005-08-12 2005-08-12 Appareil de transmission WO2007020677A1 (fr)

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JP2007530861A JP4717072B2 (ja) 2005-08-12 2005-08-12 送信装置
CN2005800502632A CN101208865B (zh) 2005-08-12 2005-08-12 发送装置
EP05780307A EP1914897A4 (fr) 2005-08-12 2005-08-12 Appareil de transmission
EP12179263A EP2521270A1 (fr) 2005-08-12 2005-08-12 Appareil émetteur
PCT/JP2005/014823 WO2007020677A1 (fr) 2005-08-12 2005-08-12 Appareil de transmission
US12/068,717 US8181099B2 (en) 2005-08-12 2008-02-11 Transmission device
US13/345,969 US8234557B2 (en) 2005-08-12 2012-01-09 Transmission device
US13/444,358 US8458579B2 (en) 2005-08-12 2012-04-11 Transmission device

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EP1914897A1 (fr) 2008-04-23
US20080141104A1 (en) 2008-06-12
CN101208865B (zh) 2012-10-03
US8234557B2 (en) 2012-07-31
CN101208865A (zh) 2008-06-25
EP1914897A4 (fr) 2012-01-11
US20120204083A1 (en) 2012-08-09
JP4717072B2 (ja) 2011-07-06
US20120110422A1 (en) 2012-05-03
EP2521270A1 (fr) 2012-11-07
US8181099B2 (en) 2012-05-15
JPWO2007020677A1 (ja) 2009-02-19

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