WO2007004843A1 - Method for forming multi-layered binary oxide film for use in resistance random access memory - Google Patents

Method for forming multi-layered binary oxide film for use in resistance random access memory Download PDF

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Publication number
WO2007004843A1
WO2007004843A1 PCT/KR2006/002610 KR2006002610W WO2007004843A1 WO 2007004843 A1 WO2007004843 A1 WO 2007004843A1 KR 2006002610 W KR2006002610 W KR 2006002610W WO 2007004843 A1 WO2007004843 A1 WO 2007004843A1
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Prior art keywords
metal layer
oxide film
forming
binary oxide
layered
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PCT/KR2006/002610
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French (fr)
Inventor
Jin-Pyo Hong
Young-Ho Do
Kap-Soo Yoon
Koo-Woong Jeong
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Industry-University Cooperation Foundation Hanyang University
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Priority to EP06769167A priority Critical patent/EP1905086B1/en
Priority to US11/994,551 priority patent/US20080200003A1/en
Priority to JP2008520178A priority patent/JP2009500845A/en
Publication of WO2007004843A1 publication Critical patent/WO2007004843A1/en

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    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01B—NON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
    • C01B13/00—Oxygen; Ozone; Oxides or hydroxides in general
    • C01B13/14—Methods for preparing oxides or hydroxides in general
    • C01B13/34—Methods for preparing oxides or hydroxides in general by oxidation or hydrolysis of sprayed or atomised solutions
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01F—COMPOUNDS OF THE METALS BERYLLIUM, MAGNESIUM, ALUMINIUM, CALCIUM, STRONTIUM, BARIUM, RADIUM, THORIUM, OR OF THE RARE-EARTH METALS
    • C01F17/00—Compounds of rare earth metals
    • C01F17/30—Compounds containing rare earth metals and at least one element other than a rare earth metal, oxygen or hydrogen, e.g. La4S3Br6
    • C01F17/32—Compounds containing rare earth metals and at least one element other than a rare earth metal, oxygen or hydrogen, e.g. La4S3Br6 oxide or hydroxide being the only anion, e.g. NaCeO2 or MgxCayEuO
    • C01F17/34—Aluminates, e.g. YAlO3 or Y3-xGdxAl5O12
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01P—INDEXING SCHEME RELATING TO STRUCTURAL AND PHYSICAL ASPECTS OF SOLID INORGANIC COMPOUNDS
    • C01P2002/00—Crystal-structural characteristics
    • C01P2002/30—Three-dimensional structures
    • C01P2002/34—Three-dimensional structures perovskite-type (ABO3)
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01P—INDEXING SCHEME RELATING TO STRUCTURAL AND PHYSICAL ASPECTS OF SOLID INORGANIC COMPOUNDS
    • C01P2002/00—Crystal-structural characteristics
    • C01P2002/50—Solid solutions
    • C01P2002/52—Solid solutions containing elements as dopants
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01P—INDEXING SCHEME RELATING TO STRUCTURAL AND PHYSICAL ASPECTS OF SOLID INORGANIC COMPOUNDS
    • C01P2004/00—Particle morphology
    • C01P2004/01—Particle morphology depicted by an image
    • C01P2004/03—Particle morphology depicted by an image obtained by SEM
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01P—INDEXING SCHEME RELATING TO STRUCTURAL AND PHYSICAL ASPECTS OF SOLID INORGANIC COMPOUNDS
    • C01P2004/00—Particle morphology
    • C01P2004/30—Particle morphology extending in three dimensions
    • C01P2004/32—Spheres
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01P—INDEXING SCHEME RELATING TO STRUCTURAL AND PHYSICAL ASPECTS OF SOLID INORGANIC COMPOUNDS
    • C01P2004/00—Particle morphology
    • C01P2004/51—Particles with a specific particle size distribution
    • C01P2004/52—Particles with a specific particle size distribution highly monodisperse size distribution
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01P—INDEXING SCHEME RELATING TO STRUCTURAL AND PHYSICAL ASPECTS OF SOLID INORGANIC COMPOUNDS
    • C01P2004/00—Particle morphology
    • C01P2004/60—Particles characterised by their size
    • C01P2004/64—Nanometer sized, i.e. from 1-100 nanometer

Definitions

  • the invention relates to a method for growing a multi-layered binary oxidation film for use in a Resistance Random Access Memory (ReRAM), and more particularly, a method for growing a binary oxidation film with excellent uniformity and reproducibility.
  • ReRAM Resistance Random Access Memory
  • Flash memory which is the most representative of nonvolatile memory, requires high operational voltage to write or erase data. Therefore, in case when the gate length is decreased to 65nm or less, adjacent cells may be operated, thus causing confusion between cells, which raises a question whether the actual realization is possible. In addition, sufficient device margin is not ensured when operated at low voltage required for low-power consumption. Therefore, there is a need for rearch on the next- generation nonvolatile memory.
  • Resistance Random Access Memory (hereinafter, referred to as 'ReRAM ) is a nonvolatile memory device based on drastic resistance change in a thin film with particular voltage applied to the thin film.
  • Other nonvolatile memories have limitations. For example, DRAM is limited in scale-down (decrease in the gate length), FRAM is unstable in its material, flash memory exhibits low speed and high power consumption, and MRAM entails a complex process, multi-layer structure and small read/write margin.
  • ReRAM has excellent characteristics such as infinite recording and reproduction, operability at high temperature, and nonvolatile characteristics ensuring safety of data. Also, it can operate at high speed of 10 to 20ns (nanoseconds) and can achieve high integration and speed since it is a single-film structure in terms of process. It is manufactured basically as a single-layer structure, which can be conducted by CMOS and integration processes, thereby minimizing energy consumption.
  • Korean Patent Application No. 2004-0080999 discloses a method of applying a
  • the application method includes forming a barrier layer in a thickness of 10 to lOOnm, depositing a layer of iridium on the barrier layer, spin coating a layer of PCMO (Pr Ca MnO ) on the iridium, baking the PCMO and substrate in a three-step baking process, post-baking annealing the substrate and the PCMO in a RTP chamber, repeating the spin coating, baking and annealing steps until the PCMO has a desired thickness, annealing the substrate and PCMO, and depositing a top electrode and complete the ReRAM device.
  • PCMO Pr Ca MnO
  • the present invention has been made to solve the foregoing problems of the prior art and therefore an object of certain embodiments of the present invention is to provide a method for forming an oxidation film for use in a ReRAM in a simple process without a problem of surface contamination.
  • a method for forming a multi-layered binary oxide film for use in a resistance random access memory comprising steps of:
  • the lower electrode layer and the upper electrode layer is made of one selected from a group consisting of Pt, Au, Al, Cu, Ti and alloys thereof. It is preferable that the metal layer is made of one selected from a group consisting of Al, Co, Ni, Fe, Ta, Ti, Au, Pt, Ag and alloys thereof. Preferably, the metal layer has a thickness ranging from 5 to IOOA and more preferably, 0-50A
  • the step (iii) comprises remote oxidation with 0% to 90% of Ar gas and 10% to 100% of O gas, with RF plasma at an output of 30W to 200W.
  • the multi-layered binary oxidation film is annealed at a temperature ranging from 100 0 C to 1000 0 C for 1 minute to 24 hours.
  • a metal layer is formed and oxidized in a vacuum atmosphere, and thus a binary oxide film can be formed in multi-layers in a simple process without potential surface contamination.
  • the multi-layered binary oxide film can be applied to a nonvolatile memory device such as a resistance random access memory to realize a nonvolatile memory device that is more efficient than the conventional Perovskite structure and has excellent reproducibility and is effective for mass production.
  • FIG. 1 illustrates a method for growing a multi-layered binary oxidation film according to the present invention.
  • FIG. 2 illustrates an exemplary apparatus for remote oxidation in the present invention.
  • FIG. 3 illustrates resistance change in a non- volatile memory, in which (a) is a graph showing the characteristics of the memory according to the present invention, and (b) is a graph showing the characteristics of the conventional memory.
  • the present invention aims to form a metal layer and binary oxide film in a vacuum atmosphere thereby to obtain a ReRAM. According to the invention, since the metal layer is formed and oxidized in a vacuum atmosphere, the binary oxide film is not exposed to an atmospheric condition, thus without potential surface contamination. It is preferable to conduct oxidation process by remote oxidation in the present invention.
  • the substrate 11 can be any kind that is typically applied to a semiconductor memory device and is not limited to a particular kind.
  • the most representative example is a Si substrate including a silicon dioxide substrate and a poly silicon substrate.
  • the electrode layer is made of one selected from a group consisting of Pt, Au, Al,
  • the electrode layer has a thickness of about 5nm to 500nm depending on the kind of electrode material.
  • the lower electrode layer can be formed by plating or deposition.
  • a metal layer 13 is formed on the lower electrode layer 12 (see FIG. l(c)).
  • a method for forming a metal layer 13 in a vacuum atmosphere is used to form the metal layer 13. That is, methods of depositing and growing a metal layer in a vacuum atmosphere can be adopted, and such methods include Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), etc. Any type of metal layer suitable for ReRAM can be adopted.
  • the most representative example of metal layer can be made of one selected from a group consisting of Al, Co, Ni, Fe, Ta, Ti, Au, Pt, Ag and alloys thereof, which however does not limit the present invention. It is preferable that the metal layer has a thickness of 5 A to 10OA. Too large a thickness of the metal layer renders the later oxidation process difficult. Too small a thickness of the metal layer can affect the characteristics of the device. More preferably, the metal layer has a thickness of 1OA to 5OA, and most preferably, the metal layer has a thickness of 2OA to 4OA.
  • the metal layer 13 formed on the substrate 11 is oxidized into a binary oxide film
  • FIG. 2 illustrates a process of applying remote oxidation.
  • O gas is flown to collide into a coil 21 with remote plasma source 22 running therethrough to be ionized, entering the chamber 23 to form oxygen plasma.
  • the metal layer 13 is oxidized by this oxygen plasma.
  • remote oxidation has advantages in that it facilitates control of the thickness of the metal layer, and control of the composition of the oxide film. It is preferable that the entire surfaces of the metal layer are oxidized including its thickness direction.
  • remote oxidation can be conducted with O gas. More preferably, a predetermined amount of Ar gas is mixed with O gas.
  • the mix ratio is O gas: 10-100% to Ar gas: 0-90%. More preferably, the ratio is O gas: 50-80% to Ar gas: 20-50% for stable ionization of O .
  • RF can be adopted as the remote plasma source according to the present invention.
  • the output range of the RF can be 30W to 200W and the most preferable output range is 30W to IOOW in order to facilitate ionization of the gas and prevent damage to the film.
  • the step of forming the metal layer (FIG. l(c)) and the step of oxidizing the metal layer (FIG. l(d)) are repeated until a desired thickness of a multi-layered binary oxide film (FIG. l(e)) is obtained.
  • Each of the steps of forming and oxidizing the metal layer can be conducted once. Also as shown in FIG. l(e), the steps can be repeated at least two times each to form a multi-layered structure.
  • the steps of forming the metal layer and oxidizing the metal layer can be conducted in the same chamber. Alternatively, the steps can be conducted in different chambers while transfer between the chambers is conducted in a vacuum condition.
  • the substrate with the binary oxide film formed thereon as described above is annealed. It is preferable that annealing is conducted at a temperature ranging from 100 0 C to 1000 0 C in a vacuum or oxygen atmosphere for about 1 minute to 24 hours. Preferably, the substrate with the binary oxide film is annealed at a temperature ranging from 500 0 C to 700 0 C for 30 minutes to 3 hours in order to deliver sufficient amount of heat energy needed for rearrangement of lattice in the film.
  • An upper electrode layer is formed on the annealed multi-layered binary oxide film (FIG. 2(f)).
  • the upper electrode layer is made of one selected from a group consisting of Pt, Au, Al, Cu, Ti and alloys thereof, which however does not limit the present invention.
  • the upper electrode layer has a thickness of 5nm to 500nm.
  • the upper electrode layer can be formed by plating, etc. and can be formed in a vacuum atmosphere.
  • the upper electrode layer is formed in patterns using a shadow mask or dry etching processes.
  • the manufactured substrate can additionally be baked and post- annealed if necessary.
  • the multi-layered binary oxide film manufactured according to the present invention can be applied to a nonvolatile memory device. Such a memory device demonstrates low power consumption, infinite recording/reproduction, and quick rebooting of the PC and safe maintenance of a large capacity of data with its nonvolatile characteristics.
  • Al thin film was grown in a thickness of 30A on a Pt lower electrode layer formed on a Si substrate.
  • Ar gas and O gas were used at the ratio of 50%: 50% with RF of about 6OW to be ionized, thereby oxidizing the Al thin film.
  • This multi-layered thin film was annealed in a vacuum condition at about 500 0 C for about 30 minutes. After annealing, a Pt electrode layer was formed on the multi-layered thin film. Resistance change rate of 18000% was measured in the thin film and shown in FIG. 3(a).
  • the set voltage was improved from 3.7V with the conventional AlOx thin film to 1.65V with the present invention and the reset voltage was improved from 1.25 with the conventional AlOx thin film to 0.85 with the present invention.
  • the metal layer is made of Al in certain embodiments of the invention, but can also be made of one selected from a group consisting of Co, Ni, Fe, Ta, Ti, Au, Pt and Ag.

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Abstract

The invention relates to a method for forming a multi-layered binary oxide film for ReRAM. The method includes forming a lower electrode layer on a substrate; forming a metal layer on the lower electrode layer in a vacuum atmosphere; oxidizing the metal layer into a binary oxide film in a vacuum atmosphere; repeating the steps of forming and oxidizing the metal layer to form a desired thickness of the multi-layered binary oxide film; and forming an upper electrode layer on the multi-layered film. The method allows a nonvolatile memory device more efficient than the conventional perovskite structure in a simple process without concerns for surface contamination since the metal layer is formed and oxidized in a vacuum atmosphere.

Description

Description
METHOD FOR FORMING MULTI-LAYERED BINARY OXIDE FILM FOR USE IN RESISTANCE RANDOM ACCESS MEMORY
Technical Field
[1] The invention relates to a method for growing a multi-layered binary oxidation film for use in a Resistance Random Access Memory (ReRAM), and more particularly, a method for growing a binary oxidation film with excellent uniformity and reproducibility.
[2]
Background Art
[3] With rapid developments in mobile, digital information communication and electronic industries, researches on devices based on the conventional charge control approach are expected to face limitations in several years. In other words, there has been a demand for a memory device based on a new concept and function rather than on the concept of the conventional electronic charge devices which have been applied for most of the twentieth century.
[4] There is a possibility that the current PC-centered market structure will be shifted to a non-PC-centered one, which means capacity expansion of memories of major information apparatuses. In this regard, there is a need for developing an original technology for the next-generation, large-capacity, extra low-power memory device.
[5]
[6] Flash memory, which is the most representative of nonvolatile memory, requires high operational voltage to write or erase data. Therefore, in case when the gate length is decreased to 65nm or less, adjacent cells may be operated, thus causing confusion between cells, which raises a question whether the actual realization is possible. In addition, sufficient device margin is not ensured when operated at low voltage required for low-power consumption. Therefore, there is a need for rearch on the next- generation nonvolatile memory.
[7] Resistance Random Access Memory (hereinafter, referred to as 'ReRAM ) is a nonvolatile memory device based on drastic resistance change in a thin film with particular voltage applied to the thin film. Other nonvolatile memories have limitations. For example, DRAM is limited in scale-down (decrease in the gate length), FRAM is unstable in its material, flash memory exhibits low speed and high power consumption, and MRAM entails a complex process, multi-layer structure and small read/write margin.
[8] [9] On the other hand, ReRAM has excellent characteristics such as infinite recording and reproduction, operability at high temperature, and nonvolatile characteristics ensuring safety of data. Also, it can operate at high speed of 10 to 20ns (nanoseconds) and can achieve high integration and speed since it is a single-film structure in terms of process. It is manufactured basically as a single-layer structure, which can be conducted by CMOS and integration processes, thereby minimizing energy consumption.
[10] Korean Patent Application No. 2004-0080999 discloses a method of applying a
PCMO thin film for use in ReRAM. The application method includes forming a barrier layer in a thickness of 10 to lOOnm, depositing a layer of iridium on the barrier layer, spin coating a layer of PCMO (Pr Ca MnO ) on the iridium, baking the PCMO and substrate in a three-step baking process, post-baking annealing the substrate and the PCMO in a RTP chamber, repeating the spin coating, baking and annealing steps until the PCMO has a desired thickness, annealing the substrate and PCMO, and depositing a top electrode and complete the ReRAM device.
[11] Such a manufacturing process of the PCMO thin film entails a complicated process, and transfer from vacuum to atmospheric conditions, which may affect the characteristics of ReRAM due to oxidation and surface contamination. Thus, the method is difficult to achieve excellent reproducibility and to maintain a uniform composition of PCMO material.
[12] Therefore, there has been a demand for a method that is simple and practical for various applications and is capable of manufacturing a nonvolatile memory device without potential surface contamination.
[13]
Disclosure of Invention
Technical Problem
[14] The present invention has been made to solve the foregoing problems of the prior art and therefore an object of certain embodiments of the present invention is to provide a method for forming an oxidation film for use in a ReRAM in a simple process without a problem of surface contamination.
[15]
Technical Solution
[16] According to an aspect of the invention for realizing the object, there is provided a method for forming a multi-layered binary oxide film for use in a resistance random access memory, comprising steps of:
[17] (i) forming a lower electrode layer on a substrate;
[18] (ii) forming a metal layer on the lower electrode layer in a vacuum atmosphere; [19] (iii) oxidizing the metal layer into a binary oxide film in a vacuum atmosphere;
[20] (iv) repeating the steps (ii) and (iii) to form a desired thickness of multi-layered binary oxide film; and
[21] (v) forming an upper electrode layer on the multi-layered binary oxide film.
[22] In the present invention, it is preferable that the lower electrode layer and the upper electrode layer is made of one selected from a group consisting of Pt, Au, Al, Cu, Ti and alloys thereof. It is preferable that the metal layer is made of one selected from a group consisting of Al, Co, Ni, Fe, Ta, Ti, Au, Pt, Ag and alloys thereof. Preferably, the metal layer has a thickness ranging from 5 to IOOA and more preferably, 0-50A
[23] In the present invention, the step (iii) comprises remote oxidation with 0% to 90% of Ar gas and 10% to 100% of O gas, with RF plasma at an output of 30W to 200W.
[24] It is preferable that the multi-layered binary oxidation film is annealed at a temperature ranging from 1000C to 10000C for 1 minute to 24 hours.
[25]
Advantageous Effects
[26] According to the present invention, a metal layer is formed and oxidized in a vacuum atmosphere, and thus a binary oxide film can be formed in multi-layers in a simple process without potential surface contamination. The multi-layered binary oxide film can be applied to a nonvolatile memory device such as a resistance random access memory to realize a nonvolatile memory device that is more efficient than the conventional Perovskite structure and has excellent reproducibility and is effective for mass production.
[27]
Brief Description of the Drawings
[28] The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
[29] FIG. 1 illustrates a method for growing a multi-layered binary oxidation film according to the present invention.
[30] FIG. 2 illustrates an exemplary apparatus for remote oxidation in the present invention.
[31] FIG. 3 illustrates resistance change in a non- volatile memory, in which (a) is a graph showing the characteristics of the memory according to the present invention, and (b) is a graph showing the characteristics of the conventional memory.
[32]
Best Mode for Carrying Out the Invention
[33] The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the shapes and dimensions are exaggerated for clarity, and the same reference numerals are used throughout to designate the same or similar components.
[34] The present invention aims to form a metal layer and binary oxide film in a vacuum atmosphere thereby to obtain a ReRAM. According to the invention, since the metal layer is formed and oxidized in a vacuum atmosphere, the binary oxide film is not exposed to an atmospheric condition, thus without potential surface contamination. It is preferable to conduct oxidation process by remote oxidation in the present invention.
[35] The steps of forming a multi-layered film will now be explained with reference to
FIGS. 1 and 2.
[36] First, a substrate 11 is prepared (see FIG. l(a)).
[37] The substrate 11 can be any kind that is typically applied to a semiconductor memory device and is not limited to a particular kind. The most representative example is a Si substrate including a silicon dioxide substrate and a poly silicon substrate.
[38] Then a lower electrode layer 12 is formed on the prepared substrate 11 (see FIG. l(b)).
[39] The electrode layer is made of one selected from a group consisting of Pt, Au, Al,
Cu, Ti and alloys thereof, which however does not limit the present invention. It is preferable that the electrode layer has a thickness of about 5nm to 500nm depending on the kind of electrode material. The lower electrode layer can be formed by plating or deposition.
[40] Then, a metal layer 13 is formed on the lower electrode layer 12 (see FIG. l(c)).
[41] A method for forming a metal layer 13 in a vacuum atmosphere is used to form the metal layer 13. That is, methods of depositing and growing a metal layer in a vacuum atmosphere can be adopted, and such methods include Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), etc. Any type of metal layer suitable for ReRAM can be adopted. The most representative example of metal layer can be made of one selected from a group consisting of Al, Co, Ni, Fe, Ta, Ti, Au, Pt, Ag and alloys thereof, which however does not limit the present invention. It is preferable that the metal layer has a thickness of 5 A to 10OA. Too large a thickness of the metal layer renders the later oxidation process difficult. Too small a thickness of the metal layer can affect the characteristics of the device. More preferably, the metal layer has a thickness of 1OA to 5OA, and most preferably, the metal layer has a thickness of 2OA to 4OA.
[42] The metal layer 13 formed on the substrate 11 is oxidized into a binary oxide film
13' in a vacuum atmosphere (see FIG. l(d)). Any kind of oxidation process suitable for oxidizing a metal layer in a vacuum atmosphere can be adopted. The most preferable example is remote oxidation.
[43]
[44] FIG. 2 illustrates a process of applying remote oxidation. In remote oxidation, O gas is flown to collide into a coil 21 with remote plasma source 22 running therethrough to be ionized, entering the chamber 23 to form oxygen plasma. The metal layer 13 is oxidized by this oxygen plasma. Compared with a general oxidation method, remote oxidation has advantages in that it facilitates control of the thickness of the metal layer, and control of the composition of the oxide film. It is preferable that the entire surfaces of the metal layer are oxidized including its thickness direction.
[45] According to the present invention, remote oxidation can be conducted with O gas. More preferably, a predetermined amount of Ar gas is mixed with O gas. The mix ratio is O gas: 10-100% to Ar gas: 0-90%. More preferably, the ratio is O gas: 50-80% to Ar gas: 20-50% for stable ionization of O .
[46] For remote oxidation, RF can be adopted as the remote plasma source according to the present invention. The output range of the RF can be 30W to 200W and the most preferable output range is 30W to IOOW in order to facilitate ionization of the gas and prevent damage to the film.
[47] The step of forming the metal layer (FIG. l(c)) and the step of oxidizing the metal layer (FIG. l(d)) are repeated until a desired thickness of a multi-layered binary oxide film (FIG. l(e)) is obtained. Each of the steps of forming and oxidizing the metal layer can be conducted once. Also as shown in FIG. l(e), the steps can be repeated at least two times each to form a multi-layered structure. In the present invention, the steps of forming the metal layer and oxidizing the metal layer can be conducted in the same chamber. Alternatively, the steps can be conducted in different chambers while transfer between the chambers is conducted in a vacuum condition.
[48] Then, the substrate with the binary oxide film formed thereon as described above is annealed. It is preferable that annealing is conducted at a temperature ranging from 1000C to 10000C in a vacuum or oxygen atmosphere for about 1 minute to 24 hours. Preferably, the substrate with the binary oxide film is annealed at a temperature ranging from 5000C to 7000C for 30 minutes to 3 hours in order to deliver sufficient amount of heat energy needed for rearrangement of lattice in the film.
[49] An upper electrode layer (pattern) is formed on the annealed multi-layered binary oxide film (FIG. 2(f)). The upper electrode layer is made of one selected from a group consisting of Pt, Au, Al, Cu, Ti and alloys thereof, which however does not limit the present invention. [50] It is preferable that the upper electrode layer has a thickness of 5nm to 500nm. The upper electrode layer can be formed by plating, etc. and can be formed in a vacuum atmosphere. The upper electrode layer is formed in patterns using a shadow mask or dry etching processes. [51] The manufactured substrate can additionally be baked and post- annealed if necessary. [52] The multi-layered binary oxide film manufactured according to the present invention can be applied to a nonvolatile memory device. Such a memory device demonstrates low power consumption, infinite recording/reproduction, and quick rebooting of the PC and safe maintenance of a large capacity of data with its nonvolatile characteristics. [53]
Mode for the Invention
[54] The present invention will now be explained in greater detail through an example.
[55] Example 1
[56] An Al thin film was grown in a thickness of 30A on a Pt lower electrode layer formed on a Si substrate. Using the apparatus shown in FIG. 2, Ar gas and O gas were used at the ratio of 50%: 50% with RF of about 6OW to be ionized, thereby oxidizing the Al thin film. [57] Repeating these growing and oxidizing steps of the Al thin film for 7 times to form an AlO multi-layered thin film in a thickness of 210A. This multi-layered thin film was annealed in a vacuum condition at about 500 0C for about 30 minutes. After annealing, a Pt electrode layer was formed on the multi-layered thin film. Resistance change rate of 18000% was measured in the thin film and shown in FIG. 3(a).
[58] On the other hand, an AlO binary oxidized substance was grown in a thickness of
210A on a Pt lower electrode layer, and the results are shown in FIG. 3(b).
[59] As seen in FIGS. 3(a) and (b), the set voltage was improved from 3.7V with the conventional AlOx thin film to 1.65V with the present invention and the reset voltage was improved from 1.25 with the conventional AlOx thin film to 0.85 with the present invention.
[60] While the present invention has been shown and described in connection with the preferred embodiments, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the spirit and scope of the invention as defined by the appended claims.
[61] For example, the metal layer is made of Al in certain embodiments of the invention, but can also be made of one selected from a group consisting of Co, Ni, Fe, Ta, Ti, Au, Pt and Ag.

Claims

Claims
[1] A method for forming a multi-layered binary oxide film for use in a resistance random access memory, comprising steps of:
(i) forming a lower electrode layer on a substrate;
(ii) forming a metal layer on the lower electrode layer in a vacuum atmosphere;
(iii) oxidizing the metal layer into a binary oxide film in a vacuum atmosphere;
(iv) repeating the steps (ii) and (iii) to form a desired thickness of multi-layered binary oxide film; and
(v) forming an upper electrode layer on the multi-layered binary oxide film. [2] The method according to claim 1, wherein the metal layer is made of one selected from a group consisting of Al, Co, Ni, Fe, Ta, Ti, Au, Pt, Ag and alloys thereof. [3] The method according to claim 1, wherein the metal layer has a thicknes ranging from 5 A to 100 A. [4] The method according to claim 3, wherein the metal layer has a thickness ranging from 1OA to 50A. [5] The method according to claim 1, wherein the step (iii) comprises remote oxidation. [6] The method according to claim 5, wherein the step (iii) is conducted with 0% to
90% of Ar gas and 10% to 100% of O gas. [7] The method according to claim 5, wherein the step (iii) is conducted with RF plasma at an output of 30W to 10OW. [8] The method according to claim 1, wherein the multi-layered binary oxidation film is annealed at a temperature ranging from 1000C to 10000C for 1 minute to
24 hours.
PCT/KR2006/002610 2005-07-04 2006-07-04 Method for forming multi-layered binary oxide film for use in resistance random access memory WO2007004843A1 (en)

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US11/994,551 US20080200003A1 (en) 2005-07-04 2006-07-04 Method for Forming Multi-Layered Binary Oxide Film for Use in Resistance Random Access Memory
JP2008520178A JP2009500845A (en) 2005-07-04 2006-07-04 Method for forming multilayer binary oxide film for ReRAM

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KR1020050059830A KR100622268B1 (en) 2005-07-04 2005-07-04 Layer-by-layer growth method of binary oxide thin films for the application of reram devices using remote oxidation process
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US7808810B2 (en) 2006-03-31 2010-10-05 Sandisk 3D Llc Multilevel nonvolatile memory cell comprising a resistivity-switching oxide or nitride and an antifuse
US7812404B2 (en) 2005-05-09 2010-10-12 Sandisk 3D Llc Nonvolatile memory cell comprising a diode and a resistance-switching material
US7824956B2 (en) 2007-06-29 2010-11-02 Sandisk 3D Llc Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same
US7829875B2 (en) 2006-03-31 2010-11-09 Sandisk 3D Llc Nonvolatile rewritable memory cell comprising a resistivity-switching oxide or nitride and an antifuse
US7834338B2 (en) 2005-11-23 2010-11-16 Sandisk 3D Llc Memory cell comprising nickel-cobalt oxide switching element
US7846785B2 (en) 2007-06-29 2010-12-07 Sandisk 3D Llc Memory cell that employs a selectively deposited reversible resistance-switching element and methods of forming the same
US7875871B2 (en) 2006-03-31 2011-01-25 Sandisk 3D Llc Heterojunction device comprising a semiconductor and a resistivity-switching oxide or nitride
US7902537B2 (en) 2007-06-29 2011-03-08 Sandisk 3D Llc Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same
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US9000407B2 (en) 2013-05-28 2015-04-07 Intermolecular, Inc. ReRAM materials stack for low-operating-power and high-density applications
US9001554B2 (en) 2013-01-10 2015-04-07 Intermolecular, Inc. Resistive random access memory cell having three or more resistive states
US9047940B2 (en) 2013-01-10 2015-06-02 Intermolecular, Inc. Resistive random access memory cells having variable switching characteristics
WO2016140715A1 (en) 2015-03-02 2016-09-09 Sandisk Technologies Llc Parallel bit line three-dimensional resistive random access memory
US9613689B1 (en) 2016-07-08 2017-04-04 Sandisk Technologies Llc Self-selecting local bit line for a three-dimensional memory array
US9620712B2 (en) 2014-10-31 2017-04-11 Sandisk Technologies Llc Concave word line and convex interlayer dielectric for protecting a read/write layer
US9627057B2 (en) 2013-03-15 2017-04-18 Crossbar, Inc. Programming two-terminal memory cells with reduced program current
US9666799B2 (en) 2014-10-31 2017-05-30 Sandisk Technologies Llc Concave word line and convex interlayer dielectric for protecting a read/write layer
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US10121965B1 (en) 2017-08-31 2018-11-06 Sandisk Technologies Llc Resistive random access memory device containing discrete memory material portions and method of making thereof
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US10224373B2 (en) 2017-06-28 2019-03-05 Sandisk Technologies Llc Three-dimensional ReRAM memory device employing replacement word lines and methods of making the same
US10224372B2 (en) 2017-05-24 2019-03-05 Sandisk Technologies Llc Three-dimensional memory device with vertical bit lines and replacement word lines and method of making thereof
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Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8664124B2 (en) 2005-10-31 2014-03-04 Novellus Systems, Inc. Method for etching organic hardmasks
US7915166B1 (en) 2007-02-22 2011-03-29 Novellus Systems, Inc. Diffusion barrier and etch stop films
US8962101B2 (en) 2007-08-31 2015-02-24 Novellus Systems, Inc. Methods and apparatus for plasma-based deposition
US8435608B1 (en) 2008-06-27 2013-05-07 Novellus Systems, Inc. Methods of depositing smooth and conformal ashable hard mask films
SG157992A1 (en) * 2008-07-01 2010-01-29 Showa Denko Hd Singapore Pte L Improvements in and relating to mram
KR101526926B1 (en) 2008-12-30 2015-06-10 삼성전자주식회사 Resist RAM and method of manufacturing the same
US8546898B2 (en) * 2009-10-29 2013-10-01 Hewlett-Packard Development Company, L.P. Optoelectronic light exposure memory
US8563414B1 (en) 2010-04-23 2013-10-22 Novellus Systems, Inc. Methods for forming conductive carbon films by PECVD
US8613863B2 (en) 2011-11-29 2013-12-24 Intermolecular, Inc. Methods for selective etching of a multi-layer substrate
US8791445B2 (en) 2012-03-01 2014-07-29 Intermolecular, Inc. Interfacial oxide used as switching layer in a nonvolatile resistive memory element
SG195494A1 (en) 2012-05-18 2013-12-30 Novellus Systems Inc Carbon deposition-etch-ash gap fill process
US8872152B2 (en) 2012-12-13 2014-10-28 Intermolecular, Inc. IL-free MIM stack for clean RRAM devices
US9362133B2 (en) 2012-12-14 2016-06-07 Lam Research Corporation Method for forming a mask by etching conformal film on patterned ashable hardmask
US9304396B2 (en) 2013-02-25 2016-04-05 Lam Research Corporation PECVD films for EUV lithography
CN103400938A (en) * 2013-08-19 2013-11-20 中国科学院微电子研究所 Method for fabricating resistance layer oxide film of nonvolatile resistance random access memory
US9320387B2 (en) 2013-09-30 2016-04-26 Lam Research Corporation Sulfur doped carbon hard masks
US9589799B2 (en) 2013-09-30 2017-03-07 Lam Research Corporation High selectivity and low stress carbon hardmask by pulsed low frequency RF power
CN113891954A (en) 2019-05-29 2022-01-04 朗姆研究公司 High selectivity, low stress, and low hydrogen diamond-like carbon hard mask generated by high power pulsed low frequency RF

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5286994A (en) * 1991-08-22 1994-02-15 Rohm Co., Ltd. Semiconductor memory trap film assembly having plural laminated gate insulating films
US6235572B1 (en) * 1998-06-19 2001-05-22 Hitachi, Ltd. Method of making a memory cell having two layered tantalum oxide films
JP2001247714A (en) * 2000-03-08 2001-09-11 Shin Etsu Chem Co Ltd Electrically conductive filler

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09223752A (en) * 1996-02-16 1997-08-26 Hitachi Ltd Manufacture of nonvolatile semiconductor storage device
US6475854B2 (en) * 1999-12-30 2002-11-05 Applied Materials, Inc. Method of forming metal electrodes
JP2003163082A (en) * 2001-11-26 2003-06-06 Tatsuo Morita Method and device for manufacturing thin film for organic el
KR100505108B1 (en) * 2003-02-12 2005-07-29 삼성전자주식회사 Sonos memory cell and method of fabricating the same
US6911361B2 (en) * 2003-03-10 2005-06-28 Sharp Laboratories Of America, Inc. Low temperature processing of PCMO thin film on Ir substrate for RRAM application
KR100773537B1 (en) * 2003-06-03 2007-11-07 삼성전자주식회사 Nonvolatile memory device composing one switching device and one resistant material and method of manufacturing the same
JP2005079563A (en) * 2003-09-04 2005-03-24 Matsushita Electric Ind Co Ltd Manufacturing method for electronic device
KR100697282B1 (en) * 2005-03-28 2007-03-20 삼성전자주식회사 Resistive memory cell, method for forming the same and resistive memory array using the same
US7527985B2 (en) * 2006-10-24 2009-05-05 Macronix International Co., Ltd. Method for manufacturing a resistor random access memory with reduced active area and reduced contact areas

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5286994A (en) * 1991-08-22 1994-02-15 Rohm Co., Ltd. Semiconductor memory trap film assembly having plural laminated gate insulating films
US6235572B1 (en) * 1998-06-19 2001-05-22 Hitachi, Ltd. Method of making a memory cell having two layered tantalum oxide films
JP2001247714A (en) * 2000-03-08 2001-09-11 Shin Etsu Chem Co Ltd Electrically conductive filler

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1905086A4 *

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Publication number Priority date Publication date Assignee Title
US8687410B2 (en) 2005-05-09 2014-04-01 Sandisk 3D Llc Nonvolatile memory cell comprising a diode and a resistance-switching material
US7812404B2 (en) 2005-05-09 2010-10-12 Sandisk 3D Llc Nonvolatile memory cell comprising a diode and a resistance-switching material
US7834338B2 (en) 2005-11-23 2010-11-16 Sandisk 3D Llc Memory cell comprising nickel-cobalt oxide switching element
US7829875B2 (en) 2006-03-31 2010-11-09 Sandisk 3D Llc Nonvolatile rewritable memory cell comprising a resistivity-switching oxide or nitride and an antifuse
US8592792B2 (en) 2006-03-31 2013-11-26 Sandisk 3D Llc Heterojunction device comprising a semiconductor oxide and a resistivity-switching oxide or nitride
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US7808810B2 (en) 2006-03-31 2010-10-05 Sandisk 3D Llc Multilevel nonvolatile memory cell comprising a resistivity-switching oxide or nitride and an antifuse
US7846785B2 (en) 2007-06-29 2010-12-07 Sandisk 3D Llc Memory cell that employs a selectively deposited reversible resistance-switching element and methods of forming the same
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WO2009005699A1 (en) * 2007-06-29 2009-01-08 Sandisk 3D, Llc Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same
US8913417B2 (en) 2007-06-29 2014-12-16 Sandisk 3D Llc Memory cell that employs a selectively deposited reversible resistance-switching element and methods of forming the same
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US7824956B2 (en) 2007-06-29 2010-11-02 Sandisk 3D Llc Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same
CN102709471A (en) * 2007-06-29 2012-10-03 桑迪士克3D公司 Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same
US8373150B2 (en) 2007-06-29 2013-02-12 Sandisk 3D, Llc Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same
US8809114B2 (en) 2007-06-29 2014-08-19 Sandisk 3D Llc Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same
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US8445885B2 (en) 2008-12-04 2013-05-21 Panasonic Corporation Nonvolatile memory element having a thin platinum containing electrode
WO2010064410A1 (en) * 2008-12-04 2010-06-10 パナソニック株式会社 Nonvolatile memory element
US9001554B2 (en) 2013-01-10 2015-04-07 Intermolecular, Inc. Resistive random access memory cell having three or more resistive states
US9047940B2 (en) 2013-01-10 2015-06-02 Intermolecular, Inc. Resistive random access memory cells having variable switching characteristics
US9627057B2 (en) 2013-03-15 2017-04-18 Crossbar, Inc. Programming two-terminal memory cells with reduced program current
US9000407B2 (en) 2013-05-28 2015-04-07 Intermolecular, Inc. ReRAM materials stack for low-operating-power and high-density applications
US9620712B2 (en) 2014-10-31 2017-04-11 Sandisk Technologies Llc Concave word line and convex interlayer dielectric for protecting a read/write layer
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WO2017131897A1 (en) 2016-01-29 2017-08-03 Sandisk Technologies Llc Vacancy-modulated conductive oxide resistive ram device including an interfacial oxygen source layer
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