CN102709471A - Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same - Google Patents

Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same Download PDF

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CN102709471A
CN102709471A CN2012101249563A CN201210124956A CN102709471A CN 102709471 A CN102709471 A CN 102709471A CN 2012101249563 A CN2012101249563 A CN 2012101249563A CN 201210124956 A CN201210124956 A CN 201210124956A CN 102709471 A CN102709471 A CN 102709471A
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forming
layer
reversible resistance
switching element
diode
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CN2012101249563A
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CN102709471B (en
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A·谢瑞克
M·克拉克
S·B·赫纳
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桑迪士克3D公司
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Priority to US11/772,082 priority patent/US7824956B2/en
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Priority to CN200880022667.42008.06.27 priority
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    • H01L27/2409Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, e.g. resistance switching non-volatile memory structures comprising two-terminal selection components, e.g. diodes
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    • H01L27/2463Arrangements comprising multiple bistable or multistable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays, details of the horizontal layout
    • H01L27/2481Arrangements comprising multiple bistable or multistable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays, details of the horizontal layout arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays, details of the vertical layout
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    • H01L27/102Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
    • H01L27/1021Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only
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    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/12Details
    • H01L45/122Device geometry
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    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/14Selection of switching materials
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    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/14Selection of switching materials
    • H01L45/145Oxides or nitrides
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    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/16Manufacturing
    • H01L45/1608Formation of the switching material, e.g. layer deposition
    • H01L45/1633Formation of the switching material, e.g. layer deposition by conversion of electrode material, e.g. oxidation

Abstract

A method of forming a memory cell is provided that includes (1) forming a first conductor (206) above a substrate; (2) forming a reversible resistance-switching element (202) above the first conductor using a selective growth process; (3) forming a diode (204) above the first conductor; and (4) forming a second conductor (208) above the diode and the reversible resistance-switching element so as to obtain a crosspoint memory device. The switching element can also be steered by a TFT. The switching element contains a difficult to etch material, e.g. TiO2, and is formed without etching this material by means of oxidising another material, e.g. Ti or TiN.

Description

利用选择性生长的可逆电阻切换元件的存储器单元以及形成该存储器单元的方法 Memory cells using the selective growth of the reversible resistance-switching element and a method of forming the memory cell

[0001] 本申请是于2008年6月27日提出的发明名称为“利用选择性生长的可逆电阻切换元件的存储器单元以及形成该存储器单元的方法”的中国发明专利ZL200880022667. 4的 [0001] This application is entitled on June 27, 2008, filed as "selective growth using reversible resistance-switching element and a method of a memory cell of the memory cell forming" Chinese Patent ZL200880022667. 4 is

分案申请。 Divisional application.

[0002] 该申请要求2007年6月29日提交的名称为“MEMORY CELLTHAT EMPLOYSA SELECTIVELY GROWN REVERSIBLERESISTANCE-SWITCHING ELEMENT AND METHODS0FF0RMING THE SAME”的美国专利申请第11/772,082号(代理人案号SD-MXD-0335X)以及2007 年6 月29 日提交的名称为“MEMORYCELL THAT EMPLOYS A SELECTIVELY GROWNREVERSIBLERESISTANCE-SWITCHING ELEMENT AND METHODS 0FF0RMING THE SAME”的美国专利申请第11/772,088号(代理人案号SD-MXD-0335Y)的优先权。 [0002] This application claims the June 29, 2007, filed as "MEMORY CELLTHAT EMPLOYSA SELECTIVELY GROWN REVERSIBLERESISTANCE-SWITCHING ELEMENT AND METHODS0FF0RMING THE SAME" US Patent Application No. 11 / 772,082 (Attorney Docket No. SD-MXD -0335X) and the name of June 29, 2007, filed as "MEMORYCELL THAT EMPLOYS a SELECTIVELY GROWNREVERSIBLERESISTANCE-SWITCHING ELEMENT aND METHODS 0FF0RMING tHE SAME" US Patent application / 11, No. 772,088 (Attorney docket No. SD-MXD-0335Y) priority. 上述两个专利申请均在此通过参考整体合并于此。 The above-mentioned two patent applications are hereby incorporated herein by reference in its entirety.

[0003] 相关申请交叉引用 [0003] CROSS-REFERENCE TO RELATED APPLICATIONS

[0004] 本申请涉及下列申请,下列申请中的每个均通过参考整体合并于此: [0004] The present application relates to the following applications, the following applications are each incorporated herein by reference in its entirety:

[0005] 2007 年6 月29 日提交的名称为“METHOD TO FORMAREffRITEABLE MEMORY CELLCOMPRISING A DIODE AND ARESISTIVITY-SWITCHING GR0WN0XIDE” 的美国专利申请第No. 11/772,081 号(案号MD-304X)。 [0005] Name June 29, 2007, filed as "METHOD TO FORMAREffRITEABLE MEMORY CELLCOMPRISING A DIODE AND ARESISTIVITY-SWITCHING GR0WN0XIDE" US Patent Application No. No. 11 / 772,081 (Docket No. MD-304X).

[0006] 2007 年6 月29 日提交的名称为“MEMORY CELL THATEMPLOYS A SELECTIVELYDEPOSITED REVERSIBLERESISTANCE-SWITCHING ELEMENT AND METHODS 0FF0RMING THESAME”的美国专利申请第11/772,090号(案号MD-333X)。 [0006] Name June 29, 2007, filed as "MEMORY CELL THATEMPLOYS A SELECTIVELYDEPOSITED REVERSIBLERESISTANCE-SWITCHING ELEMENT AND METHODS 0FF0RMING THESAME" US Patent Application No. 11 / 772,090 (Docket No. MD-333X).

[0007] 2007 年6 月29 日提交的名称为“MEMORY CELL THATEMPLOYS A SELECTIVELYDEPOSITED REVERSIBLERESISTANCE-SWITCHING ELEMENT AND METHODS 0FF0RMING THESAME”的美国专利申请第11/772,084号(案号MD-333Y)。 [0007] Name June 29, 2007, filed as "MEMORY CELL THATEMPLOYS A SELECTIVELYDEPOSITED REVERSIBLERESISTANCE-SWITCHING ELEMENT AND METHODS 0FF0RMING THESAME" US Patent Application No. 11 / 772,084 (Docket No. MD-333Y).

技术领域 FIELD

[0008] 本申请涉及一种非易失性存储器,特别涉及一种利用选择性生长的可逆电阻切换元件的存储器单元以及形成该存储器单元的方法。 [0008] The present application relates to a nonvolatile memory, and more particularly to a method of switching elements and forming a memory cell of the memory cell with a reversible resistance is selectively grown.

背景技术 Background technique

[0009] 由可逆电阻切换元件形成的非易失性存储器是众所周知的。 [0009] The nonvolatile memory element is formed by a reversible resistance-switching are well known. 例如,2005年5月9 日提交的名称为“REWRITEABLE MEMORY CELLCOMPRISING A DIODE AND ARESISTANCE-SWITCHINGMATERIAL”的美国专利申请第11/125,939号(下文中称其为' 939申请),通过参考整体合并于本文以用于全部目的,其中描述了一种可重复写入的非易失性存储器单元,该存储器单元包括与可逆电阻切换材料例如金属氧化物或者金属氮化物串联的二极管。 For example, the name of May 9, 2005 entitled "REWRITEABLE MEMORY CELLCOMPRISING A DIODE AND ARESISTANCE-SWITCHINGMATERIAL" U.S. Patent Application No. 11 / 125,939 (hereinafter referred to as' 939 application), incorporated by reference in its entirety herein for all purposes, which describes the non-volatile memory unit for rewritable, the memory cell comprising a diode and a reversible resistance-switching material such as a metal oxide or a metal nitride series.

[0010] 然而,利用可重复写入的电阻切换材料制造存储器件是困难的;希望有利用可逆电阻切换材料制造存储器件的改进方法。 [0010] However, with the resistance-switching material rewritable memory device it is difficult; desired improved method using reversible resistance-switching material memory device. 发明内容 SUMMARY

[0011] 在本发明的第一方面,提供一种形成存储器单元的方法,该方法包括(I)在衬底上方形成控向元件;(2)利用选择性生长工艺形成耦连到控向元件的可逆电阻切换元件。 [0011] In a first aspect of the present invention, there is provided a method of forming a memory cell, the method comprising (I) form a steering element above a substrate; (2) is formed using a selective growth process is coupled to the steering element reversible resistance-switching element.

[0012] 在本发明的第二方面,提供一种形成存储器单元的方法,该方法包括(I)在衬底上方形成第一导体;(2)利用选择性生长工艺在第一导体上方形成可逆电阻切换元件;(3)在第一导体上方形成二极管;(4)在二极管和可逆电阻切换元件上方形成第二导体。 [0012] In a second aspect of the present invention, there is provided a method of forming a memory cell, the method comprising (I) forming a first conductor above a substrate; (2) using a selective growth process is formed above the first conductor reversible resistance switching element; (3) forming a diode above the first conductor; (4) forming a second conductor above the diode and the reversible resistance-switching element.

[0013] 在本发明的第三方面,提供一种形成存储器单元的方法,该方法包括(I)在衬底上方形成第一导体;(2)在第一导体上方形成氮化钛层;(3)通过氧化氮化钛层选择性地形成可逆电阻切换元件;(4)在可逆电阻切换元件上形成垂直多晶二极管;(5)在竖直多晶二极管上方形成第二导体。 [0013] In a third aspect of the present invention, there is provided a method of forming a memory cell, the method comprising (I) forming a first conductor above a substrate; (2) a titanium nitride layer is formed over the first conductor; ( 3) the titanium oxide layer is selectively formed by a reversible resistance-switching element of; (4) forming a reversible resistance-switching vertical polycrystalline diode element; (5) forming a second conductor above the vertical polycrystalline diode plurality.

[0014] 在本发明的第四方面,提供一种形成存储器单元的方法,该方法包括(I)形成具有源极区和漏极区的薄膜晶体管;(2)形成耦连到薄膜晶体管的源极区或漏极区的第一导体;(3)在第一导体上形成氮化钛层;(4)通过氧化氮化钛层选择性地形成可逆电阻切换元件;(5)在可逆电阻切换元件上方形成第二导体。 [0014] In a fourth aspect of the present invention, there is provided a method of forming a memory cell, the method comprising (I) forming a thin film transistor having a source region and a drain region; (2) forming a thin film transistor coupled to a source of a first conductive region or the drain region; (3) forming a titanium nitride layer on the first conductor; (4) the reversible resistance-switching element formed by the titanium oxide layer is selectively; (5) in the reversible resistance-switching a second conductor formed above the element.

[0015] 在本发明的第五方面,提供一种存储器单元,该存储器单元包括(I)控向元件; [0015] In a fifth aspect of the present invention, there is provided a memory cell, the memory cell comprises (I) to the control element;

(2)可逆电阻切换元件,该可逆电阻切换元件耦连到该控向元件并且是利用选择性生长工艺形成的。 (2) reversible resistance-switching element, the reversible resistance-switching element coupled to the steering element and is formed using a selective growth process.

[0016] 在本发明的第六方面,提供一种存储器单元,该存储器单元包括(I)第一导体; [0016] In a sixth aspect of the present invention, there is provided a memory cell, the memory cell comprising (I) a first conductor;

(2)形成于第一导体上方的第二导体;(3)形成于第一导体和第二导体之间的二极管;(4)利用选择性生长工艺形成于第一导体和第二导体之间的可逆电阻切换元件。 (2) a second conductor formed above the first conductor; (3) a diode formed between the first and second conductors; (4) using a selective growth process is formed between the first and second conductors reversible resistance-switching element.

[0017] 在本发明的第七方面,提供一种存储器单元,该存储器单元包括(I)第一导体; [0017] In a seventh aspect of the present invention, there is provided a memory cell, the memory cell comprising (I) a first conductor;

(2)在第一导体上方形成氮化钛层;(3)通过氧化氮化钛层选择性形成可逆电阻切换元件; (2) forming a titanium nitride layer over the first conductor; (3) is selectively formed through the reversible resistance-switching element titanium oxide layer;

(4)在可逆电阻切换元件上形成的垂直多晶硅二极管;(5)形成于竖直多晶二极管上方的第二导体。 (4) vertical polycrystalline diode formed on the reversible resistance-switching element; (5) a second conductor formed on the top of the vertical polycrystalline diode.

[0018] 在本发明的第八方面,提供一种存储器单元,该存储器单元包括(I)具有源极区和漏极区的薄膜晶体管;(2)耦连到薄膜晶体管的源极区或漏极区的第一导体;(3)形成于第一导体上的氮化钛层;(4)通过氧化氮化钛层而选择性地形成的可逆电阻切换元件;和 [0018] In an eighth aspect of the present invention, there is provided a memory cell, the memory cell comprising (I) a thin film transistor having a source region and a drain region; (2) coupled to the source or drain region of the thin film transistor a first conductive region; and (3) is formed on the titanium nitride layer on the first conductor; (4) a reversible resistance-selectively formed by the titanium oxide layer switching element; and

(5)形成于可逆电阻切换元件上方的第二导体。 (5) a second conductor formed above the reversible resistance-switching element in the.

[0019] 在本发明的第九方面,提供多个非易失性存储器单元,该存储器单元包括(I)沿第一方向延伸的大致平行、大致共面的多个第一导体;(2)多个二极管;(3)多个可逆电阻切换元件;(4)沿不同于第一方向的第二方向延伸的大致平行、大致共面的多个第二导体。 [0019] In a ninth aspect of the present invention, there is provided a plurality of nonvolatile memory cells, the memory cell comprising (I) substantially extending parallel to a first direction, a plurality of substantially coplanar first conductors; (2) a plurality of diodes; (3) a plurality of reversible resistance-switching element; (4) substantially parallel to a second direction different from the extending direction of the first plurality of substantially coplanar second conductors. 在每个存储器单元中,二极管中的一个与可逆电阻切换元件中的一个串联,并设置在第一导体中的一个和第二导体中的一个之间。 In each memory cell, a diode in series with a reversible resistance-switching element and provided in a first conductor and a second conductor between. 每个可逆电阻切换元件都是利用选择性生长工艺形成的。 Each reversible resistance- switching element are formed using a selective growth process.

[0020] 在本发明的第十方面,提供一种包括形成于衬底上方的第一存储器级的单片三维存储阵列,其中第一存储级具有多个存储器单元。 [0020] In a tenth aspect of the present invention, there is provided a monolithic three dimensional memory array comprising a first memory level formed above a substrate, wherein the first storage stage having a plurality of memory cells. 第一存储器级的每个存储器单元含有(I)控向元件;(2)可逆电阻切换元件,该可逆电阻切换元件耦连到该控向元件并且是利用选择性生长工艺形成的。 Each memory cell comprising a first memory level (I) to the control element; (2) a reversible resistance-switching element, the reversible resistance-switching element coupled to the steering element and is formed using a selective growth process. 单片三维存储器阵列还包括单片地形成于第一存储器级上方的至少一个第二存储器级。 Monolithic three dimensional memory array further comprises at least a second memory level monolithically formed above the first memory level. 提供了很多的其它方面。 It provides many other aspects.

[0021] 本发明的其它特征和方面通过下文的具体描述、权利要求以及附图得以更清楚地体现。 [0021] Other features and aspects of the invention by the following detailed description, claims, and drawings to more clearly embody.

附图说明 BRIEF DESCRIPTION

[0022] 图I是根据本发明提供的示例性存储器单元的示意图。 [0022] FIG. I is a schematic diagram of an exemplary memory cell in accordance with the present invention is provided.

[0023] 图2A是根据本发明提供的存储器单元的第一实施例的简化透视图。 [0023] FIG. 2A is a simplified perspective view of a first embodiment of the present invention, a memory cell is provided.

[0024] 图2B是由多个图2A中的存储器单元形成的第一存储器级的一部分的简化透视图。 [0024] 2B is a simplified perspective view of a portion of a first memory level formed from a plurality of FIG. 2A in the memory cell of FIG. [0025] 图2C是根据本发明提供的第一示例性三维存储器阵列的一部分的简化透视图。 [0025] FIG. 2C is a simplified perspective view of a portion of a first exemplary three dimensional memory array provided by the invention.

[0026] 图2D是根据本发明提供的第二示例性三维存储器阵列的一部分的简化透视图。 [0026] FIG 2D is a simplified perspective view of a portion of a second exemplary three dimensional memory array provided by the invention.

[0027] 图3是图2A的存储器单元的示例性实施例的截面图。 [0027] FIG. 3 is a sectional view of an exemplary embodiment of a memory cell of FIG. 2A.

[0028] 图4A-4D是根据本发明制造单个存储器级期间的衬底的一部分的截面图。 [0028] Figures 4A-4D is a cross-sectional view of a portion of a substrate during fabrication of a single memory level according to the present invention.

[0029] 图5是根据本发明提供的可替代的存储器单元的截面图。 [0029] FIG. 5 is a sectional view of an alternative memory cell provided in accordance with the present invention.

具体实施方式 Detailed ways

[0030] 如上所述,利用可重复写入的电阻率切换材料来制造存储器件是困难的。 [0030] As described above, the resistivity switching material rewritable memory device manufacturing is difficult. 例如,很多可重复写入的电阻率切换材料很难被化学刻蚀,由此增加了制造的成本和将其用于集成电路的复杂性。 For example, many rewriteable resistivity-switching material may be difficult to be chemically etched, thereby increasing the cost and manufacturing complexity for the integrated circuit.

[0031] 根据本发明,难以被化学刻蚀的可重复写入的电阻率切换材料可以用于存储器单元而不需要被刻蚀。 [0031] According to the present invention, the resistivity hardly rewritable chemical etched material may be used to switch a memory cell without being etched. 例如,在至少一个实施例中,提供了一种存储器单元,该存储器单元包括利用选择性生长工艺形成的可逆电阻率切换材料,从而可逆电阻率切换材料可以用于存储器单元而不被刻蚀。 For example, in at least one embodiment, a memory cell, the memory cell comprising a reversible resistivity is formed using a selective growth process switching material, such reversible resistivity-switching materials may be used in a memory cell without being etched.

[0032] 在一个或多个示例性实施例中,利用氧化钛作为可逆电阻率切换材料来形成可逆电阻切换元件。 [0032] In one or more exemplary embodiments, the use of titanium oxide as a reversible resistivity-switching material to form a reversible resistance-switching element. 如上文中合并的'939申请中所记载的,氧化钛膜已经表现出适用于存储器单元。 As hereinbefore incorporated '939 application described, the titanium oxide film has been shown to apply to the memory cell.

[0033] 氧化钛的膜如Ti0、Ti02、Ti0x、Ti0xNy等都难以被化学刻蚀。 [0033] The titanium oxide film such as Ti0, Ti02, Ti0x, Ti0xNy so difficult to etch chemistry. 在至少一个实施例中,通过利用选择性生长工艺,氧化钛层可以用于存储器单元的可逆电阻切换元件中而不需要对氧化钛层进行刻蚀。 In at least one embodiment the reversible resistance embodiment, by using a selective growth process, the titanium oxide layer may be used for the switching element of the memory cell without the need for titanium oxide layer is etched. 例如,可以通过氧化含钛层,如氮化钛这样比氧化钛更容易被图案化和刻蚀的氧化物,来形成可逆电阻切换元件。 For example, by containing titanium oxide layer such as titanium nitride, which is more easily patterned and etched oxide of titanium oxide, to form a reversible resistance-switching element. 通过这种方式,在含钛层的氧化之前,只有下层的含钛层(如氮化钛或者钛)被图案化和刻蚀而不是氧化钛层。 In this manner, before titanium oxide-containing layer, only the lower layer containing titanium (such as titanium nitride or titanium) is not patterned and etched titanium oxide layer.

[0034] 在一些实施例中,通过在有氧环境,如O2、臭氧或者它们的结合,或者使用其它任何合适的氧化空间中对含钛层实施快速热氧化而选择性地形成氧化钛。 [0034] In some embodiments, by any other suitable oxidation space containing selectively formed embodiment of a rapid thermal oxidation in an oxygen atmosphere the titanium layer, such as O2, ozone or a combination thereof, or titanium oxide. 在其它的实施例中,在含有臭氧或者其它氧源的化学气相沉积腔中通过氧扩散,通过气相或者液相的臭氧清洗,或者通过任何其它合适的氧化处理氧化含钛层以形成氧化钛。 In other embodiments, the diffusion of oxygen, ozone cleaning in gas or liquid phase chemical vapor deposition chamber containing ozone, or other oxygen source, a titanium-containing layer or by any other appropriate oxidation treatment to form titanium oxide. 在所有的例子中,都不需要对氧化钛进行刻蚀,这样就现出简化了存储单元的制造。 In all cases, we do not require etching of the titanium, thus emerged simplifies the production of the memory cell.

[0035] 根据本发明,其它的材料也可以被选择性地氧化以形成可逆的或者是一次性可编程的电阻率切换材料以用于存储器单元。 [0035] According to the present invention, other materials may also be selectively oxidized to form a reversible or time programmable resistivity-switching material for use in memory cells. 例如,可在衬底上沉积Ta、TaN, Nb, NbN, Al、A1N、Hf、HfN, V、VN等层,并与含钛层相似地被图案化、刻蚀和/或氧化,以形成可逆电阻率切换材料如Ta2O5, Nb2O5, Al2O3, HfO2, V2O5 等。 For example, may be deposited on a substrate Ta, TaN, Nb, NbN, Al, A1N, Hf, HfN, V, VN layer and the like, and similarly with the titanium-containing layer is patterned, etched, and / or oxidized to form reversible resistivity-switching material such as Ta2O5, Nb2O5, Al2O3, HfO2, V2O5 and the like.

[0036] 存储器单元的示例性发明 [0036] The exemplary inventive memory cell

[0037] 图I是根据本发明提供的示例性存储器单元100的示意图。 [0037] FIG. I is a schematic diagram 100 of an exemplary memory cell in accordance with the present invention is provided. 存储器单元100包括耦连到控向元件104的可逆电阻切换元件102。 The memory unit 100 includes a controller coupled to the reversible resistance-switching element 102 to element 104.

[0038] 可逆电阻切换元件102包括可逆电阻率切换材料(未单独示出),该可逆电阻率切换材料具有可在两个或更多个的状态之间可逆地切换的电阻。 [0038] Reversible resistance-switching element 102 includes reversible resistivity-switching material (not separately shown), the reversible resistivity-switching material having a resistivity may be reversibly switched between two or more states. 例如,元件102的可逆电阻率切换材料可以在制造时处于初始低电阻率状态,而在施加第一电压和/或电流后就被切换成高电阻率状态。 For example, the reversible resistivity-switching material of element 102 may be in an initial low-resistivity state upon fabrication, while applying a first voltage and / or current is switched after a high-resistivity state. 施加第二电压和/或电流可以使该可逆电阻率切换材料变回到低电阻率状态。 A second voltage and / or current can be applied so that the reversible resistivity-switching material changes back to a low resistivity state. 可替代地,可逆电阻切换元件102可以在制造时处于初始高阻状态,而在施加适当的(多个)电压和/或(多个)电流后就被可逆地切换成低阻状态。 Alternatively, the reversible resistance-switching element 102 may be in an initial high-impedance state at the time of manufacture, and is applied to the low-resistance state reversibly switched voltage and / or (s) after an appropriate current (s). 当用于存储器元件时,一种电阻状态可表示二进制的“ O ”而另一种电阻状态可以表示二进制的“ 1”,尽管可以使用多于两个的数据/电阻状态。 When a memory element is a resistance state may represent a binary "O" while another resistance state may represent a binary "1", although more than two data / resistance states. 许多可逆电阻率切换材料和利用可逆电阻切换元件的存储器单元的操作被记载在例如之前合并的' 939申请文件中。 Many operating a memory cell and a reversible resistivity-switching material with a reversible resistance-switching elements are described, for example combined prior '939 application documents.

[0039] 在本发明的至少一个实施例中,可逆电阻切换元件102是利用选择性生长工艺形成的。 [0039] In at least one embodiment of the present invention, the reversible resistance-switching element 102 is formed using a selective growth process. 本文中下面将会记载,利用选择性生长工艺可以在可逆电阻切换元件102中提供可逆电阻率切换材料而不需要对该可逆电阻率切换材料进行刻蚀。 It will be described herein below, using a selective growth process may be provided in the switching element 102 is reversible resistivity-switching material without the need for switching material is etched in the reversible resistance-reversible resistivity. 因此可逆电阻切换元件102的制造变得简化。 Thus producing a reversible resistance-switching element 102 becomes simplified.

[0040] 控向元件104可以包括薄膜晶体管、二极管或者通过选择性地限制可逆电阻切换元件102两端的电压和/或穿过可逆电阻切换元件102的电流而表现为非欧姆导通的其它合适的控向元件。 Other suitable [0040] the control element 104 may include a thin film transistor, a diode element or the voltage across the switch 102 and / or the current through the reversible resistance-switching element 102 by selectively limiting the performance of non-reversible resistance ohmic conduction steering element. 通过这种方式,存储器单元100可用作二维或三维存储器阵列的一部分,数据可以写入存储器单元100和/或从存储器单元100中读取而不影响阵列中其它存储器单元的状态。 In this manner, a portion of the two or three dimensional memory array of memory cells 100 may be used, data can be written and / or read from the memory cell array 100 without affecting the state of other memory cells in the memory cell 100.

[0041] 存储器单元100、可逆电阻切换元件102和控向元件104的示例性实施例将参考附图2A-图5在下文进行描述。 [0041] The memory cell 100, reversible resistance-switching element 102 and the control element to the exemplary embodiments with reference to the accompanying drawings 2A- 104 of FIG. 5 described below.

[0042] 存储器单元的第一优选实施例 A first preferred [0042] embodiment of a memory cell

[0043] 图2A是根据本发明提供的存储器单元200第一实施例的简化透视图。 [0043] FIG. 2A is a simplified perspective view of a memory cell 200 according to a first embodiment of the present invention is provided. 参考图2A,存储器单元200包括在第一导体206和第二导体208之间与二极管204串联的可逆电阻切换元件202(如虚线所示)。 2A, the first memory cell 200 includes a reversible resistance between the conductor 206 and 208 and the diode 204 in series with a second switching element conductor 202 (shown in phantom). 在一些实施例中,在可逆电阻切换元件202和二极管204之间还形成有阻挡层209,例如氮化钛、氮化钽、氮化钨等。 In some embodiments, the reversible resistance-switching layer 209 is also formed with a barrier, such as titanium nitride, tantalum nitride, tungsten and the like between the element 202 and the diode 204.

[0044] 如下文中将要提到的,可逆电阻切换元件是选择性形成的,这样可以简化存储单元200的制造。 [0044] As will be noted, the reversible resistance-switching element is selectively formed, which can simplify the manufacturing the memory cell 200. 在至少一个实施例中,可逆电阻切换元件202包括通过氧化含钛层,如氮化钛,而形成的至少部分的氧化钛层。 In at least one embodiment, the reversible resistance-switching element 202 includes a titanium oxide layer by a titanium-containing layer such as titanium nitride, it is formed at least partially. 例如,氮化钛层或者其它相似形态的钛可被沉积在二极管204的上面或者下面,然后被图案化和刻蚀(例如,和第一导体206 —起)。 For example, titanium nitride layer, or other similar forms of titanium may be deposited above or below the diode 204, and then patterned and etched (e.g., the first conductor and 206-- onwards). 氮化钛(或者其它物质)层然后被氧化形成氧化钛(例如,通过快速热氧化或者其它的氧化工艺)。 Titanium nitride (or other material) layer is then formed titanium oxide (e.g., by rapid thermal oxidation or another oxidation process) oxide.

[0045] 在图2A的实施例中,氮化钛或者类似的层210被形成后,与第一导体一起被图案化和刻蚀。 [0045] In the embodiment of FIG. 2A, or the like after the titanium nitride layer 210 is formed, together with the first conductor pattern and etching. 氮化钛或者类似的层然后被氧化形成氧化钛层212。 Titanium nitride or similar layer 212 is then formed titanium oxide layer. 与二极管204垂直重叠和/或对齐的氧化钛层的一部分作为位于存储单元200的二极管204和第一导体206之间的可逆电阻切换元件202。 And vertically overlapping a portion of the diode 204 and / or titanium oxide layer as the alignment between the reversible resistance-storage unit 206 is a first diode 204 and conductor 200 of switching element 202. 在一些实施例中,只有可逆电阻切换元件202的一部分,如一个或者几个细丝,可被切换和/或是可切换的。 In some embodiments, only a portion of the reversible resistance-switching element 202, such as one or several filaments, can be switched and / or be switchable. 氧化钛层可包括例如TiO、TiO2, TiOx, TiOxNy者类似物。 Titanium oxide layer may comprise, for example, TiO, TiO2, TiOx, TiOxNy who like. 虽然在图2A中所示的可逆电阻切换元件202位于二极管204的下方,可以理解,在可替代的实施例中,可逆电阻切换元件202可位于二极管204的上方。 While the reversible resistance-switching shown in FIG. 2A element 202 is positioned below the diode 204, it is understood, in alternative embodiments, the reversible resistance-switching element 202 may be located above the diode 204. 关于可逆电阻切换元件202的更多的细节将在下文中参考图3给予说明。 More details about the reversible resistance-switching element 202 will be given with reference to FIG. 3 described below.

[0046] 二极管204可以包括任何合适的二极管,例如垂直多晶pn或pin 二极管,其可以是朝上的,即二极管的η区在P区的上面,也可以是朝下的,即二极管的P区在η区的上面。 [0046] Diode 204 may include any suitable diode such as a vertical polycrystalline pn or pin diodes, which may be upward, i.e. in the region above the diode η P region, may also be downward, i.e., the diode P η region above the region. 二极管204的示例性实施例在下文中参考图3进行说明。 Diode 204 of an exemplary embodiment with reference to FIG 3 will be described below.

[0047] 第一和/或第二导体206、208可以包括任何合适的导电材料,如钨、任何合适的金属、重掺杂的半导体材料、导电的硅化物、导电的硅-锗化物、导电的锗化物等。 [0047] The first and / or second conductor 206, 208 may comprise any suitable conductive material, such as tungsten, any appropriate metal, heavily doped semiconductor material, a conductive suicide, a conductive silicon - germanium, a conductive germanium compounds and the like. 在图2Α的实施例中,第一和第二导体206、208是轨道形状的并沿着不同的方向延伸(例如,大体上互相垂直)。 In the embodiment of FIG 2Α embodiment, the first and second conductors 206, 208 are rail-shaped and extend in different directions (e.g., substantially perpendicular to each other). 其它的导体形状和/或结构也是可用的。 Other conductor shapes and / or configurations are also useful. 在一些实施例中,阻挡层、粘合层、抗反射涂层和/或类似物(未示出)可以与第一和/或第二导体206、208结合使用来提高器件的性能和/或有利于器件的制造。 In some embodiments, barrier layers, adhesion layers, antireflection coatings and / or the like (not shown) may be combined with the first 206, 208 and / or the second conductor to improve the performance of the device and / or It facilitates the manufacture of the device.

[0048] 如上所述,其它材料也可以用于形成可逆电阻切换元件202。 [0048] As described above, other materials may also be used to form a reversible resistance-switching element 202. 例如,如Ta、TaN、Nb、NbN、Al、AIN、Hf、HfN, V、VN等材料,可相似地被沉积(和/或被图案化和刻蚀)到第一导体206上,然后被氧化形成层212,其中包括可逆电阻切换材料202。 For example, such as Ta, TaN, Nb, NbN, Al, AIN, Hf, HfN, V, VN and other materials, can be similarly deposited (and / or patterned and etched) to a first conductor 206, and then forming an oxide layer 212, which includes a reversible resistance-switching material 202.

[0049] 图2B是利用多个图2A中的存储器单元形成的第一存储器级214的一部分的简化透视图。 [0049] FIG. 2B is a simplified perspective view of a portion of a first memory level 214 of Figure 2A with a plurality of memory cells formed. 为了简化,含钛的层210和氧化钛层212只示于底部导体206中的一个之上。 For simplicity, the oxide layer 210 and a titanium-containing layer 212 is shown at the bottom of a conductor 206 on top. 存储器阵列214是一个“交叉点”阵列,该阵列包括多个位线(第二导体208)和字线(第一导体206),多个存储器单元被耦连到这些线上(如图所示)。 The memory array 214 is a "cross-point" array, the array comprising a plurality of bit lines (second conductors 208) and word lines (first conductors 206), a plurality of memory cells are coupled to these lines (shown in FIG. ). 其它的存储器阵列结构也是可用的,例如也可以有多个存储器层级。 Other memory array configurations are available, for example, may have a plurality of memory levels. 例如,图2C是单片三维阵列216的一部分的简化透视图,该阵列包括位于第二存储器级220下面的第一存储器级218。 For example, FIG. 2C is a simplified perspective view of a portion of a monolithic three dimensional array 216, the array 218 includes a first memory level 220 positioned below a second memory level. 在图2C所示的实施例中,每个存储器级218、220包括位于交叉点阵列中的多个存储器单元200。 In the embodiment illustrated in Figure 2C, each memory level 218, 220 includes a plurality of cross point array 200 of memory cells. 可以理解,在第一和第二存储器级218和220之间可以存在一个或多个另外的层(例如层间电介质),但是为了简化,在图2C中没有示出。 It will be appreciated, there may be one or more additional layers (e.g., interlayer dielectric) between the first and second memory level 218 and 220, but for simplicity, not shown in FIG. 2C. 其它存储器阵列结构也是可用的,也可以有更多的存储器层级。 Other memory array configurations are available, there may be more memory hierarchy. 在图2C所示的实施例中,根据所有的二极管可以“指向”同一个方向,例如根据使用具有在二极管底部或顶部上的P掺杂区域的Pin 二极管来决定朝上或者朝下,以此来简化二极管的制造。 In the embodiment illustrated in Figure 2C, all diodes may according to a same direction "point", for example in accordance Pin diode having a P-doped region on the bottom or top of the diode determines the upward or downward, thereby to simplify the manufacture of diode.

[0050] 在一些实施例中,存储器级可以如例如美国专利第6,952,030号“High-densitythree-dimensional memory cell”中所记载的那样形成,该专利通过参考全文合并于此。 [0050] In some embodiments, the memory levels may be formed, such as, for example, U.S. Pat. No. 6,952,030 "High-densitythree-dimensional memory cell" described in this patent is incorporated herein by reference in its entirety. 例如,第一存储器级的上导体可用作位于第一存储器级上面的第二存储器级的下导体,如图2D所示。 For example, the conductor may be used as the first memory level conductor located in a second memory level above the first memory level, shown in Figure 2D. 在这样的实施例中,相邻存储器级的二极管优选指向相对的方向,如2007年 In such an embodiment, adjacent memory levels preferably point in the direction opposite to the diodes, such as 2007,

3 月27 日提交的名称为“LARGE ARRAY OF UPWARD POINTINGP-IN DIODES HAVING LARGEAND UNIFORM⑶RRENT”的美国专利申请第11/692,151号(下文中被称为' 151申请)中记载的那样,该申请通过参考全文合并于此。 U.S. Patent application entitled, filed March 27 to "LARGE ARRAY OF UPWARD POINTINGP-IN DIODES HAVING LARGEAND UNIFORM⑶RRENT" of No. 11 / 692,151 (hereinafter referred to as' 151 application), as described, which is incorporated by incorporated herein by reference in their entirety. 例如,第一存储器级218中的二极管如箭头A1所示朝上(例如,P区在二极管的底部),同时第二存储器级220的二极管如箭头A2所示朝下(例如,η区在二极管的底部),反之亦然。 For example, a diode as shown by arrow A1 upwardly (e.g., P in the area at the bottom of the diodes) a first memory level 218, while the diodes of the second memory stage 220 downward as indicated by arrow (e.g., [eta] in the diode region A2 shown in FIG. bottom), or vice versa.

[0051] 单片三维存储器阵列就是这样的一种存储器阵列,其中多个存储器级形成在单个衬底例如晶片上而没有介于其间的衬底。 [0051] The monolithic three dimensional memory array is such a memory array in which multiple memory levels are formed in a single substrate such as a wafer substrate is not interposed therebetween. 形成第一存储器级的层直接沉积或者生长在一个或多个现有级的层上。 Forming a first memory level are deposited or grown layer is directly on one or more layers of an existing level. 相反,堆叠的存储器是通过在分离的衬底上形成多个存储器级并将这些存储器级在顶部彼此粘合在一起而构建成的,如Leedy的美国专利第5,915,167号“Three dimensional structure memory”中记载的那样。 , As in Leedy, U.S. Patent No. 5,915,167 In contrast, stacked memories by forming on a substrate a plurality of separate stages of memory and memory levels on top of and adhered to each other to construct a "Three dimensional structure memory "as in the claims. 衬底在键合之前被减薄或者从存储器级上去除,但是因为存储器级最初形成于分离的衬底上,所以这样的存储器并不是真正的单片三维存储器阵列。 The substrate is thinned or removed from the memory levels before bonding, but as the memory levels are initially formed over separate substrates, such memories are not true monolithic three dimensional memory array.

[0052] 图3是图2A中的存储器单元200的示例性实施例的截面图。 [0052] FIG. 3 is a sectional view of an exemplary embodiment of a memory cell 200 of FIG. 2A. 参考图3,存储器单元200包括可逆电阻切换元件202 (例如,可逆电阻切换材料层的一部分,在该实施例中也就是氧化钛层212),二极管204和第一以及第二导体206,208。 Referring to Figure 3, memory cell 200 includes a reversible resistance-switching element 202 (e.g., a portion of the reversible resistance-switching material layer is, in this embodiment the titanium oxide layer is 212), and a first diode 204 and a second conductor 206, 208. 可逆电阻切换元件202可以是与二极管204垂直重叠和/或交迭的氧化钛层212的部分。 Reversible resistance-switching element 202 may be vertically overlapped with the diode 204 and / or the overlapping portion 212 of the titanium oxide layer.

[0053] 在图3的实施例中可逆电阻切换元件202是通过选择生长工艺形成的。 [0053] In one embodiment the reversible resistance-switching element 202 is formed by selective growth process in embodiment 3 of FIG. 例如,通过氧化含钛层210,在含钛层210上选择性地形成氧化钛层212。 For example, the titanium-containing oxide layer 210, 212 is selectively formed on the titanium oxide layer containing titanium layer 210. 通过这种方式,只有含钛层210,而不是氧化钛层212被蚀刻,如在第一导体206的图案化和刻蚀步骤。 In this manner, only the titanium-containing layer 210, instead of the titanium oxide layer 212 is etched, such as the step of patterning and etching the first conductor 206 in.

[0054] 含钛层210可通过任何合适的工艺被氧化。 [0054] The titanium-containing layer 210 may be oxidized by any suitable process. 例如,可在氧、臭氧、氧和臭氧共存或者其它氧源的环境下被热氧化(例如,通过快速热氧化)。 For example, it may be thermally oxidized in ambient oxygen, ozone, oxygen and ozone, or other oxygen source, coexist (e.g., by rapid thermal oxidation). 可替代地或者额外地,含有钛的层210可在含有臭氧或者其它氧源的化学气相沉积(CVD)腔中通过氧扩散,通过气相或者液相的臭氧清洗,或者通过任何其它合适的氧化工艺氧化含钛层以形成氧化钛。 Chemical vapor deposition (CVD) Alternatively or additionally, containing titanium layer 210 can contain ozone or another source of oxygen diffusion through an oxygen chamber, ozone gas or liquid phase by washing, or by any other suitable oxidation process titanium-containing oxide to form a titanium oxide layer. 如上文记载,其它的可逆电阻切换材料也可以通过对Ta、TaN, Nb、NbN、Al、A1N、Hf、HfN, V、VN等进行氧化来相似地形成。 Described above, other reversible resistance-switching material can also be similarly formed by Ta, TaN, Nb, NbN, Al, A1N, Hf, HfN, V, VN like oxidation.

[0055] 在一个优选实施例中,快速热氧化是在大约300到大约800°C的温度范围内,在氧气流的流速为大约2sccm到大约40sccm的条件下持续大约I秒到大约5分钟,其取决于需要氧化的厚度和/或其它性质。 [0055] In a preferred embodiment, the rapid thermal oxidation at a temperature in the range of about 300 to about to 800 ° C, the flow rate of oxygen flow was about 2sccm to under about 40sccm duration of about I second to about 5 minutes, oxidized as required depending on the thickness and / or other properties. 其它的氧化物质种类、温度、时间和/或流速也是可用的。 Other types of oxidizing species, temperature, time, and / or flow rate are also useful.

[0056] 在CVD腔中通过臭氧扩散的氧化过程可在大约300到大约800°C的温度范围内,优选在大约350到大约450°C的温度范围内,持续大约2分钟到大约4小时,优选大约15到25分钟,在合适的臭氧流速下,如在大约10到60sccm之间,取决于需要氧化的厚度和/或其它性能。 [0056] In the CVD chamber through the ozone diffusion of the oxidation process may be at a temperature in the range of about 300 to about to 800 ° C, preferably at a temperature in the range of about 350 to about 450 ° C, and lasts about 2 minutes to about 4 hours. preferably from about 15 to 25 minutes at a suitable flow rate of ozone, such as between about 60 sccm to 10, depending on the needs of oxide thickness and / or other properties. 其它的氧化物质种类,温度,时间和/或流速也是可用的。 Other types of oxidizing species, temperature, time, and / or flow rate are also useful.

[0057] 在上述各个实施例中,只有含有钛的层210被图案化和刻蚀,不需要对氧化钛层进行刻蚀。 [0057] In each of the above embodiments, only contains 210 is patterned and etched titanium layer, the titanium oxide layer does not need to be etched. 因此存储单元的制造被显著地简化。 Fabricating a memory cell is thus significantly simplified. 进一步的,可形成任何希望的氧化钛层的厚度。 Further, the thickness of the titanium oxide layer may be formed of any desired. 在一些实施例中,厚度为大约500埃或者更小,优选大约300埃或者更小的氧化钛层用于可逆电阻切换元件202中(虽然其它的厚度范围也是可用的)。 In some embodiments, a thickness of about 500 angstroms or less, preferably about 300 Å or less for titanium oxide layer reversible resistance-switching element 202 (although other thickness ranges are available).

[0058] 如上所述,二极管204可以是垂直的pn或者p-i_n 二极管,方向可以朝上或者朝下。 [0058] As described above, the diode 204 may be a vertical pn diode or a p-i_n, direction may be upward or downward. 在图2D所示的实施例中,相邻的存储器级共用导体,相邻的存储器级优选具有指向相对方向的二极管,例如第一存储器级中的Pin 二极管朝下,相邻的第二存储器级的pin二极管朝上(反之亦然)。 In the embodiment illustrated in FIG. 2D, adjacent memory levels share conductors, adjacent memory levels preferably have diodes directed in opposite directions, for example, the first memory level of Pin diode downward, adjacent to the second memory level pin diode upward (or vice versa).

[0059] 在一些实施例中,二极管204可以由多晶半导体材料形成,例如多晶硅、多晶硅-锗合金、多晶锗或者其它合适的材料。 [0059] In some embodiments, diode 204 may be formed from a polycrystalline semiconductor material such as polysilicon, polycrystalline silicon - germanium alloy, polycrystalline germanium, or other suitable materials. 举例来说,二极管204可以包括重掺杂的η+多晶硅区域302、η+多晶硅区域302上方的轻掺杂或者本征(非有意掺杂的)多晶硅区域304和本征区域304上方的重掺杂的ρ+多晶硅区域306。 For example, diode 204 may comprise a heavily doped polysilicon region 302 η +, η + lightly doped polysilicon region 302 above the intrinsic or above the heavily doped (unintentionally doped) polysilicon region 304 and the intrinsic region 304 miscellaneous ρ + polysilicon region 306. 在一些实施例中,在η+多晶硅区域302上形成薄的(例如几百埃或者更少的)锗和/或硅-锗合金层(未示出),当使用硅-锗合金时其中锗的含量为大约10at% (原子数百分比为10% )或者更多,以阻挡和/或减少从η+多晶硅区域302到本征区域304的掺杂迁移,如2005年12月9日提交的发明名称为^DEPOSITEDSEMICONDUCTOR STRUCTURE TO MINIMIZE N-TYPE DOPANTDIFFUSION AND METHODOF MAKING”的美国专利申请第11/298,331号(下文中被称为' 331申请)中记载的那样,该申请通过参考全文合并于此。可以理解,η+区和ρ+区的位置是可以互换的。 In some embodiments, a thin (e.g. a few hundred angstroms or less) germanium and / or silicon-on-η + polysilicon region 302 - (not shown), when a silicon-germanium alloy layer - germanium alloy wherein germanium the content of about 10at% (atomic percentage 10%) or more, to block and / or reduce dopant migration from η + polysilicon region 302 into the intrinsic region 304, such as the invention, December 9, 2005, filed entitled ^ DEPOSITEDSEMICONDUCTOR STRUCTURE tO MINIMIZE N-TYPE DOPANTDIFFUSION AND METHODOF MAKING "U.S. Patent application No. 11 / 298,331 (hereinafter referred to as' 331 application) described above, which application is incorporated herein by reference in its entirety. It will be appreciated , η + ρ + area and location area is interchangeable.

[0060] 在一些实施例中,阻挡层308,如氮化钛、氮化钽、氮化钨等,可形成于氧化钛层212和η+区域302之间(例如用来阻挡和/或减小金属原子迁移到多晶硅区域中)。 [0060] In some embodiments, the barrier layer 308, such as titanium nitride, tantalum nitride, tungsten, titanium oxide layer may be formed between 212 and η + region 302 (e.g., for blocking and / or decrease small migration of metal atoms into the polysilicon regions). 使用这样一个金属阻挡层可在阻挡层308和氧化钛层212之间形成不希望的整流接触。 The use of such a barrier metal layer between the barrier layer 308 and the oxide layer 212 is formed undesired rectifying contact. 因此,在一些实施例中,可在氧化钛层212和阻挡层308之间形成一个薄的导体层(图中未示出), 如钛、镍、其它导体材料等(例如,为了功函数调谐),来降低或者阻止整流接触的形成。 Thus, in some embodiments, may be formed of a thin conductive layer (not shown), such as titanium, nickel, other conductive materials between the titanium layer 212 and the barrier layer 308 (e.g., to tune the work function ), to reduce or prevent the formation of a rectifying contact.

[0061] 当通过沉积硅(例如无定形硅或多晶硅)形成二极管204时,在制造过程中二极管204上可以形成硅化物层310以使沉积硅处于低电阻率状态。 [0061] When the diode 204 is formed by depositing silicon (e.g., amorphous or polycrystalline silicon), a diode 204 may be formed during the manufacturing process silicide layer 310 so that the deposited silicon in a low resistivity state. 这样的低电阻率状态允许存储器单元200更容易被编程,因为不需要大的电压来将沉积硅切换到低电阻率状态。 Such a low resistivity state allows for easier memory cell 200 is programmed, because no large voltage will be deposited silicon to a low resistivity state switch. 例如,娃化物形式金属(silicide-forming metal)层312如钛或钴可以被沉积在ρ+多晶娃区域306上。 For example, the form of the baby metal (silicide-forming metal) layer 312 such as titanium or cobalt may be deposited on the polycrystalline baby ρ + region 306. 在随后为了使形成二极管204的沉积硅结晶而采用的退火步骤中(下面将详述),硅化物形式金属层312和二极管204的沉积硅相互作用形成硅化物层310,消耗掉所有的或者一部分娃化物形式金属层312。 In the annealing step subsequent to deposition of the silicon crystal forming the diode 204 employed in the (detailed below), in the form of a metal silicide layer 312 and the deposited silicon of diode 204 interact silicide layer 310 is formed, consume all or a portion of baby in the form of a metal layer 312.

[0062]如美国专利第 7,176,064 号“Memory Cell Comprising aSemiconductorJunction Diode Crystallized Adjacent to a Silicide” 中记载的(该专利通过参考全文合并于此),硅化物形成材料例如钛和/或钴在退火过程中与沉积硅反应形成硅化物层。 In [0062] U.S. Patent No. 7,176,064 "Memory Cell Comprising aSemiconductorJunction Diode Crystallized Adjacent to a Silicide" described in (which is incorporated by reference in its entirety is incorporated herein), silicide-forming materials such as titanium and / or cobalt in the annealing process depositing silicon to form the silicide layer. 硅化钛和硅化钴的晶格间距大小与硅相近,很明显这样的硅化物层在沉积硅结晶时可作为邻近的沉积硅的“结晶模版”或者“籽晶”(例如,硅化物层310在退火时增强硅二极管204的晶体结构)。 Titanium silicide and cobalt silicide and the silicon lattice spacing of similar size, it is clear that such a silicide layer is deposited adjacent the silicon crystal silicon is deposited as "crystalline template" or "seeds" (e.g., silicide layer 310 annealing enhanced silicon diode crystal structure 204). 由此提供低电阻率的硅。 Thereby providing a low-resistivity silicon. 在硅-锗合金二极管和/或锗二极管中也可以得到类似的结果。 Silicon - germanium alloy diodes and / or germanium diodes can also be obtained similar results. [0063] 在硅化物形式金属层312形成以后,形成顶部导体208。 [0063] After the silicide layer 312 is formed in the form of a metal, top conductor 208 is formed. 在一些实施例中,在沉积导体层315之前,在硅化物形式金属层312上形成一个或者多个的阻挡层和/或粘合层314。 In some embodiments, prior to deposition of the conductive layer 315 is formed of one or more barrier layers and / or adhesion layer 314 in the form of a metal silicide layer 312. 导体层315、阻挡层314和硅化物形式金属层312可一起被图案化和/或刻蚀,以形成顶部导体208。 Conductor layer 315, barrier layers 314 and 312 may be patterned and / or etched together form a metal silicide layer to form a top conductor 208.

[0064] 顶部导体208形成后,可以使存储器单元200退火,以使二极管204的沉积半导体材料结晶(和/或形成硅化物层310)。 After the [0064] top conductor 208 is formed, so that the memory cell 200 can be annealed to a crystalline semiconductor material is deposited in the diode 204 (310 and / or the formation of silicide layers). 在至少一个实施例中,退火是在氮气的气氛下在大约600-800°C之间且更优选地在大约650-750°C之间的温度下持续大约10秒至大约2分钟。 In at least one embodiment, annealing is performed under an atmosphere of nitrogen and more preferably at a temperature between about 650-750 ° C lasting about 10 seconds to between about 600-800 ° C for about 2 minutes. 也可以采用其它的退火时间、温度和/或环境。 May be used for further annealing time, temperature and / or the environment. 如前所述,硅化物层310可在退火过程中作为下面沉积的半导体材料的“结晶模板”或者“籽晶”,该半导体材料形成二极管204。 As described above, the silicide layer 310 may be deposited as a semiconductor material under "crystallization template" or "seeds" in the annealing process, the semiconductor material of diode 204 is formed. 由此提供低电阻率的二极管材料。 Thereby providing a low resistivity diode material. [0065] 根据本发明用于制造存储器单元的示例性工艺在下文中结合附图4A-D进行说明。 [0065] will be described in conjunction with the accompanying drawings 4A-D in the following exemplary process according to the present invention for manufacturing a memory cell.

[0066] 存储器单元的示例性制造工艺 [0066] An exemplary manufacturing process of memory cells

[0067] 附图4A-D图示说明根据本发明制造第一存储器级过程中衬底400的一部分的截面图。 [0067] 4A-D illustrate cross-sectional drawings showing a part of a first memory level of the manufacturing process of the substrate 400 according to the present invention. 如下文中将要说明的,第一存储器级包括多个存储器单元,每个存储器单元包括利用选择性生长工艺形成的可逆电阻切换元件。 As will be described, the first memory level comprising a plurality of memory cells, each memory cell comprising a reversible resistance using a selective growth process for forming the switching element. 可以在第一存储器级上方制造另外的存储器级(如之前结合附图2C-2D所述)。 Additional memory levels may be fabricated above the first memory level (e.g., in conjunction with the accompanying drawings before 2C-2D). [0068] 参考图4A,所示的衬底400已经经历了若干工艺步骤。 [0068] Referring to FIG. 4A, the substrate 400 having undergone several process steps. 衬底400可以是任何合适的衬底,如硅、锗、硅-锗、非掺杂的、掺杂的、块状的(bulk)、绝缘体上的硅(SOI)或者其它带有或不带有额外电路的衬底。 The substrate 400 may be any suitable substrate, such as silicon, germanium, silicon - germanium, undoped, doped, bulk is (Bulk), silicon (SOI), or other on-insulator with or without the substrate has additional circuitry. 例如,衬底400可以包含有一个或更多个η-阱或者ρ-阱区域(未示出)。 For example, the substrate 400 may comprise one or more η- ρ- well or well region (not shown).

[0069] 在衬底400上方形成隔离层402。 [0069] The spacer layer 402 is formed over the substrate 400. 在一些实施例中,隔离层402可以是一层氧化硅、氮化硅、氮氧化硅或者其它任何合适的绝缘层。 In some embodiments, the isolation layer 402 may be a layer of silicon oxide, silicon nitride, silicon oxide or any other suitable insulating layer. 在其它的实施例中,绝缘层402是浅的沟槽绝缘(STI)区域,其通过在衬底400内蚀刻沟槽,在衬底400上沉积如氧化硅、氮化硅或者其它电介质以填充沟槽,并对衬底400进行平坦化以重新露出衬底400的顶表面403而形成。 In other embodiments, the insulating layer 402 is a shallow trench isolation (STI) region 400 by etching a trench in a substrate, such as silicon oxide is deposited on the substrate 400, silicon nitride, or other dielectric to fill trench, and planarizing the substrate 400 to re-expose the top surface 403 of the substrate 400 is formed. 注意到在一个或者多个实施例中,在绝缘区形成之前在衬底400的有源区(图中未示出)上形成氮化硅或者类似的保护层(例如为了保护有源区)(图中未示出)。 Note that in one or more embodiments, prior to the insulating region formed in the active region of the substrate 400 (not shown) similar to the embodiment is formed of silicon nitride or a protective layer (e.g., to protect the active region) ( FIG not shown). 作为一个可替代的选择,可使用硅的局部氧化(LOCOS)工艺或者任何其它的合适工艺限定绝缘层402。 As an alternative selection, use local oxidation of silicon (LOCOS) process or any other suitable insulating layer 402 defining process.

[0070] 形成隔离层402后,在隔离层402上方形成粘合层404 (例如,通过物理气相沉积或者其它方法)。 After [0070] forming an isolation layer 402, 404 (e.g., by physical vapor deposition or another method) the adhesive layer is formed over the isolation layer 402. 例如,粘合层404可以是厚度大约为20埃至大约500埃且优选为大约100埃的氮化钛,或者其它合适的粘合层如氮化钽、氮化钨、一个或更多个粘合层的结合等。 For example, the adhesive layer 404 may be a thickness of about 20 angstroms to about 500 angstroms and preferably about 100 angstroms, of titanium nitride or another suitable adhesion layer such as tantalum nitride, tungsten nitride, or a more viscous the sealing layer binding the like. 可以采用其它的粘合层材料和/或厚度。 Adhesive layer may employ other materials and / or thickness. 在一些实施例中,粘合层404是可选的。 In some embodiments, the adhesive layer 404 is optional.

[0071] 形成粘合层后,在粘合层404上方沉积导电层406。 After [0071] forming an adhesive layer, the adhesive layer 404 is deposited over the conductive layer 406. 导电层406可以包括通过任何合适的方法沉积(例如化学气相沉积、物理气相沉积等)的任何合适的导电材料如钨或者其它合适的金属、重掺杂的半导体材料、导电的硅化物、导电的硅-锗化物、导电的锗化物等。 Any suitable conductive material may include depositing a conductive layer 406 (e.g., chemical vapor deposition, physical vapor deposition, etc.) by any suitable method, such as tungsten or other suitable metal, heavily doped semiconductor material, a conductive suicide, a conductive silicon - germanide, a conductive germanide, or the like. 在至少一个实施例中,导电层406可能包括大约200埃至大约2500埃的钨。 In at least one embodiment, conductive layer 406 may comprise about 200 Angstroms to about 2500 Angstroms tungsten. 也可以采用其它的导电材料和/或厚度。 You may also use other conductive materials and / or thickness.

[0072] 导电层406形成后,在导电层406上形成含钛层407,如氮化钛(例如通过物理气相沉积或者其它的方法)。 After [0072] The conductive layer 406 is formed, a titanium-containing layer 407, such as titanium nitride (e.g., by physical vapor deposition or other methods) on the conductive layer 406 is formed. 在一些实施例中,含有钛的层407包括大约20到大约1200埃厚度的钛。 In some embodiments, the titanium layer 407 includes about 20 to about 1200 Angstroms thickness of titanium. 其它的含钛层材料,如钛、钛合金、TiSi2^Tiff等和/或厚度也是可用的。 Other titanium-containing layer material, such as titanium, titanium alloys, TiSi2 ^ Tiff the like and / or thickness are also useful.

[0073] 形成含钛层407后,对粘合层404、导电层406和含钛层407进行图案化和刻蚀。 [0073] After forming a titanium-containing layer 407, adhesion layer 404, conductive layer 406 and a titanium-containing layer 407 is patterned and etched. 例如,通过传统的光刻技术,利用软掩模或者硬掩膜,湿蚀刻或者干刻蚀工艺,对粘合层404、导电层406和含钛层407进行图案化和刻蚀。 E.g., by conventional photolithographic techniques, using a soft mask or a hard mask, a wet etching or a dry etching process, the adhesion layer 404, conductive layer 406 and a titanium-containing layer 407 is patterned and etched. 在至少一个实施例中,对粘合层404和导电层406以及含钛层407进行图案化和刻蚀,以形成基本平行、基本共面的导体408 (如图4Α中所示)。 In at least one embodiment, adhesion layer 404 and conductive layer 406 and a titanium-containing layer 407 is patterned and etched to form substantially parallel, substantially coplanar conductors 408 (as shown in FIG 4Α). 导体408和/或导体408之间的空隙的优选宽度范围在200到2500埃之间,尽管其它的导体宽度和/或空隙宽度也是可用的。 Preferably the width of the gap between the conductor 408 and / or 408 of the conductors 200 to 2500 angstroms, although other conductor widths and / or the gap width are also useful.

[0074] 形成导体408后,在衬底400上方形成介电层410来填充导体408之间的间隙。 After [0074] forming a conductor 408, a dielectric layer 400 over the substrate 408 between a gap 410 filled conductor. 例如,可以在衬底400上沉积大约3000-7000埃的氧化硅,并利用化学机械抛光或回刻工艺将其平坦化以形成平坦表面412。 For example, the substrate 400 may be deposited on the silicon oxide of approximately 3000-7000 angstroms, using chemical mechanical polishing or etch-back process which is planarized to form a planar surface 412. 平坦表面412包括暴露在外的由介电材料410隔开的含钛层材料407的不连续的区域407a-f (如图所示)。 The flat surface 412 comprising a titanium-containing material layer 410 of dielectric material spaced from the outer exposed discontinuous regions 407a-f 407 (as shown). 不连续的含钛层区域407a_f可用于为在衬底400上形成的每个存储单元选择形成氧化钛可逆电阻切换元件(如下文中将要说明的)。 A discontinuous layer containing a titanium oxide region 407a_f be used to form reversible resistance-switching element (which will be described below) of each memory cell is formed on the substrate 400 selected.

[0075] 其它的介电材料如氮化硅,硅的氮氧化物,低K电介质等,和/或其它的介电层的厚度也是可用的。 [0075] Other dielectric materials such as silicon nitride, silicon oxynitride, low K dielectrics, etc., and / or other dielectric layer thicknesses are also useful. 优选的低K电介质包括碳掺杂的氧化物,碳化硅层,或者类似物。 Preferred low K dielectrics include carbon doped oxides, silicon carbide layer, or the like.

[0076] 当通过氧化一种材料而不是含钛的材料来形成可逆电阻切换元件时,可使用要被氧化的材料如Ta、TaN, Nb、NbN, Al、A1N、Hf、HfN, V、VN、等来代替含钛层407。 [0076] When forming a reversible resistance-switching element, a material to be oxidized such as Ta, TaN, Nb, NbN, Al, A1N, Hf, HfN, V, VN by oxidation of a material not containing titanium material , etc. instead of titanium-containing layer 407.

[0077] 参考图4B,平坦化后,在每一个含钛层区域407a_f上形成一个可逆电阻切换元件413a-f。 [0077] Referring to Figure 4B, after planarization, to form a reversible resistance-switching element 413a-f in a titanium-containing layer on each region 407a_f. 例如,通过将含有钛的层区域407a-f氧化而在每个含有钛的层区域407a_f上选择形成氧化钛层。 E.g., 407a-f through the oxide layer region containing titanium dioxide layer is formed is selected on each of the layer region containing titanium 407a_f. 一些或者所有的含有钛的层区域407a-f将在氧化过程中被消耗而产生可逆电阻切换元件413a_f。 Some or all of the titanium-containing layer regions 407a-f will be consumed in the oxidation process and produce a reversible resistance-switching element 413a_f. 如上文中所述的,任何合适的方法都可以用于氧化含钛层区域407a_f,如在氧气、臭氧或者二者共存的氧环境中快速热氧化或者使用其它合适的氧化物质来进行的快速热氧化。 As hereinbefore described, and any suitable method may be used for the titanium oxide-containing layer region 407a_f, such as a rapid thermal oxidation in an oxygen rapid thermal, ozone or both coexist in an oxygen atmosphere or other suitable oxidizing species to oxide . 在其它的实施例中,在含有臭氧或者其它氧源的化学气相沉积腔中通过氧扩散,通过气相或者液相的臭氧清洗,或者通过任何其它合适的氧化处理氧化含钛层区域以形成氧化钛。 In other embodiments, the diffusion of oxygen, ozone cleaning in gas or liquid phase chemical vapor deposition chamber containing ozone, or other oxygen source, a titanium-containing layer region or by any other suitable oxidation process to form a titanium oxide .

[0078] 参考图4C,当可逆电阻切换元件413a_f形成以后,每个存储单元的二极管结构被形成。 [0078] Referring to Figure 4C, When 413a_f form reversible resistance-switching element, the diode structures of each memory cell is formed. 在氧化钛层区域上可形成可选的薄金属层(图中未示出),如大约10埃到大约300埃厚度的钛、镍等(例如为了工作函数调节)。 Titanium oxide layer on a region of an optional thin metal layer (not shown), such as about 10 Angstroms to about 300 Angstroms thickness of titanium and nickel (e.g., to adjust the work function) may be formed. 在一些实施例中,在二极管形成之前,可在氧化钛层区域上形成如氮化钛,氮化钽,氮化钨等的阻挡层(例如,为了阻止或者减小金属原子到多晶硅区域的迁移)。 In some embodiments, prior to formation of the diode may be formed such as titanium nitride, tantalum nitride, tungsten, titanium oxide barrier layer on the layer region (e.g., to prevent or reduce migration of metal atoms into the polysilicon regions of ). 阻挡层414在薄导电层之上的层,除薄导电层之外的层或代替薄导电层的层,并且其可以是厚度为大约20埃至大约500埃且优选为大约100埃的氮化钛或者其它合适的阻挡层如氮化钽、氮化钨、一个或多个阻挡层的结合、阻挡层与其它层的结合如钛/氮化钛、钽/氮化钽或者钨/氮化钨堆叠等。 Layer 414 on the thin conductive layer is a barrier layer, a layer or layers instead of the thin conductive layer except the conductive layer is thin, and its thickness may be about 20 angstroms to about 500 angstroms and preferably about 100 angstroms of nitride the combined tantalum nitride, tungsten nitride, one or more barrier layers of titanium or other suitable barrier layer, the barrier layer in combination with other layers such as titanium / titanium nitride, tantalum / tantalum nitride or tungsten / tungsten nitride stacking and the like. 也可以采用其它的阻挡层材料和/或厚度。 It may also be employed other barrier layer materials and / or thickness.

[0079] 在沉积薄导电层(如果采用)和/或阻挡层414后,开始沉积用于形成每个存储器单元中的二极管(例如图2A-3的二极管204)的半导体材料。 [0079] After depositing a thin conductive layer (if employed), and / or a barrier layer 414, deposition is started for forming the diode of each memory cell (e.g., diode 204 in FIGS. 2A-3) of semiconductor material. 如前所述,每个二极管可以是垂直的P-η或者pin 二极管。 As described above, each diode may be a vertical or a P-η pin diode. 在一些实施例中,每个二极管是由多晶半导体材料如多晶硅、多晶硅-锗合金、锗或者其它合适的材料形成的。 In some embodiments, each diode is a polycrystalline semiconductor such as polysilicon material, polycrystalline silicon - germanium alloy, germanium, or other suitable material. 为了叙述方便,本文描述了一种多晶硅的朝下的二极管的制造过程。 For convenience of description, described herein is a process for producing polycrystalline silicon diode downward. 可以理解,其它的材料和/或二极管结构也是可用的。 It will be appreciated that other materials and / or diode configurations are available.

[0080] 参考图4C,形成阻挡层414后,在阻挡层414上方沉积重掺杂的η+硅层416。 After [0080] Referring to Figure 4C, the barrier layer 414 is formed, the barrier layer 414 is deposited over a heavily doped silicon layer 416 η +. 在一些实施例中,η+硅层416是以无定形状态沉积的。 In some embodiments, η + silicon layer 416 is deposited in an amorphous state. 在其它的实施例中,η+硅层416是以多晶状态沉积的。 In other embodiments, η + silicon layer 416 is deposited a polycrystalline state. 可以采用化学气象沉淀或者其它合适的工艺来沉积η+硅层416。 Chemical vapor precipitation or other suitable process may be employed to deposit η + silicon layer 416. 在至少一个实施例中,η+硅层416可以由例如厚度在大约100埃到大约1000埃之间且使用磷或砷掺杂的硅形成,掺杂浓度为大约1021cm_3。 In at least one embodiment, η + silicon layer 416 may be used for example, and a thickness between about 100 Angstroms to about 1000 Angstroms of silicon doped with arsenic or phosphorous is formed, a doping concentration of about 1021cm_3. 其它的厚度、掺杂剂和掺杂浓度也是可用的。 Other thicknesses, dopant and dopant concentration are also useful. η+硅层416可以是原位掺杂,例如在沉积过程中通入施主气体。 η + silicon layer 416 may be doped in situ, for example, in the deposition process gas into the donor. 其它的掺杂方法也是可用的(例如,离子注入)。 Other doping methods are also available (e.g., ion implantation).

[0081] 沉积η+娃层416后,在η+娃层416上方形成轻掺杂的、本征的和/或非有意掺杂的硅层418。 [0081] After deposition baby η + layer 416, forming a lightly doped, intrinsic and / or unintentionally doped silicon layer 418 over the layer 416 η + baby. 在一些实施例中,本征硅层418是以无定形状态沉积的。 In some embodiments, intrinsic silicon layer 418 is deposited in an amorphous state. 在其它的实施例中,本征硅层418是以多晶状态沉积的。 In other embodiments, intrinsic silicon layer 418 is deposited a polycrystalline state. 可以采用化学气象沉淀或者其它合适的工艺来沉积本征娃层418。 Chemical vapor precipitation or other suitable process may be employed to deposit the intrinsic layer 418 baby. 在至少一个实施例中,本征娃层418的厚度可以为大约500埃到大约4800埃,优选为大约2500埃。 In at least one embodiment, the thickness of the intrinsic layer 418 may be a baby about 500 angstroms to about 4800 angstroms, preferably about 2500 angstroms. 其它的本征层厚度也是可以采用的。 Other intrinsic layer thicknesses may be employed also.

[0082] 在沉积本征硅层418之前,可以在η+硅层416上方形成薄的(例如几百埃或者更薄)的锗和/或硅-锗合金层(未示出),用来阻止和/或减小从η+硅层416到本征硅层418的掺杂剂扩散(如之前合并' 331申请中所记载)。 [0082] Prior to deposition of intrinsic silicon layer 418 may be formed of a thin germanium and / or silicon (e.g. a few hundred angstroms or thinner) in the silicon layer above the η + 416-- germanium alloy layer (not shown), for prevent and / or reduce the η + silicon layer 416 into intrinsic silicon layer 418 dopant diffusion (e.g., before merging the '331 application are described).

[0083] 重掺杂的P型硅被沉积并通过离子注入掺杂或者在沉积过程中原位掺杂来形成P+硅层420。 [0083] The heavily doped P-type silicon is deposited and doped by ion implantation or in-situ doping deposition process to form a P + silicon layer 420. 例如,可以采用表面均匀P+注入将硼注入到本征硅层418内一个预定的深度。 For example, a uniform surface implanted P + boron is injected into a 418 predetermined intrinsic silicon layer depth. 示例性可注入分子离子包括BF2、BF3、B等。 Exemplary molecules implanted ions comprise BF2, BF3, B and the like. 在一些实施例中,可以采用大约IXlO15离子/cm2至5X IO15离子/cm2的注入剂量。 In some embodiments, the ion implantation dose of about IXlO15 / cm2 to 5X IO15 ions / cm2 may be employed. 也可以采用其它的注入种类和注入剂量。 Other implant species and the implantation dose may be employed. 进一步地,在一些实施例中,可采用扩散工艺。 Further, in some embodiments, a diffusion process may be employed. 在至少一个实施例中,最终的P+硅层420的厚度为大约100埃-700埃,尽管其它的p+硅层尺寸也是可用的。 In at least one embodiment, the final thickness of the silicon P + layer 420 is about 100 Å -700 Å, although other p + silicon layer sizes may be available.

[0084] 形成P+娃层420后,在p+娃层420上方沉积娃化物形式金属层422。 [0084] After the baby a P + layer 420, p + deposition in the form of baby doll 420 over metal layer 422. 不例性娃化物形式金属包括溅射的或沉积的钛或钴。 Examples of the baby is not in the form of a metal deposited or sputtered comprises titanium or cobalt. 在一些实施例中,硅化物形式金属层422具有大约10埃到大约200埃的厚度,优选为大约20埃到大约50埃,且更优选为大约20埃。 In some embodiments, the form of the metal silicide layer 422 having a thickness of about 10 angstroms to about 200 angstroms, preferably about 20 angstroms to about 50 angstroms, and more preferably about 20 angstroms. 其它的硅化物形式金属层材料和/或厚度也是可用的。 Other forms metal silicide layer materials and / or thicknesses are also useful.

[0085] 在硅化物形式金属层422上方沉积阻挡层424。 [0085] In the above form of a metal silicide layer 422 is deposited a barrier layer 424. 阻挡层424可以是厚度为大约20埃到大约500埃且优选为大约100埃的氮化钛或者其它合适的阻挡层如氮化钽、氮化钨、一个或者多个阻挡层的结合、阻挡层与其它层的结合如钛/氮化钛、钽/氮化钽、钨/氮化钨堆叠等。 The barrier layer 424 may be a thickness of about 20 angstroms to about 500 angstroms and preferably about 100 angstroms, of titanium nitride or another suitable barrier layer such as tantalum nitride, tungsten, or binding a plurality of barrier layers, the barrier layer combined with other layers such as titanium / titanium nitride, tantalum / tantalum nitride, tungsten / tungsten nitride stacking and the like. 也可以采用其它的阻挡层材料和/或厚度。 It may also be employed other barrier layer materials and / or thickness. [0086] 形成阻挡层424后,在阻挡层424上方形成导电层426。 After [0086] forming a barrier layer 424, conductive layer 426 is formed over the barrier layer 424. 导电层426是厚度为大约50埃到大约1000埃且优选为大约500埃的导电材料,如钨或者其它合适的金属。 A conductive layer 426 having a thickness of about 50 Angstroms to about 1000 Angstroms and preferably about 500 Angstroms of conductive material, such as tungsten or other suitable metal.

[0087] 然后阻挡层414、硅区域416、418和420、硅化物形式金属层422、阻挡层424和导电层426被图案化并被刻蚀成柱428。 [0087] Then the barrier layer 414, silicon regions 416, 418 and 420, in the form of a metal silicide layer 422, barrier layer 424 and the conductive layer 426 is patterned and etched into column 428. 例如,最开始时,导电层426和阻挡层424被刻蚀。 For example, initially, the conductive layer 426 and barrier layer 424 is etched. 然后刻蚀继续进行,刻蚀硅化物形式金属层422、硅区域420、418和416以及阻挡层414。 Then etching continues, is etched in the form of a metal silicide layer 422, silicon regions 420, 418 and 416, and barrier layer 414. 在对硅进行刻蚀的时候,导电层426和阻挡层424作为硬掩膜。 When silicon is etched, the conductive layer 426 and the barrier layer 424 as a hard mask. 硬掩膜是一个刻蚀过的层,其用于对下面的层进行图案化刻蚀;如果导电层426上的所有光刻胶都被消耗掉的话,硬掩膜可以代替其提供图案。 The etched hard mask is a layer for the underlying layer is patterned etching; if all of the photoresist on the conductive layer 426 is consumed, then the hard mask pattern is provided which may be substituted. 以这种方法,只用一次光刻步骤就可以形成柱428。 In this way, only one photolithography step column 428 may be formed. 可以采用传统的光刻技术以及湿法或干法刻蚀工艺来形成柱428。 Column 428 may be formed using conventional photolithography and wet or dry etch process. 每个柱428包括pin型的朝下的二极管430。 Each post 428 includes a downwardly facing pin-type diodes 430. 类似地可以形成朝上的pin 二极管。 Similarly, a pin diode may be formed upwardly.

[0088] 形成柱428后,在柱428上方沉积介电层432,用于填充柱428之间的空隙。 After the [0088] form pillars 428, 428 in the column above the dielectric layer 432 is deposited, for filling the gap between the column 428. 例如,大约200-7000埃的氧化硅可以被沉积,然后利用化学机械抛光或回蚀工艺进行平坦化以形成平坦表面434。 For example, approximately 200-7000 angstroms of silicon oxide may be deposited, and then using chemical mechanical polishing or planarization etch-back process to form a planar surface 434. 平坦表面434包括被介电材料432分隔开的柱428的裸露顶表面(如图所示)。 The flat surface 434 includes exposed top surface 432 is spaced apart columns 428 of a dielectric material (as shown). 其它的介电材料如氮化硅、氮氧化硅、低K介电材料等和/或其它的介电层厚度也是可用的。 Other materials, such as dielectric and / or other dielectric layer thicknesses of silicon nitride, silicon oxynitride, low K dielectric materials, are also useful. 优选的低K介电材料包括碳掺杂的氧化物、碳化硅层等。 Preferred low K dielectric materials include carbon-doped oxide, silicon carbide layer.

[0089] 形成平坦表面434后,在每个柱428上方选择性地形成可逆电阻切换元件436 (图4C)。 After [0089] forming planar surface 434, to selectively form a reversible resistance-switching element 436 (FIG. 4C) above each column 428. 例如,可以通过选择性沉积(I)氧化镍;和/或(2)选择性沉积镍然后将镍氧化的方式在每个导电的柱428上方选择性地形成氧化镍层。 For example, by selective deposition (I) nickel oxide; / or (2) selective deposition of nickel and nickel oxide selective manner and nickel oxide layer formed above each of the conductive pillar 428. 在上述任一种情况下,都可以省去刻蚀镍和/或氧化镍层的步骤,明显简化存储器单元的制造。 In either case, the steps are omitted etching nickel and / or nickel oxide layer, significantly simplifies the manufacturing of the memory cell. 如上所述,可以使用选择性沉积镍或氧化镍的任何合适的方法,如化学沉积、电镀等。 As described above, may be used any suitable method selectively depositing a nickel or nickel oxide, such as chemical deposition, plating and the like. 在至少一个实施例中,在每个导电柱428上方形成的可逆电阻切换元件436都包括氧化镍层,该氧化镍层具有1000埃或更小的厚度优选厚度为500埃或更小。 In at least one embodiment, is formed above the reversible resistance of each conductive post 428 includes a switching element nickel oxide layer 436, nickel oxide layer having 1000 angstroms or less, preferably a thickness of 500 angstroms thickness or less. 可以采用其它氧化镍厚度。 Other nickel oxide thickness may be employed. 氧化镍层可以包括例如NiO、NiOj^P NiOxPy或者其它类似的材料。 Nickel oxide layer may comprise, for example, NiO, NiOj ^ P NiOxPy or other similar materials. 其它材料例如Nb、V、Al、Ti、Co、钴-镍合金等可以类似地被选择性沉积、氧化和/或退火以在每个柱428上方形成选择性沉积的可逆电阻率切换。 Other materials such as Nb, V, Al, Ti, Co, Co - Ni alloy, etc. may similarly be selectively deposited, oxidation and / or anneal to form a reversible resistivity-switching selectively deposited above each column 428.

[0090] 参考图4D,形成可逆电阻切换元件436后,可以以类似于底部的一组导体408的形成方法在柱428上方形成第二组导体438。 [0090] Referring to Figure 4D, after forming the reversible resistance-switching element 436 may be similar to the method of forming the bottom of a set of conductors 408 of the conductor 438 is formed over the second set of column 428. 例如,如图4D所示,在一些实施例中,在沉积用于形成上部第二组导体438的导电层442之前,可以在可逆电阻切换元件436上方沉积一个或更多个阻挡层和/或粘合层440。 For example, shown in Figure 4D, in some embodiments, prior to the deposition of the conductive layer for forming the upper portion 438 of the second set of conductors 442, 436 deposited elements can be switched over one or more barrier layers and a reversible resistance / or The adhesive layer 440.

[0091] 当η+娃层416,本征娃层418形成以后,η+娃层416、本征娃层418、阻挡层414和/或任何导体层(如果需要的话)被图案化并刻蚀以形成位于导体408上的硅柱420 (如图)。 [0091] When η + baby layer 416, an intrinsic baby layer 418 is formed, η + baby layer 416, an intrinsic baby layer 418, barrier layer 414 and / or any conductor layer (if required) are patterned and etched to form a silicon pillar 408 positioned on the conductor 420 (as shown). 传统的光刻技术,使用软掩模或硬掩膜以及湿蚀刻和干刻蚀工艺都可以用于形成硅柱420。 Conventional photolithographic techniques, with a soft mask or a hard mask, and wet etching and a dry etching process may be used to form silicon pillars 420.

[0092] 硅柱420形成以后,沉积介电层422用以填充硅柱420之间的空隙。 After the [0092] silicon pillar 420 is formed, a dielectric layer 422 is deposited to fill the gap between the silicon pillars 420. 例如,可以沉积大约200-7000埃厚度的氧化硅,然后通过化学机械抛光或者回蚀工艺将其平坦化以形成平坦表面424。 For example, silicon oxide may be deposited about 200-7000 Angstroms thickness, and then by chemical mechanical polishing or an etchback process which is planarized to form a planar surface 424. 平坦表面424包括被介电材料422分隔开的娃柱420的裸露的顶面(如图所示)。 The flat surface 424 includes exposed top surface 422 is spaced apart from the dielectric material baby column 420 (as shown). 其它的介电材料如氮化硅,氮氧化硅,低K值介电材料等,和/或其它的介电层厚度也是可用的。 Other dielectric materials such as silicon nitride, silicon oxynitride, low K dielectric materials, and / or other dielectric layer thicknesses are also useful. 优选的低K值介电材料包括碳掺杂的氧化物,碳化硅层,或者类似物。 Preferably the low-K dielectric materials include carbon-doped oxide, silicon carbide layer, or the like.

[0093] 娃柱420形成以后,在每个娃柱内,靠近娃柱420的上表面部分形成一个ρ+娃区域。 [0093] After the post 420 formed baby, baby in each column, the upper surface portion 420 is formed near a baby post baby ρ + region. 例如,可以通过表面P+注入,将硼注入硅柱420内预定的深度。 For example, the surface can be a P + implantation, implanting boron into a predetermined depth in the silicon pillar 420. 优选的注入分子离子包括BF2、BF3、B和类似物。 Preferred molecular ion implantation include BF2, BF3, B and the like. 在一些实施例中,采用大约1-5Χ IO15离子/cm2的注入剂量。 In some embodiments, using an ion implantation dose of about 1-5Χ IO15 / cm2. 也可以采用其它的注入元素和注入剂量。 Other elements of the injection and implantation dose may also be employed. 进一步地,在一些实施例中,可采用扩散工艺以掺杂硅柱420的上部部分。 Further, in some embodiments, a diffusion process may be employed to dope the upper portion of the silicon pillar 420. 在至少一个实施例中,ρ+硅区域426的厚度为大约100-700埃,尽管其它的P+硅区域的厚度也是可用的。 In at least one embodiment, ρ + silicon region 426 thickness of about 100-700 angstroms, although other thickness of the silicon P + regions are also available. (需要提醒的是,如果形成的二极管是朝上的pn或者pin 二极管,硅柱420的上部将会被η型掺杂)。 (A reminder that, if the diode is formed upwardly a pn or pin diode, an upper portion of the silicon pillar 420 will be η-type doping). 如此,每个硅柱420上就包括了一个朝下的Pin 二极管428。 As such, each silicon pillar 420 including a downwardly facing Pin diode 428.

[0094] 参考图4D,pin 二极管428形成以后,在衬底400上沉积一层硅化物形式金属层430。 [0094] Referring to Figure 4D, after the pin diode 428 is formed, the silicide layer 430 in the form of a metal layer 400 deposited on the substrate. 优选的娃化物形式金属包括派射或者其它方式沉积的钛或者钴。 Preferred forms of the metal compounds include baby send exit or otherwise deposited titanium or cobalt. 在一些实施例中,娃化物形式金属层130具有大约10到大约200埃的厚度,优选大约20到大约50埃,更优选大约20埃。 In some embodiments, the baby in the form of a metal layer 130 has a thickness of about 10 to about 200 angstroms, preferably about 20 to about 50 angstroms, and more preferably about 20 angstroms. 其它的硅化物形式金属层材料和/或厚度也是可用的。 Other forms metal silicide layer materials and / or thicknesses are also useful. 如下文中将要说明的,对结构的退火会引起娃化物形式金属层430中的金属与ρ+娃区域426中的娃反应以在邻近每个P+硅区域426处形成硅化物区域432。 As will be described, the structure of the annealed metal can cause ρ + region 426 of the baby doll in the form of a metal compound 430 baby bed reactor adjacent to each silicon P + region 426 is formed a silicide region 432.

[0095] 硅化物形式金属层430形成以后,通过与形成底部导体408相似的方法在二极管428上形成第二组导体436。 After [0095] the form of a metal silicide layer 430 is formed, bottom conductor formed by a method similar to 408 formed on a second set of conductors 436 in the diode 428. 在一些实施例中,在沉积导电层440之前,在硅化物形式金属层430上形成一个或者多个阻挡层和/或粘结层438,以用于形成上部的第二组导体436。 In some embodiments, prior to deposition of the conductive layer 440, the one or more barrier layers and / or adhesion layer 438 is formed in the form of a metal silicide layer 430, a second set of conductors 436 for forming an upper portion.

[0096] 导电层440可使用任何合适的导电材料如钨、其它合适的金属、重掺杂的半导体材料、导电的硅化物、导电的硅化物-锗化物、导电的锗化物等通过任何合适的方法(如化学气象沉淀、物理汽相沉淀等)来形成。 [0096] conductive layer 440 may be any suitable conductive material such as tungsten, another suitable metal, heavily doped semiconductor material, electrically conductive suicide, a conductive silicide - germanide, through a conductive germanide, or the like of any suitable The method (e.g., chemical vapor precipitation, physical vapor deposition, etc.) are formed. 可以使用其它导电层材料。 Other conductive layer materials may be used. 阻挡层和/或粘合层438可包括氮化钛或其它合适的层例如氮化坦、氮化钨、一个或几个层的结合或者任何其它的合适材料。 Barrier layer and / or adhesion layers 438 may include titanium nitride or another suitable layer such as nitrides Tan, tungsten nitride, or a conjunction of several layers or any other suitable material. 沉积的导电层440和阻挡层和/或粘合层438和/或硅化物形式金属层430可被图案化和/或被刻蚀以形成第二组导体438。 Deposited conductive layer 440 and the barrier layer and / or adhesive layers 438 and / or in the form of a metal silicide layer 430 may be patterned and / or etched to form a second set of conductors 438. 在至少一个实施例中,上部导体436是大致平行、大致共面的导体,其与底部导体408沿着不同的方向延伸。 In at least one embodiment, upper conductors 436 are substantially parallel, substantially coplanar conductors that extend along the bottom conductor 408 in different directions.

[0097] 形成上部导体436后,该结构可以被退火以使二极管428的沉积的半导体材料结晶(和/或形成硅化物区域432)。 After [0097] forming the upper conductor 436, the structure may be annealed to a crystalline semiconductor material deposited diode 428 (and / or forming a silicide region 432). 在至少一个实施例中,退火在600°C到800°C的温度下在氮气气氛中进行大约10秒到大约2分钟,优选在650°C到750°C的温度范围中。 In at least one embodiment, the annealing at 600 ° C in a nitrogen atmosphere to 800 ° C at a temperature of about 10 seconds to about 2 minutes, preferably at 650 ° C to a temperature in the range of 750 ° C. 可以使用其它退火时间、温度和/或环境。 Other annealing times may be used, the temperature and / or the environment. 在每个硅化物形式金属区域422与ρ+区域420反应时形成的硅化物区域432在退火过程中可以作为下面沉积的形成二极管432的半导体材料的“结晶模板”或“籽晶”(例如,将任何无定形半导体材料变为多晶半导体材料和/或提高二极管432的整体结晶性质)。 Silicide region 432 formed in the reactor 420 each form metal silicide regions 422 and ρ + region during annealing may be formed as a diode semiconductor material deposited below 432 "crystallization template" or "seeds" (e.g., any amorphous semiconductor material to polycrystalline semiconductor material changes and / or improving overall crystalline properties of the diodes 432). 由此提供低电阻率的二极管材料。 Thereby providing a low resistivity diode material.

[0098] 可替代的示例性存储器单元 [0098] Alternatively exemplary memory cell

[0099] 图5是根据本发明提供的示例性存储器单元500的截面图。 [0099] FIG. 5 is a cross-sectional view 500 of an exemplary memory cell in accordance with the present invention is provided. 存储器单元500包括薄膜晶体管(TFT),如薄膜金属氧化物半导体场效应晶体管(MOSFET) 502,该晶体管与形成于衬底505上方的可逆电阻切换元件504耦连。 The memory unit 500 includes a thin film transistor (TFT), thin film metal-oxide semiconductor field effect transistor (MOSFET) 502, the transistor is formed above the reversible resistance-switching element 504 substrate 505 is coupled. 例如,MOSFET 502可以是形成在任何合适的衬底上的η沟道或ρ沟道薄膜M0SFET。 For example, MOSFET 502 may be formed η or ρ-channel thin film M0SFET channel on any suitable substrate. 在图示的实施例中,在衬底505上方形成绝缘区域506如二氧化硅、氮化硅、氮氧化物等,然后在绝缘区域506上方形成沉积的半导体区域507如沉积的硅、锗、硅-锗等。 In the illustrated embodiment, an insulating region 506 such as silicon dioxide, silicon nitride, oxide 505 over the substrate, and then forming a deposited semiconductor region 507 such as deposited silicon, germanium over the insulating region 506, silicon - germanium. 薄膜MOSFET 502形成于沉积的半导体区域507内,并通过绝缘区506与衬底505绝缘。 Semiconductor region 507 is formed in the thin film deposition MOSFET 502, and 506 and the insulating substrate 505 by an insulating region.

[0100] MOSFET 502包括源极/漏极区508、510和沟道区512,以及栅介电层514、栅电极516和间隔区518a-b。 [0100] MOSFET 502 comprises 512, and the gate dielectric layer 514, the gate electrode 516 and spacers 518a-b of the source / drain regions 508, 510 and the channel region. 在至少一个实施例中,源极/漏极区508、510可以是ρ型掺杂,沟道区512可以是η型掺杂,而在其它的实施例中源极/漏极区508、510可以是η型掺杂,沟道区512可以是ρ型掺杂。 In at least one embodiment, the source / drain regions 508, 510 may be a ρ-type doped channel region 512 may be a η-type dopant, while in other embodiments, the source / drain regions 508, 510 may be a η-type doped channel region 512 may be a ρ-doped. 任何其它的MOSFET结构或者任何合适的制造技术都可以用于薄膜MOSFET 502。 Any other suitable MOSFET structure or any manufacturing technique may be used for film MOSFET 502. 在一些实施例中,通过衬底506内形成(如通过使用STI、L0C0S或其它类似工艺形成)的绝缘区(未示出)来使MOSFET 502电绝缘。 In some embodiments, form (e.g., formed by using a STI, L0C0S or other similar process) an insulating region (not shown) within the substrate 506 to make the MOSFET 502 is electrically insulated. 可替代地,MOSFET 502的栅极、源极区和/或漏极区可以与在衬底506上形成的其它晶体管(未示出)共用。 Alternatively, the gate of the MOSFET 502, the source region and / or drain regions may be shared with other transistors (not shown) formed on the substrate 506.

[0101] 可逆电阻切换元件504包括下导体520,形成于下导体520上的含钛层521,在含钛层521上选择生长的氧化钛层522以及在可逆电阻切换材料(氧化钛层522)上形成上导体524。 [0101] Reversible resistance-switching element 504 includes a lower conductor 520, formed on the lower titanium layer 521 on the conductor 520, selected on the titanium-containing oxide layer 521 is grown on layer 522 and the reversible resistance-switching material (titanium oxide layer 522) conductor 524 is formed. 上导体和下导体520,524可包括任何合适的导电材料如钨、其它的金属、重掺杂的半导体材料、导电的硅化物、导电的硅化物-锗化物、导电的锗化物或者类似物。 Upper conductor and the lower conductor 520, 524 may comprise any suitable conductive material such as tungsten, other metal, heavily doped semiconductor material, a conductive suicide, a conductive silicide - germanide, a conductive germanide, or the like. 在一些实施例中,在上导体和下导体520、524和可逆电阻切换材料(氧化钛层522)之间还有一个或者多个阻挡层和/或粘合层(图中未示出)。 In some embodiments, the conductors and between the upper and lower conductors 520, 524 reversible resistance-switching material (titanium oxide layer 522) there is one or more barrier layers and / or adhesive layer (not shown).

[0102] 在至少一个实施例中,可逆电阻切换材料(氧化钛层522)是通过上文结合附图I-图4D的实施例记载的选择生长工艺形成的。 [0102] In at least one embodiment, the reversible resistance-switching material (titanium oxide layer 522) is above I- DRAWINGS FIG selected by growth process described in Example 4D embodiment is formed. 例如,通过在氧环境中如O2、臭氧、或者它们的结合,或者使用其它任何合适的氧化空间对含有钛的层521实施快速热氧化而选择性地形成氧化钛层522。 For example, titanium layer 522 such as by O2, ozone, or a combination thereof, or any other suitable space oxide layer 521 containing titanium embodiments a rapid thermal oxidation selectively formed in an oxygen environment. 在其它的实施例中,在含有臭氧或者其它氧源的化学气相沉积(CVD)腔中通过氧扩散,通过气相或者液相的臭氧清洗,或者通过任何其它合适的氧化工艺氧化含钛层521以形成氧化钛层522。 In other embodiments, a chemical vapor deposition (CVD) or other oxygen containing ozone source chamber containing the titanium layer 521 by diffusion of oxygen, ozone cleaning gas or liquid phase, or by any other suitable oxidation process is oxidized to forming a titanium oxide layer 522. 在任何的实施例中,都不需要对氧化钛层进行刻蚀,存储单元的执照得以显著简化。 In any embodiment, do not require etching the oxide layer, the license storage unit can be significantly simplified. 根据本发明,其它的材料也可以被选择氧化以形成用于存储单元500的可逆电阻切换材料(如Ta、TaN、Nb、NbN, Al、A1N、Hf、HfN、V和VN等)。 According to the present invention, other materials may also be selected oxidized to form a reversible resistance-switching unit 500 for storing the material (e.g., Ta, TaN, Nb, NbN, Al, A1N, Hf, HfN, V and VN, etc.).

[0103] 如图5所示,可逆电阻切换元件504通过第一导电栓塞526与MOSFET 502的源极/漏极区510耦连,并通过第二导电栓塞530(其延伸穿过介电层532)与第一金属级(Ml)线528耦连。 [0103] As shown in FIG 5, the reversible resistance-switching element 504 through conductive plug 526 and the source of the first MOSFET 502 of the source / drain region 510 is coupled, through a second conductive plug 530 (which extends through the dielectric layer 532 ) and the first metal level (of Ml) is coupled to line 528. 同样地,第三导电栓塞534将MOSFET 502的源极/漏极区508与MI线536耦连。 Similarly, the third conductive plug 534 to source 502 of MOSFET source / drain regions 508 and 536 is coupled to line MI. 导电栓塞和/或线可以用任何合适的金属如钨、其它金属、重掺杂的半导体材料、导电的硅化物、导电的硅-锗化物、导电的锗化物等形成(带有或不带有阻挡层)。 Conductive plug and / or wire may be any suitable metal such as tungsten, other metal, heavily doped semiconductor material, a conductive suicide, a conductive silicon - germanium are formed, a conductive germanide, or the like (with or without barrier layer). 需要注意的是,当MOSFET为η-沟道器件时,区域508作为MOSFET 502的漏极区而区域510作为MOSFET502的源极区;当MOSFET为ρ-沟道器件时,区域508作为MOSFET 502的源极区而区域510作为MOSFET 502的漏极区。 Note that, when the MOSFET is η- channel device, region 508 as a drain region of MOSFET 502 and the source region 510 as the region MOSFET502; ρ- channel when the MOSFET is a device, a region 508 of MOSFET 502 the source region and the drain region 510 as a region of the MOSFET 502. 介电层532包括任何合适的介电材料如二氧化硅、氮化硅氮氧化硅、低K介电材料等。 The dielectric layer 532 comprises any suitable dielectric material such as silicon dioxide, silicon nitride, silicon oxynitride, low K dielectric materials.

[0104] 在存储器单元500中,薄膜MOSFET 502用作控向元件,其工作方式与图2A-4D中的存储器单元使用的二极管的工作方式类似,选择性地限制施加到可逆电阻切换元件504两端的电压和/或流过可逆电阻切换元件504的电流。 [0104] In the memory cell 500, the thin film MOSFET 502 works like the control unit for use as the element, which works with the memory of FIG. 2A-4D diode, is applied to selectively limiting reversible resistance-switching element 504 two voltage terminal and / or the current flow through reversible resistance-switching element 504.

[0105] 在至少一个实施例中,可逆电阻切换元件504包括厚度为大约500埃或更少的氧化钛层,优选厚度为大约300埃或更少。 [0105] In at least one embodiment, the reversible resistance-switching element 504 includes a thickness of about 500 Angstroms or less of titanium oxide layer, preferably a thickness of about 300 Angstroms or less. 可以采用其它的氧化钛厚度。 Other thickness of the titanium oxide may be employed.

[0106] 前述内容只公开了本发明的优选实施例。 [0106] The foregoing discloses only the preferred embodiments of the present invention. 落在本发明范围内的上面公开的设备和方法的修改对本领域技术人员来说是显而易见的。 It falls modifying device and method disclosed above within the scope of the invention to those skilled in the art will be apparent. 例如,尽管本发明主要描述了选择性氧化氮化钛,但应该理解其它材料也可以被选择性氧化以用于可逆电阻切换元件,形成例如Ta、TaN、Nb、NbN, Al、A1N、Hf、HfN、V 和VN 等。 For example, although the present invention is primarily described with titanium oxide selectively, it is to be understood that other materials may also be selectively oxidized to a reversible resistance-switching element formed for example Ta, TaN, Nb, NbN, Al, A1N, Hf, HfN, V and VN and so on.

[0107] 因此,虽然已经通过其示例性实施例公开了本发明,但应该理解,如,其它实施例也可能落入随附的权利要求所限定的本发明的主旨和保护范围内。 [0107] Thus, while the invention has been disclosed exemplary embodiments thereof, it is to be understood that such other embodiments are possible within the spirit and scope of the invention, the appended claims as defined.

Claims (15)

1. ー种形成存储器単元的方法,所述方法包括: 在衬底上方形成控向元件,其中形成所述控向元件包括形成垂直多晶ニ极管; 通过下面的步骤选择性地形成与所述控向元件耦连的可逆电阻切換元件: 在所述衬底上形成材料层; 蚀刻所述材料层;和氧化所蚀刻的材料层以形成可逆电阻切換材料;和形成与所述垂直多晶ニ极管的多晶材料接触的硅化物、硅-锗化物和锗化物区域,以便所述多晶材料处于低电阻率状态。 A method of forming a memory ー species radiolabeling element, the method comprising: forming a steering element above the substrate, wherein forming the control element is formed perpendicular to the diode comprises a polycrystalline Ni; and is formed by the steps of selectively said control reversible resistance-switching element coupled to the element: forming a material layer on the substrate; etching the layer of material; the material layer and the oxide etched to form a reversible resistance-switching material; and forming with the vertical polycrystalline Ni silicide polycrystalline material contact diode, a silicon - germanium compounds and germanium region thereof so that the polycrystalline material is in a low resistivity state.
2.如权利要求I所述的方法,其中所述材料层包括Ta、TaN、Nb、NbN、Al、AlN、Hf、HfN、V和VN中的一种或更多种。 2. The method of claim I, wherein said material layer comprises a Ta, TaN, Nb, NbN, Al, AlN, Hf, HfN, V and VN or more thereof.
3.如权利要求I所述的方法,其中所述可逆电阻切换材料包括Ta205、Nb205、Al203、Hf02和V2O5中的ー种或多种。 The method of claim I as claimed in claim 3, wherein the reversible resistance-switching material comprises one or more ー Ta205, Nb205, Al203, Hf02 and V2O5 in.
4.如权利要求I所述的方法,其中形成所述控向元件包括形成pn ニ极管或pin ニ极管。 4. The method of claim I, wherein forming the steering element comprises a diode or a pn ni ni pin diode.
5.如权利要求I所述的方法,其中选择性地形成可逆电阻切換元件包括形成具有约500埃或更薄厚度的氧化物的可逆电阻切换元件。 5. The method of claim I, wherein selectively forming a reversible resistance-switching element comprises a reversible resistance-forming oxides having a thickness of about 500 Angstroms or less of a switching element.
6.如权利要求I所述的方法,其中选择性地形成可逆电阻切換元件包括形成具有约300埃或更薄厚度的氧化物的可逆电阻切换元件。 6. The method of claim I, wherein selectively forming a reversible resistance-switching element comprises a reversible resistance-forming oxides having a thickness of about 300 Angstroms or less of a switching element.
7.如权利要求I所述的方法,进ー步包括将所述控向元件与所述可逆电阻切換元件串联。 7. The method of claim I, further comprising ー into said control element to reversibly switching element connected in series with the resistor.
8.根据权利要求I所述的方法形成的存储器単元。 The memory according to claim I of the radiolabeling method of forming element.
9. ー种形成存储器単元的方法,所述方法包括: 在衬底上方形成第一导体; 由下面步骤在所述第一导体上方选择性地形成可逆电阻切換元件: 在所述衬底上形成材料层; 蚀刻所述材料层;和氧化所蚀刻的材料层以形成可逆电阻切換材料; 在所述第一导体上方形成ニ极管,其中形成所述ニ极管包括形成垂直多晶ニ极管;在所述ニ极管和所述可逆电阻切換元件上方形成第二导体;和形成与所述垂直多晶ニ极管的多晶材料接触的硅化物、硅-锗化物或锗化物区域,以便所述多晶材料处于低电阻率状态。 9. A method of forming a memory ー species radiolabeling element, the method comprising: forming a first conductor above a substrate; manufactured by the steps of selectively forming a reversible resistance-switching element above the first conductor: forming on said substrate material layer; etching the material layer; and etching the material layer to form the oxide reversible resistance-switching material; Ni is formed over the first conductor diode, wherein forming comprises forming said Ni electrode tube a vertical polycrystalline diode ni ; pole tube and the second conductor is formed reversible resistance switching element above the ni; and forming a polycrystalline material of the vertical polycrystalline diode Ni silicide contact, silicon - germanide or germanide region in order to the polycrystalline material is in a low resistivity state.
10.如权利要求9所述的方法,其中所述材料层包括Ta、TaN、Nb、NbN、Al、AlN、Hf、HfN、V和VN中的一种或更多种。 10. The method according to claim 9, wherein said material layer comprises a Ta, TaN, Nb, NbN, Al, AlN, Hf, HfN, V and VN or more thereof.
11.如权利要求9所述的方法,其中所述可逆电阻切換材料包括形成Ta205、Nb2O5.Al2O3, HfO2和V2O5中的一种或更多种。 11. The method according to claim 9, wherein the reversible resistance-switching material comprises formation of a Ta205, Nb2O5.Al2O3, HfO2, and one or more of V2O5.
12.如权利要求9所述的方法,其中选择性地形成所述可逆电阻切換元件包括形成具有约500埃或更薄厚度的氧化物的可逆电阻切换元件。 12. The method according to claim 9, wherein selectively forming the reversible resistance-switching element includes reversible resistance-forming oxides having a thickness of about 500 Angstroms or less of a switching element.
13.如权利要求9所述的方法,其中选择性地形成所述可逆电阻切換元件包括形成具有约300埃或更薄厚度的氧化物的可逆电阻切換元件。 13. The method according to claim 9, wherein selectively forming the reversible resistance-switching element comprising forming an oxide having a thickness of about 300 Angstroms or less of the reversible resistance-switching element.
14.使用权利要求9,进ー步包括将所述ニ极管和所述可逆电阻切換元件串联。 14. Use as claimed in claim 9, further comprising the feed ー ni diode and the reversible resistance-switching element in series.
15.根据权利要求9所述的方法形成的存储器単元。 15. The memory according to claim 9 formed by radiolabeling element.
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