WO2006117907A1

WO2006117907A1 - Methods for manufacturing semiconductor element and circuit board, and semiconductor element and circuit board

Info

Publication number: WO2006117907A1
Application number: PCT/JP2006/301444
Authority: WO
Inventors: Takeshi Hara; Yuichi Saito
Original assignee: Sharp Kabushiki Kaisha
Priority date: 2005-04-28
Filing date: 2006-01-30
Publication date: 2006-11-09

Abstract

Methods for manufacturing semiconductor element and circuit board by which selective film forming is made possible and a number of times of photolithography required for forming an element structure is reduced, a semiconductor element, a circuit board, an electronic device and a display device obtained by using such methods are provided. The method for manufacturing semiconductor element is a method for manufacturing a semiconductor element having a channel and includes a step of forming a functional layer by dropping a functional material having fluidity in a channel groove.

Description

Specification

SEMICONDUCTOR ELEMENT AND CIRCUIT BOARD MANUFACTURING METHOD, SEMICONDUCTOR ELEMENT AND CIRCUIT BOARD

Technical field

The present invention relates to a semiconductor element, a method for manufacturing a circuit board, and a semiconductor element, a circuit board, and an electronic device. More specifically, a method for manufacturing a semiconductor element suitable for manufacturing a thin film transistor or the like, a method for manufacturing a circuit board suitable for manufacturing an active matrix substrate or the like, a semiconductor element such as a thin film transistor, or a circuit substrate such as an active matrix substrate or the like. And an electronic apparatus such as an imaging apparatus, an image input apparatus, and a display apparatus. Background art

[0002] Semiconductor substrates typified by silicon (Si) substrates, glass substrates typified by alkali glass substrates and non-alkali glass substrates, glass-epoxy substrates used for printed wiring boards, flexible substrates, display applications, and other widely used Photolithography is often used when it is required to form a fine pattern thin film with high accuracy on a substrate such as a plastic substrate, which is used for precise pattern wiring and display.

In general photolithography, first, a resist material (photoresist material) having photosensitivity is applied to the entire surface of a substrate, and a heat treatment is performed to obtain a resist film. Subsequently, exposure is performed using an exposure apparatus such as a stepped projection exposure apparatus (stepper) and a photomask having a predetermined pattern. Subsequently, the resist pattern film is obtained on the substrate by developing with a developer containing an organic alkali or the like. Subsequently, using the resist pattern film as a mask, the substrate is exposed to an etching atmosphere by a wet etching method or a dry etching method, whereby the thin film on the substrate is processed into a predetermined pattern. The resist pattern film is removed at a suitable stage with a stripping solution containing an organic solvent or the like.

In such photolithography, it is advantageous in manufacturing to reduce the number of times of producing the resist pattern film as much as possible. Many attempts have been made to reduce the number of times the resist pattern film is produced by optimizing the structure of the target device and wiring.

[0005] In recent years, the inkjet technology developed for printer applications has been It was considered to be used for production. This is a technique for forming a metal film having a pattern directly on a substrate by an ink-jet method, and production of wiring and passive elements (capacitor resistance, inductor) is considered. In this technology, droplets containing metal fine particles are used to make wiring, and droplets containing metal oxide material are used to make capacitors, etc. (See Non-Patent Document 1, for example.) O

[0006] In addition, regarding a TFT (Thin Film Transistor), a technique is disclosed in which an insulating layer or a protective insulating layer is formed by applying a fluid material and heat-treating (for example, see Patent Document 1).

Furthermore, using an ink jet method, a technique for forming a TFT all organic as the material has also been shown to open (e.g., non-patent document 2 reference.) ₀

A thin film formed of a coating film obtained by heat-treating at least one thin film of a thin film laminated structure constituting a thin film device such as a TFT after a liquid containing a thin film component is applied. Devices have been disclosed (for example, see Patent Document 2). ₀ According to these ink jet technologies, photolithography is not used to form a thin film in a thin film device, so that the number of times of photolithography can be reduced. However, there was room for improvement in that the shape of the formed film and variations in device characteristics were likely to increase.

[0007] On the other hand, in the ink jet method, a method of pre-treating a substrate in advance before dropping a droplet has been considered. This is performed for the purpose of relaxing the positional accuracy (landing accuracy) when the dropped droplet reaches the substrate, or for increasing the processing speed by reducing the number of required droplets. . In this technology, an affinity region and a non-affinity region for the wiring forming material are formed on the substrate on which the wiring is to be formed, and the wiring is formed by dropping a droplet of the wiring material into the affinity region by an inkjet method ( For example, see Patent Document 3.) _{0 An} exposure apparatus and a photomask are used to form this affinity region and non-affinity region.

[0008] Apart from this, similarly, in the wiring formation technology by the ink jet method, in order to suppress the protrusion of wiring material that is strong in the wiring formation region, a bank is formed so as to surround the wiring formation region, and the upper portion of this bank is formed. Disclosure of non-lyophilic and lyophilic wiring formation area (See, for example, Patent Document 4.) ₀ An exposure apparatus and a photomask are also used to produce this bank.

[0009] When the ink jet method is used in this way, a special manufacturing method is required to obtain the same characteristics as a film formed by a vacuum film forming apparatus such as a conventional sputtering method or a CVD method. Become. Therefore, at present, the conventional method has not been replaced.

[0010] As described above, in the manufacture of semiconductor elements on a substrate, photolithography is often used particularly when a fine pattern requires high accuracy. As a circuit board that frequently uses this photolithography, for example, there is a TFT array substrate. The TFT array substrate includes TFTs as source wiring, gate wiring, and switching elements connected to these on the substrate, and is suitably used for, for example, a liquid crystal display device. This TFT array substrate is manufactured, for example, by a series of processes as shown in Non-Patent Document 3, and in many cases, the manufacture of a TFT array substrate requires five or more times of photolithography. It was.

[0011] A general disadvantage of using photolithography is that a resist material having photosensitivity is applied to the entire surface of the substrate, so that a large amount of resist material, a developer for developing, and a stripping solution for removing the resist are used. Examples include the use of chemicals and the need for highly accurate equipment such as resist coating equipment and exposure equipment. For this reason, when conventional general photolithography is used, the environmental burden may be large, the material cost may be high, and a large amount of capital investment may be required. Therefore, reducing the number of photolithography operations in manufacturing circuit boards and devices has been an important issue. Above all,

In the manufacture of TFT array substrates, the reduction of the number of times of photolithography was an important issue because a multilayer thin film was formed on a large substrate.

Patent Document 1: Pamphlet of International Publication No. 97Z43689

Patent Document 2: Japanese Unexamined Patent Application Publication No. 2004-145333

Patent Document 3: Japanese Patent Laid-Open No. 11-204529

Patent Document 4: Japanese Unexamined Patent Publication No. 2000-353594

Non-Patent Document 1: Nikkei Electronics, June 17, 2002, Nikkei Business Publications, June 17, 2002, No. 824, p. 67-78 Non-Patent Document 2: Takeo Kawase et al., “Invited Paper: All-Polymer Thin Film Transistors Fabricated by High—Resolution Ink—jet PrintingJ, SID 01 DI GEST, (USA), Society for Information Display, 2001, No. 32 , 1st edition, p. 40-43

Non-Patent Document 3: Nikkei Microdevices, “Flat Panel Display 1999”, Nikkei BP, 1998, p. 129

Disclosure of the invention

Problems to be solved by the invention

[0012] The present invention has been made in view of the above-described present situation, and can selectively form a film and can reduce the number of times of photolithography necessary for forming an element structure. It is an object of the present invention to provide a method for manufacturing a substrate, and a semiconductor element, a circuit substrate, and an electronic device obtained by using them.

Means for solving the problem

[0013] The present inventors have studied various methods for manufacturing a semiconductor device having a channel. As a result, the groove portion (channel groove) on the channel region or below the channel region formed in the element formation process by channel etching or the like is formed. We focused on effective use. Then, as shown in FIG. 1, by dropping a functional material having fluidity into the channel groove, the functional layer can be selectively and highly accurately formed even by coating formation. We have found that it is possible to reduce the number of photolithography required for formation. As a result, the inventors have conceived that the above problems can be solved brilliantly and have reached the present invention.

That is, the present invention is a method of manufacturing a semiconductor device having a channel, and the manufacturing method includes a step of forming a functional layer by dropping a functional material having fluidity into a channel groove. It is a manufacturing method of an element.

[0015] A semiconductor element manufactured according to the present invention has a channel. Usually, the semiconductor element includes a structure in which a source electrode and a drain electrode are opposed to each other, and the channel is formed of a source electrode and a drain in a semiconductor layer positioned below or above the source electrode and the drain electrode. It is formed in a region corresponding to the electrode. In addition, the above The channel groove refers to a groove formed between a source electrode and a drain electrode facing each other when the source electrode and the drain electrode are formed separately in the manufacturing process of the semiconductor element.

According to the method for manufacturing a semiconductor element of the present invention, when the functional material having fluidity is dropped, the channel groove functions as a groove portion of the bank pattern that controls the shape of the droplet. Variations in characteristics of semiconductor elements due to variations can be suppressed. In addition, since the functional layer is formed by selectively dropping a functional material having fluidity into the channel groove on the substrate, the functional layer is formed on the entire surface of the substrate and then patterned. It is possible to reduce photolithography once. As a result, loss of the functional material can be reduced and damage to the base film during patterning can be eliminated. Furthermore, since an exposure process and a development process are not required, a photomask, an exposure apparatus, and a developer can be reduced. Therefore, it is possible to manufacture (process) semiconductor elements with reduced environmental impact, material costs, and capital investment costs. In this specification, the functional material having fluidity is not particularly limited as long as it can form a functional layer by drying or heat treatment after dropping, and can be applied by an inkjet apparatus. It is preferable that it is a thing.

[0017] A preferred embodiment of the method for manufacturing a semiconductor device of the present invention will be described below.

A preferable form of the functional material is an insulating material, and a protective layer (insulating layer) can be formed as the functional layer. Note that in this specification, the fluid insulating material is not particularly limited as long as a protective layer (insulating layer) can be formed by drying or heat treatment after dropping. . The protective layer is preferably impermeable to moisture. In the case of forming the protective layer, preferred embodiments of the method for manufacturing a semiconductor element of the present invention include (1) sequentially forming a gate electrode, a gate insulating film, a semiconductor layer, and a source electrode and a drain electrode on a substrate. And a step of forming a protective layer by dropping a fluid insulating material into a channel groove formed by at least the source electrode and the drain electrode, (2) a gate electrode, a gate insulating film, A semiconductor film, a source electrode and a drain electrode are sequentially formed on the substrate, and a fluid insulating material is dropped and maintained in at least a channel groove formed by the source electrode and the drain electrode. An embodiment includes a step of forming a protective layer and a step of patterning a semiconductor film using the protective layer to form a semiconductor layer. According to these, in a semiconductor element such as an inverted staggered type (bottom gate type) thin film transistor, a protective layer (insulating layer) can be selectively formed by a simple method, and the channel portion of the semiconductor element is protected. be able to. The protective layer may be formed of a material that can also serve as a light shielding layer.

[0018] In the above aspect (1), the patterning of the semiconductor film is performed before the step of forming the protective layer. On the other hand, in the above aspect (2), patterning of the semiconductor film is performed after the step of forming the protective layer.

In the above aspect (1), the semiconductor layer includes a lower semiconductor layer and a pair of upper semiconductor layers, and the channel groove is formed by a pair of upper semiconductor layers, a source electrode, and a drain electrode. It can be a thing.

Further, in the above aspect (2), the semiconductor film includes a lower semiconductor film and a pair of upper semiconductor layers, and the channel groove is formed by a pair of upper semiconductor layers, a source electrode, and a drain electrode. The lower semiconductor film may be patterned using the protective layer to form the lower semiconductor layer. In this case, the patterning of the upper semiconductor film is performed before the protective layer forming step, and the patterning of the lower semiconductor film is performed after the protective layer forming step.

[0019] As a form of the channel groove formed using the source electrode and the drain electrode, for example, a form formed between the source electrode and the drain electrode, a stacked film of the source electrode and the photoresist, Form formed between the drain electrode and the laminated film of the photoresist, formed between the laminated film of the source side upper semiconductor layer and the source electrode, and the laminated film of the drain side upper layer semiconductor layer and the drain electrode. And a form formed between the laminated film of the source side upper semiconductor layer, the source electrode and the photoresist, and the laminated film of the drain side upper layer semiconductor layer, the drain electrode and the photoresist. That is, the photoresist used as a mask in channel etching may be left when the functional material having fluidity is dropped or may be removed. In the case of remaining, the photoresist is preferably a resist having liquid repellency (liquid repellent resist) with respect to the functional material having fluidity from the viewpoint of increasing the dropping accuracy of the functional material having fluidity. Photo If the resist is left as part of the channel groove, the functional layer may also protrude the channel groove force after the photoresist is removed.

[0020] The functional layer (protective layer) made of the insulating material may be further formed on the wiring. In this case, the wiring can be protected by corrosion or the like by a functional layer made of an insulating material.

[0021] A preferable form of the functional material is a semiconductor material, and a semiconductor layer can be formed as the functional layer. Note that in this specification, the semiconductor material having fluidity is not particularly limited as long as a semiconductor layer can be formed by drying or heat treatment after dropping. In this case, as a preferred embodiment of the method for manufacturing a semiconductor element of the present invention, a gate electrode, a gate insulating film, a source electrode and a drain electrode are sequentially formed on the substrate, and the source electrode and the drain electrode are formed. And a step of dropping a fluid semiconductor material into a channel groove to form a semiconductor layer. According to this, the semiconductor layer of the semiconductor element can be selectively formed by a simple method.

[0022] As the form of the channel groove formed by the source electrode and the drain electrode, for example, a form formed between the source electrode and the drain electrode, a laminated film of the source electrode and the photoresist, and the drain electrode And a form formed between the laminated film of the photoresist and the like. In the case where the photoresist remains as a part of the channel groove, the photoresist resists a liquid repellent resist (repellent repellent) with respect to the fluid functional material from the viewpoint of improving the dropping accuracy of the fluid functional material. (Liquid resist) is preferred.

Furthermore, a preferred form of the functional material is a light shielding material, and a light shielding layer can be formed as the functional layer. In the present specification, the light-shielding material having fluidity is not particularly limited as long as it can form a light-shielding layer by performing drying or heat treatment after dropping. In this case, a preferred embodiment of the method for manufacturing a semiconductor device of the present invention is that the source electrode and the drain electrode are sequentially formed on the substrate, and at least in the channel groove formed by the source electrode and the drain electrode. An aspect including a step of forming a light shielding layer by dropping a light shielding material having fluidity, and a step of sequentially forming a semiconductor layer, a gate insulating layer, and a gate electrode on the light shielding layer, a source electrode and a drain electrode, and Sequentially forming a pair of lower semiconductor layers on a substrate; Forming a light shielding layer by dropping a light shielding material having fluidity in a channel groove formed by the lower semiconductor layer, the source electrode, and the drain electrode, and an upper semiconductor layer on the lower semiconductor layer and the light shielding layer. And a step of sequentially forming a layer, a gate insulating layer, and a gate electrode. According to these, in a semiconductor element such as a positive stagger type (top gate type) thin film transistor, the light shielding layer of the semiconductor element can be selectively formed by a simple method.

[0024] As the form of the channel groove formed using the source electrode and the drain electrode, for example, a form formed between the source electrode and the drain electrode, a stacked film of the source electrode and the photoresist, Form formed between the drain electrode and the laminated film of the photoresist, formed between the laminated film of the source electrode and the source-side lower semiconductor layer, and the laminated film of the drain electrode and the drain-side lower semiconductor layer Examples include a form formed between a stacked film of a form, a source electrode, a source-side lower semiconductor layer and a photoresist, and a stacked film of a drain electrode, a drain-side lower semiconductor layer, and a photoresist. In the case where the photoresist is left as part of the channel groove, the photoresist is a resist having liquid repellency to the resist material having fluidity (liquid repellent) from the viewpoint of increasing the dropping accuracy of the functional material having fluidity. Preferred to be a sex resist).

[0025] The functional material may be any one of an insulating material, a semiconductor material, and a light shielding material, and these materials may be mixed. Moreover, the insulating material may have two or more functions as in the case where the insulating material also serves as a light shielding material.

[0026] The method for producing a semiconductor device of the present invention preferably includes a step of bonding fluorine atoms and Z or a fluorine compound to the substrate surface before dropping the functional material having fluidity. That is, in the present invention, since the functional layer is formed by selectively dropping a functional material having fluidity, the surface treatment is performed on the substrate before dropping, so that at least the channel groove is formed on the substrate surface. It is preferable to adjust the lyophobic property with respect to the functional material having fluidity. As a result, it is possible to prevent the functional material having fluidity from being excessively spread on the surface of the substrate, and to effectively reduce the shape variation of the functional layer. Especially, it is preferable that the manufacturing method of the semiconductor element of this invention includes the surface treatment process using plasma, before dripping the functional material which has fluidity | liquidity. Especially on The surface treatment step is preferably performed in a plasma containing a fluorine-based gas. Thereby, it is possible to form a surface state having good liquid repellency. The fluorine-based gas is not particularly limited as long as the gas is a compound containing a fluorine atom, and examples thereof include carbon tetrafluoride. In addition, as a method for adjusting the lyophobic property of the surface, it is also possible to use a method in which a material having liquid repellency is applied and dispersed.

[0027] The method for producing a semiconductor element of the present invention preferably includes a dry etching step before dropping the functional material having fluidity. In the present invention, it may be possible to continue the surface treatment of the substrate in the same vacuum chamber where dry etching is performed. In such a case, the dry etching process and the surface treatment process for the purpose of patterning can be continuously performed, which is efficient.

[0028] It is preferable that the functional material having fluidity is applied using a coating apparatus having a multi-nozzle type ejection head and a substrate stage. In other words, when a large number of functional layers are formed on a substrate, it is advantageous to use a multi-nozzle type ejection head having a large number of nozzles as a functional material ejection mechanism because this leads to a reduction in processing time per substrate. is there. The substrate stage is not particularly limited as long as the substrate can be mounted. It is preferable that the substrate can be held horizontally, and it is preferable that the substrate stage has a mechanism for moving and Z or rotating the substrate.

[0029] The coating device is preferably an inkjet device, but more preferably a piezo method or a bubble method (thermal method). Inkjet devices are widely used especially for printers, and since they have accumulated technology, they can drop a small amount of several pi units, and they have fluidity for channel grooves of several / zm to several tens / zm units. It is suitable for selectively producing a functional layer by selectively dropping a functional material having

In this case, the functional material having the above fluidity has an ethylene glycol, diethylene glycol, triethylene glycol, polyethylene glycol, propylene glycol, dipropylene glycol having a boiling point of 180 ° C or higher at 1 atm. It is preferable to contain at least one ether, ester, diester and Z or ether ester selected from the group consisting of tripropylene glycols, polypropylene glycols, and butylene glycols, or hydrocarbons. Above all, at 1 atm mentioned above Examples of ethers, esters, diesters, ether esters or hydrocarbons having a boiling point of 180 ° C. or higher include tetralin (tetrahydronaphthalene), ethylene glycol, ethylene glycol diacetate, ethylene glycol jetinoleate, Ethylene glycol monobutyl etherate, ethylene glycol monoacetate, ethylene glycol monoethyl etherate acetate, ethylene glycol monobutinoate etherate, ethylene glycol monohexyl ether, 1, 3 —Otatiendalicol, glyceryl triacetate, diethylene glycol, diethylene glycol ethyl methyl ether, polyethylene glycol chlorohydrin, diethylene glycol jetino ether, diethylene glycol -Resin chinoleatenore, diethyleneglycolenomonochinenoatenoate, diethyleneglycolenomonochinenoatenoateate, diethyleneglycolenomonobutinorecatenoate , Diethylene glycol monomethenoate ether, dipropylene glycol, dipropylene glycol monoethyl ether, dipropylene glycol monobutyl ether, dipropylene glycol monomonopropynol ether, dipropylene glycol monomonomethyl ether, tetraethylene daritolol , Triethylene glycol, triethylene glycol di 2-ethyl butyrate, triethylene glycol dimethylol ether, triethylene glycol monomethenoate , Triethyleneglycol monomethinole ether, triglycol dichloride, tripropylene glycol, tripropylene glycolenomonomethylenoether, tripropylene glycolenomonoethylenoether, tripropylene glycol monobutyl ether, trimethylene glycol, 1 3,3-butanediol, propylene glycol, propylene glycol phenol ether, hexylene glycol, 1,5-pentanediol, and the like are preferably used. A functional material containing such a solvent is suitable for application by an ink jet apparatus because it is difficult to dry at around room temperature.

If a plurality of channel grooves are arranged in a matrix and the distance between the adjacent channel grooves in the left-right direction is smaller than the distance in the up-down direction, nozzle processing is easy and processing time is reduced. From the viewpoint, the inkjet head is preferably moved in the left-right direction.

In addition, the viscosity of the functional material having fluidity is preferably 5 cP or more and 30 cP or less. Yes. If it is in this viscosity range, it is suitable for application | coating with an inkjet apparatus, and dripping from an inkjet head can be stabilized. In addition, since the viscosity of the functional material having fluidity tends to increase as the contained solid content increases, it is preferable to adjust the solid content concentration to a desired viscosity.

Furthermore, the amount of dripping per discharge depends on the shape and size of the channel groove, but for example, when manufacturing TFTs in a TFT array substrate used for a display device, 0.5 pl or more, It is preferable that it is below lOpl.

[0031] The present invention is also a circuit board manufacturing method in which a semiconductor element is formed on a substrate using the semiconductor element manufacturing method of the present invention. Examples of the semiconductor element include a thin film transistor (TFT) and a thin film diode. The circuit board is not particularly limited as long as it has a circuit including a semiconductor element on the substrate, and examples thereof include a TFT array substrate. According to the circuit board manufacturing method of the present invention, it is possible to reduce the number of times of photolithography by one, and it is possible to reduce the environmental load, material cost, and capital investment cost in circuit board manufacturing.

In the method for manufacturing a circuit board according to the present invention, the circuit board constitutes a display device or an imaging device, and a semiconductor element in the display region or the imaging region and the non-display region or the non-imaging region is a gate. It is arranged on a group of parallel lines extending in the extending direction of the wiring and the Z or source wiring, and the functional layer forming step is performed in the display area or the imaging area and the non-display area or the non-imaging area. It is preferable to apply the functional material having fluidity by continuously moving the discharge head or the substrate stage in the stretching direction. Thus, using the semiconductor element manufacturing method of the present invention, the functional material is dropped by scanning the ejection head in the extending direction of the gate wiring and Z or the source wiring, thereby constituting the circuit board constituting the display device. In the manufacturing of the semiconductor device, the semiconductor element in the display region and the semiconductor element in the non-display region can be manufactured together. In the manufacture of the circuit board constituting the imaging device, the semiconductor element in the imaging region and the semiconductor in the non-imaging region Since the devices can be manufactured in a lump, the processing time can be shortened in addition to the reduction of environmental burden, material cost, and capital investment cost in circuit board manufacturing. The display area or imaging area is usually located at the center of the circuit board, for example, a switch for applying a voltage to the pixel electrode. A TFT for ching is arranged for each pixel. On the other hand, the non-display area or the non-imaging area is usually located in the peripheral portion (frame portion) of the circuit board. For example, TFTs provided in the display area, thin film diodes for preventing electrostatic breakdown of wiring, and driving circuits TFT for driver is arranged. The circuit board has a configuration in which semiconductor elements in a display region or an imaging region and a non-display region or a non-imaging region are arranged on a common parallel line group extending in the extending direction of the gate wiring and the Z or source wiring. In addition, a semiconductor element may be arranged on another parallel line group extending in the extending direction of the gate wiring and the Z or source wiring. In addition to the semiconductor elements arranged on the parallel lines extending in the extending direction of the gate wiring or the source wiring, semiconductor elements may be arranged on the circuit board.

In this case, it is preferable that the discharge head is continuously moved in the extending direction of the gate wiring. Many gate wirings and source wirings are arranged in a direction orthogonal to a circuit board such as a TFT array substrate. The spacing between adjacent gate wirings (gate wiring pitch) is equal to the spacing between adjacent source wirings (source wiring pitch). In many cases. For this reason, by sequentially applying functional materials in the extending direction of the gate wiring, it is possible to reduce the number of nozzle mechanisms provided in the discharge head. This leads to a decrease.

[0033] The present invention is also a semiconductor device manufactured using the method for manufacturing a semiconductor device of the present invention. According to the semiconductor device of the present invention, it is possible to manufacture by reducing the number of times of photolithography, and it is possible to reduce the environmental load, material cost, and capital investment cost in manufacturing the semiconductor device.

The present invention is also a semiconductor element having a channel, and the semiconductor element includes a semiconductor element having a functional layer having a curved shape at an end portion located between a source electrode and a drain electrode (hereinafter referred to as a semiconductor element) Also referred to as a first semiconductor element). The first semiconductor element of the present invention has characteristics when the functional layer of the channel portion is formed of a fluid material, and can be manufactured by the method for manufacturing a semiconductor element of the present invention. Can

. That is, a functional layer is formed in a channel portion by using a source electrode and a drain electrode for a bank and dropping a functional material having fluidity between the source electrode and the drain electrode. In such a case, the functional material dropped between the source electrode and the drain electrode has a curved shape due to its surface tension. Therefore, when the functional layer is formed in the channel portion using such a functional material, the end of the functional layer located between the source electrode and the drain electrode has a curved shape in the obtained semiconductor element. become. Examples of the curved shape of the end portion of the functional layer include an oval shape protruding in the end direction, an oval shape protruding in the direction opposite to the end portion, and the like. The first semiconductor element of the present invention is therefore

The device structure can be formed by reducing the number of times of photolithography, and the environmental load, material cost, and capital investment cost in the manufacture of semiconductor devices can be reduced.

[0035] The present invention is also a semiconductor device having a channel, wherein the source electrode and the Z or drain electrode have a notch at the end on the channel side (hereinafter also referred to as a second semiconductor device). Also). The second semiconductor element of the present invention has a structure that is advantageous when the functional layer of the channel portion is also formed with a fluid material force. That is, by having a notch at the end on the channel side of the source electrode and the Z or drain electrode force channel (facing the channel), it is possible to provide a liquid reservoir in the channel groove and increase its volume. As a result, the fluid material dropped into the channel groove can be easily retained in the groove, and the functional film can be formed with high accuracy. Such a second semiconductor element of the present invention is preferably manufactured by the method for manufacturing a semiconductor element of the present invention. The notch is not particularly limited as long as the channel groove or the resist groove can be enlarged. The shape of the notch is not particularly limited, and examples thereof include a triangular shape, a quadrangular shape, and a semicircular shape. The number of notches is not particularly limited, and may be one or plural for one semiconductor element.

The present invention is also a semiconductor element having a channel, and the semiconductor element is also a semiconductor element having a dummy channel in the vicinity of the channel (hereinafter also referred to as a third semiconductor element). The third semiconductor element of the present invention has a structure advantageous when the functional layer of the channel portion is also formed with a fluid material force. That is, when the semiconductor element has a dummy channel in the vicinity of the channel, a liquid reservoir can be provided in the vicinity of the channel groove. As a result, the fluid material dripped into the channel groove can be easily retained in the groove by holding it in the liquid reservoir, and the functional film can be accurately formed. . Such a third semiconductor element of the present invention is preferably manufactured by the method for manufacturing a semiconductor element of the present invention.

[0037] The dummy channel is not particularly limited as long as it is a region provided on the semiconductor layer by a cutout portion of the source electrode and the Z or drain electrode and can function as a liquid reservoir. From the viewpoint of more effectively functioning as a liquid reservoir, it is more preferable that the channel is provided at a position within 20 μm from the channel force. The shape of the dummy channel is not particularly limited. The number of dummy channels is not particularly limited, and may be one or more than one semiconductor element.

The present invention is also a semiconductor element having a channel, and the semiconductor element is also a semiconductor element having a dummy electrode between a source electrode and a drain electrode (hereinafter also referred to as a fourth semiconductor element). is there. The fourth semiconductor element of the present invention has a structure that is advantageous when the functional layer of the channel portion is formed from a fluid material. In other words, if the channel width of the channel groove is too large relative to the size of the droplet at the time of landing of the fluid material that drops into the groove, the gap between the source electrode and the drain electrode is reduced. By providing a dummy electrode in the channel, the channel groove can be divided into a plurality of parts, and the fluid material dropped into the groove can be divided and held. As a result, the fluid material dropped into the groove can be easily retained in the groove, and the functional film can be formed with high accuracy. Such a fourth semiconductor element of the present invention is preferably manufactured by the method for manufacturing a semiconductor element of the present invention.

[0039] The dummy electrode is effective in controlling the shape of a droplet dropped between the source electrode and the drain electrode, and is a structure provided independently of the other electrodes. Although there is no particular limitation as long as it is used, it is more preferable that it is provided at a position within 20 μm from the source electrode and the drain electrode from the viewpoint of more effective use for liquid storage. The material of the dummy electrode is not particularly limited, but is preferably the same material as the source electrode and the drain electrode. In this case, it can be manufactured in the same process as the formation of the source electrode and the drain electrode. The shape of the dummy electrode is not particularly limited. The number of dummy electrodes is not particularly limited, and may be one or more per semiconductor element. [0040] Preferred forms of the second to fourth semiconductor elements of the present invention include, for example, a mode in which the channel has a protruding portion on the source electrode side and the Z or drain electrode side, and a channel on the outer side. The source electrode and the Z or drain electrode force have a comb tooth portion (notch portion) of 2 or more, and a dummy channel is formed between the comb tooth portions, the source electrode and the Z or drain electrode are notched. And a structure in which a dummy channel is formed between the divided electrodes, and the semiconductor element has a dummy electrode, between the source Z dummy electrode, between the drain Z dummy electrode, and Z or dummy Z A dummy channel is formed between dummy electrodes. In particular, a shape in which the line width of the notch is equal to the channel length of the semiconductor element (TFT) is preferably used.

The present invention is also a semiconductor element having a channel, wherein the channel of the semiconductor element is a semiconductor element bent to 2 or more (hereinafter also referred to as a fifth semiconductor element). The fifth semiconductor element of the present invention has a structure that is advantageous when the functional layer of the channel portion is formed into a fluid material force. That is, even if the length of the entire channel is the same, the channel of the semiconductor element is bent to 2 or more, so that the entire channel can be put in a smaller circle, so that the functional layer can be easily formed. . In addition, it is possible to increase the channel area ratio in the portion of the semiconductor layer that constitutes the semiconductor element, and to increase the volume of the channel groove. As a result, the fluid material dropped into the channel groove can be easily retained in the groove, and the functional film can be formed with high accuracy. Such a fifth semiconductor element of the present invention is preferably manufactured by the method for manufacturing a semiconductor element of the present invention. The bent part of the channel may be a right angle or a curved shape.

As a more preferable form of the fifth semiconductor element of the present invention, for example, a form in which the channel has a U-shape, a form having a U-shape, a form having a Z-shape, and the like can be mentioned. Especially, it is preferable that a channel has U shape or U shape.

The present invention is also a semiconductor element having a channel, wherein the source electrode and the drain electrode have a corner on both sides of the end of the channel (hereinafter also referred to as a sixth semiconductor element). But there is. The sixth semiconductor element of the present invention has a structure that is advantageous when the functional layer of the channel portion is formed from a fluid material. Channel groove Edge force When formed in a portion where the corner of the source electrode and the corner of the drain electrode face each other, the material having fluidity is channeled along the bank portions located on both sides of the channel groove. It is possible to suppress spreading out of the groove. As a result, the fluid material dropped into the channel groove can be easily retained in the groove, and the functional film can be formed with high accuracy. That is, a form having corners on both sides of the end part of the source electrode and drain electrode force channel (a form in which the end part of the channel is located at a part where the corner part of the source electrode and the corner part of the drain electrode face each other) In the case of manufacturing a semiconductor element having a functional film, the functional film can be formed with high accuracy by the method for manufacturing a semiconductor element of the present invention. Thus, the sixth semiconductor element of the present invention is preferably manufactured by the method for manufacturing a semiconductor element of the present invention.

[0044] In the sixth semiconductor element of the present invention, the outline shape of the corners of the source electrode and the drain electrode may be formed by curves, but is formed by two straight lines. It is more preferable that The angle of the corners of the source electrode and the drain electrode is preferably 135 ° or less, more preferably 90 ° or less, and even more preferably 90 °.

In the case where a dummy channel is provided, the source electrode and the drain electrode preferably have corner portions on both sides of the end portion of the dummy channel.

[0045] The semiconductor element of the present invention may be any element as long as it has any of the first to sixth semiconductor elements, and may be a combination of these! /.

The dimension of the channel groove is determined so as to have a predetermined performance mainly in the form of use as a product, but is determined in consideration of the amount of droplets of the functional material to be applied and other manufacturing conditions to be set. As an example, for TFTs in TFT array substrates used for display devices, the channel groove dimensions are 5 μm or more and 100 μm or less in length, 1 μm or more and 10 m or less in width, and depth. Is preferably 0.01 μm or more and 10 μm or less. Here, the length of the channel groove means the length in the extending direction of the channel groove, and the width of the channel groove corresponds to the distance between the source electrode and the drain electrode. The number of channel grooves may be one per semiconductor element or plural.

[0046] Further, when manufacturing the semiconductor element of the present invention, a material having fluidity from the inside of the channel groove If there is a risk of overflowing, it is preferable to take measures to define the direction of overflowing. Specific examples include a method of controlling the electrode shape of the source electrode and the drain electrode, the dropping conditions of the fluid material, and the like. For example, in the case of a TFT in a TFT array substrate used in a liquid crystal display device, if the capacitance (Cg-d) between the gate electrode Z and the drain electrode varies, the capacitance (Cg-s) between the gate electrode Z and the source electrode varies. This will have a greater effect on the display quality than when it occurs. Therefore, it is more preferable that the material having fluidity easily overflows to the source electrode side.

[0047] The semiconductor element of the present invention is preferably a thin film transistor (TFT) or a thin film diode (TFD). In the present invention, the TFD is usually formed by electrically connecting a gate electrode and a source electrode, or a gate electrode and a drain electrode.

[0048] The present invention also provides a semiconductor element manufactured using the method for manufacturing a semiconductor element of the present invention, or a circuit board having the first to sixth semiconductor elements of the present invention (hereinafter referred to as the first circuit board). It is also called). Such a first circuit board of the present invention can reduce the environmental load, the material cost and the capital investment cost in the manufacturing process.

The present invention is also a circuit board having a gate wiring, a source wiring, and a semiconductor element on a substrate, and the circuit board constitutes a display device or an imaging device, and the display region or the imaging region Including a configuration in which the semiconductor element is arranged on a group of parallel lines extending in the extending direction of the gate wiring and the Z or source wiring, and the semiconductor element in the non-display area or the non-imaging area is arranged on the parallel line group. It is also a circuit board (hereinafter also referred to as a second circuit board) including the above-described configuration. In such a second circuit board of the present invention, the functional material is dropped by scanning the ejection head in the extending direction of the gate wiring and Z or the source wiring by using the semiconductor element manufacturing method of the present invention. Therefore, in the manufacture of the circuit board constituting the display device, the semiconductor elements in the display region and the semiconductor element in the non-display region can be manufactured at once. Since semiconductor elements and non-imaging area semiconductor elements can be manufactured together, the processing time can be shortened in addition to reducing the environmental burden, material costs, and capital investment costs in circuit board manufacturing. is there. The circuit board has a common parallel extension extending in the extending direction of the gate wiring and Z or source wiring in the display area or imaging area and non-display area or non-imaging area. The semiconductor device may have a configuration in which the semiconductor element is arranged on another group of parallel lines extending in the extending direction of the gate wiring and the z or source wiring. In addition to the semiconductor elements arranged on the parallel lines extending in the extending direction of the gate wiring or the source wiring, semiconductor elements may be arranged on the circuit board. A preferable form of the circuit board includes, for example, an active matrix substrate in which semiconductor elements as active elements are arranged in a matrix in a display area or an imaging area.

The present invention is also a circuit board having a gate wiring, a source wiring, and a semiconductor element on a substrate, and the circuit board constitutes a display device or an imaging device. The semiconductor element includes a configuration in which the semiconductor element is arranged on a parallel line group (also referred to as a first parallel line group) extending in the extending direction of the gate wiring and the Z or source wiring, and the non-display area or the non-imaging area A circuit board (hereinafter referred to as a third circuit) including a configuration in which a semiconductor element is arranged on a straight line group (also referred to as a ^second parallel line group) determined by a distance of an integer of the interval between the parallel line groups. Also called a substrate). Even with such a third circuit board of the present invention, similarly to the second circuit board of the present invention, the discharge head is formed of the gate wiring and the Z or source wiring by using the semiconductor element manufacturing method of the present invention. By performing functional material dropping by scanning in the stretching direction, semiconductor elements in the display area and semiconductor elements in the non-display area can be manufactured together in the manufacture of the circuit board constituting the display device. In the manufacture of the circuit board that constitutes the imaging device, the semiconductor elements in the imaging region and the semiconductor elements in the non-imaging region can be manufactured together. In addition to reducing investment costs, processing time can be shortened. In addition to the semiconductor elements arranged on the parallel lines extending in the extending direction of the gate wiring or the source wiring, semiconductor elements may be arranged on the circuit board.

A preferable form of the circuit board includes, for example, an active matrix substrate in which semiconductor elements as active elements are arranged in a matrix in a display area or an imaging area.

[0051] The second and third circuit boards of the present invention preferably include a configuration in which the semiconductor elements in the display region or the imaging region are arranged on a group of parallel lines extending in the extending direction of the gate wiring. As a result, when the semiconductor element manufacturing method of the present invention is used, the functional material can be dropped by scanning the ejection head in the extending direction of the gate wiring. A large number of gate wirings and source wirings are arranged in a direction orthogonal to a circuit board such as a TFT array substrate. The spacing between adjacent gate wirings (gate wiring pitch) is the spacing between adjacent source wirings (source wiring). In many cases, it is wider than the wiring pitch. For this reason, by sequentially applying functional materials in the gate wiring direction, the number of nozzle mechanisms provided in the ejection head can be reduced, which makes it easier to produce the ejection head and reduce equipment costs. Connected.

[0052] In the second and third circuit boards of the present invention, a plurality of semiconductor elements arranged in the display region or imaging region are arranged at each intersection of the gate wiring and the source wiring, and are arranged at the intersection. The plurality of semiconductor elements preferably include a configuration in which the plurality of semiconductor elements are arranged on one parallel line group extending in the extending direction of the gate wiring or the source wiring. Thus, even when a plurality of semiconductor elements are provided in one pixel, the semiconductor elements on the circuit board can be efficiently manufactured.

[0053] In the second and third circuit boards of the present invention, the semiconductor element arranged in the display area or the imaging area is preferably a thin film transistor. The thin film transistor is suitable for manufacturing using the method for manufacturing a semiconductor element of the present invention. In addition, it is possible to obtain excellent display quality or imaging quality by switching the voltage applied to the electrodes provided in the display area or imaging area using a thin film transistor.

The semiconductor element disposed in the non-display area or non-imaging area is preferably a thin film diode. The thin film diode is suitable for manufacturing using the method for manufacturing a semiconductor device of the present invention. In addition, by disposing a thin film diode in the non-display area, electrostatic breakdown in a switching element such as a thin film transistor provided in the display area can be prevented, and an excellent display quality or imaging quality can be obtained. .

The present invention is also a circuit board manufactured using the circuit board manufacturing method of the present invention, or an electronic device comprising the circuit board of the present invention. Such an electronic device of the present invention can reduce the environmental load, material cost, and capital investment cost in the manufacturing process. In addition, an imaging device, a display device, an image input device, and the like are preferable as the electronic device of the present invention. Examples of the imaging device include a flat panel X-ray image sensor device. In addition The flat panel X-ray image sensor device has, for example, a structure in which an TFT array substrate is provided with an X-ray light receiving layer and a signal readout circuit, and is used for medical applications, fluoroscopic inspection applications, and the like. is there. Further, as the display device, a liquid crystal display device, an organic electroluminescence display device, or the like is suitable.

The invention's effect

[0055] According to the method for manufacturing a semiconductor element of the present invention, a functional layer can be selectively and accurately formed by dropping a functional material having fluidity into a channel groove. The number of times of photolithography necessary for forming the substrate can be reduced, and the method is suitably used for manufacturing a semiconductor element formed on a circuit board or the like.

BEST MODE FOR CARRYING OUT THE INVENTION

[0056] Hereinafter, the present invention will be described in more detail with reference to examples, but the present invention is not limited to these examples.

[Example 1]

As an embodiment of the present invention, a method of manufacturing an inverted staggered amorphous silicon TFT (thin film transistor) according to Embodiment 1 will be described with reference to FIGS.

The characteristic of this embodiment is the protective film formation process. After obtaining the source electrode and drain electrode, the source Z drain pattern is used to protect the TFT gap and wiring parts from corrosion. Only by using an inkjet device, a droplet of insulating material is selectively landed to form a TFT protective film.

[0058] FIG. 1 (a) is a schematic plan view showing the structure of a TFT fabricated using the manufacturing method of the present embodiment and its vicinity, and (b) is an AA line in (a). FIG.

As shown in FIGS. 1A and 1B, the TFT 7 manufactured in this example has a bottom gate structure, and a gate electrode 10 branched from a gate wiring 9 on a glass substrate (insulating substrate) 8. A gate insulating film 11, an amorphous silicon layer 12, an n + type amorphous silicon layer 13, a source wire 14 branched from a source electrode 15, and a drain electrode 17 connected to a drain connection wire 16. Have a configuration in which the layers are stacked. The drain connection wiring 16 is formed for the purpose of, for example, connecting a pixel electrode (not shown) and the drain electrode 17 in a display application. Here, a portion of the amorphous silicon layer 12 positioned between the source electrode 15 and the drain electrode 17 is the TFT channel portion 18, and a protective film (functional film) 35 is formed.

In manufacturing the TFT 7 of this example, an ink jet apparatus was used as a pattern forming apparatus capable of selectively ejecting or dropping a fluid material as droplets on a substrate surface. As shown in FIG. 2, the ink jet apparatus includes a mounting table (substrate stage) 20 on which a substrate 19 (corresponding to the glass substrate 8 in FIG. 1) is mounted. An inkjet head 21 as a droplet ejection means for ejecting or dropping a fluid material as droplets, an X-direction drive unit 22 for moving the inkjet head 21 in the X direction, and a Y-direction drive unit 23 for moving in the Y direction. Is provided.

In addition, the ink jet apparatus includes an ink supply system 24 that supplies a fluid material to the ink jet head 21, ejection control of the ink jet head 21, and drive control of the X direction driving unit 22 and the vertical direction driving unit 23. And a control unit 25 for performing various controls. From the control unit 25, ejection position information is output to the X direction driving unit 22 and the Y direction driving unit 23, and ejection information is output to a head driver (not shown) of the inkjet head 21. As a result, the inkjet head 21 operates in conjunction with the X-direction drive unit 22 and the Y-direction drive unit 23, and a target amount of droplets is dropped at a target position on the substrate 19.

[0061] As the inkjet head 21, a piezo type using a piezoelectric actuator, a bubble type having a heater in the head, or the like can be used. Control of the droplet discharge amount from the inkjet head 21 is performed by controlling applied voltage or the like.

Note that the droplet discharge method of the pattern forming apparatus used in the present invention is not limited to the ink jet method, and may be any method that can discharge or drop a fluid material as droplets.

In this embodiment, the gate electrode Z wiring forming step, the gate insulating film Z lower layer semiconductor film Z, the upper layer semiconductor film forming step, the lower layer and upper layer semiconductor film patterning step, and the source z drain electrode After the z wiring formation process and the channel etching process are sequentially performed, the protective film formation process is performed.

Hereinafter, the manufacturing method of the TFT 7 of this embodiment will be described in detail for each process.

[Gate electrode Z wiring formation process] In this step, the gate electrode 10 and the like are formed on the glass substrate 8.

In this step, a titanium (Ti) film having a thickness of 0.2 m was formed on the glass substrate 8 by sputtering at a film forming temperature of 100 ° C. to obtain a gate metal film made of titanium. Subsequently, a resist pattern film is formed on the gate metal film using a resist material, and patterning is performed using the resist pattern film as a mask, that is, gate wiring 9 by photolithography. Thus, a gate electrode 10 and the like were obtained. A dry etching method was used as the gate metal film etching method at this time. Etching gases include chlorine (C1) gas and three

2

A salty boron (BC1) gas or the like was used in combination. Subsequently, using organic solvent, etc.

Three

The photoresist film was peeled off.

In the present invention, the metal constituting the gate metal film is not particularly limited. For example, aluminum (A1), copper (Cu), chromium (Cr), tantalum (Ta), molybdenum (Mo), indium Metals or metal compounds such as mu tin oxide (ITO), titanium and molybdenum (Mo) can be used. The gate metal film may be formed as a single layer or may have a stacked structure. A method for forming the gate metal film is not particularly limited, and a vapor deposition method or the like can be used in addition to the sputtering method. The thickness of the gate metal film is not particularly limited. Further, the etching method of the gate metal film is not particularly limited, and a wet etching method or the like can be used.

[Gate Insulating Film Z Lower Semiconductor Film Z Upper Semiconductor Film Formation Process]

In this step, a gate insulating film 11, an amorphous silicon film (lower semiconductor film), and an n + type amorphous silicon film (upper semiconductor film) are formed on the glass substrate 8 that has undergone the gate electrode / wiring forming process. The gate insulating film 11 is made of silicon nitride (SiN). These films were continuously formed in the same vacuum chamber by a plasma chemical vapor deposition (CVD) method at a film forming temperature of 300 ° C. The thickness of each film was set to 0.4 / zm (gate insulating film 11), 0.2 / zm (amorphous silicon film) and 0.1 / ζ πι (η ⁺ type amorphous silicon film), respectively. However, in the present invention, the film forming method and film thickness of each film are not particularly limited.

[Lower layer and upper layer semiconductor film patterning step]

In this step, an amorphous silicon film and an η + type amorphous silicon film were formed into islands (island shapes) by performing a dry etching process using photolithography. For dry etching, carbon tetrafluoride (CF 3) gas and oxygen ( o) Used in combination with gas.

2

[Source Z Drain Electrode Z Wiring Formation Process and Channel Etching Process]

In this step, a source metal film was obtained by depositing titanium (Ti) with a film thickness of 0.2 m by the same film formation method as that for the gate metal film. The source metal film is later subjected to patterning to become the source electrode 15 and the drain electrode 17. Note that the source metal film is not particularly limited to the form of this embodiment as well as the gate metal film.

Subsequently, as one stage of photolithography, a resist pattern film was obtained on the source metal film using a photosensitive resist material. The film thickness of the resist pattern film was 2.

Then, using the resist pattern film as a mask, the source metal film and the n + type amorphous silicon film were successively etched to obtain the source electrode 15, the drain electrode 17, and the n + type amorphous silicon layer 13. Thereafter, the resist pattern film was peeled and removed.

In this step, the gap L between the source electrode 15 and the drain electrode 17 is set to the size of the gap formed between the source electrode 15 and the drain electrode 17 (also referred to as a TFT gap portion or a channel groove). L = 3 m, and the width W of the source electrode 15 and the drain electrode 17 was W = 60 μm.

In this process, a dry etching method is used as an etching method for the source metal film and the n + type amorphous silicon film, and a chlorine (C1) gas is used as an etching gas.

2 and boron trichloride (BC1) gas were used in combination. The above etching process

Three

The method is not particularly limited, and a wet etching method or the like may be used. In order to prevent a leakage current failure between the source electrode 15 and the drain electrode 17, the n + type amorphous silicon film in the TFT gap portion must be sufficiently removed by the etching process. Therefore, in this embodiment, an over-etching process may be performed to etch a part on the upper layer side of the amorphous silicon film, but this is not shown in FIG. 1 (b).

Further, after removing and removing the resist pattern film, the surface of the source electrode 15, the drain electrode 17, the gate insulating film 11, the amorphous silicon layer 12, and the like is lyophilic and lyophobic for the protective material used in the next step. The process which provides sex was performed. Here, the lyophobic property refers to the property of getting wet or repelling when the liquid comes into contact with the solid surface. In this example, four foot Surface treatment was performed by a plasma treatment method using carbon fluoride (CF 3) gas.

Four

[0070] After this surface treatment, lyophilicity was confirmed by measuring the contact angle of the surface. As a method for measuring the contact angle, a method of calculating the contact angle by approximating it as a part of a sphere, which is a commonly used method, was used. As a result, the contact angle of the source electrode 15 and the drain electrode 17 exposed on the substrate surface is 40 to 50 °, the contact angle of the gate insulating film 11 is 15 to 30 °, and the contact angle on the amorphous silicon layer 12 is 20 to 30 °. Met. On the other hand, when the surface treatment was not performed, each contact angle was 0 to 10 °. Thus, the surface treatment provided the lyophobic property to the surfaces of the source electrode 15, the drain electrode 17, the gate insulating film 11 and the amorphous silicon layer 12.

The contact angle of the end face of the n + type amorphous silicon layer 13 exposed on the TFT gap side is about 20 to 80 ° from the measurement result of the film surface of the same material processed under the same conditions as in this example. Presumed.

Further, the surface treatment method used in the present invention is not particularly limited to the method of this example, and any method may be used as long as the lyophobic property can be adjusted. The value of the contact angle is also just an example, and is not particularly limited in the present invention.

[Protective film forming step]

This process will be described with reference to FIGS.

As shown in FIG. 3, in this embodiment, the space between the opposing source electrode 15 and drain electrode 17 and the removed portion of the n + -type amorphous silicon layer 13 are used as channel grooves.

One drop of SOG (Spin on Glass) material droplet (insulating material having fluidity) 32 was ejected onto the glass substrate 8 that had undergone the channel etching process by the inkjet method with the aim of the vicinity of the center of the TFT gap portion 31. FIG. 3 (a) is a schematic plan view showing a state at the moment when a droplet has landed on the TFT gap portion 31, and FIG. 3 (b) is a schematic cross-sectional view taken along line FF in FIG. 3 (a). As the SOG material, a solution in which a metal alkoxide is dissolved in a diethylene glycol monobutyl ether solvent can be used. By baking after applying the SOG material, a film composed mainly of silicate glass (SiO 2) can be formed.

2

[0072] In this step, a liquid material droplet may be selectively discharged or dropped onto the substrate surface. Force Using a Pattern Forming Apparatus That Can Be Used As described above, an inkjet apparatus was used in this example. In addition, the volume of the droplets 32 discharged at this time was 1 to 2 pl.

As shown in FIG. 3 (a), the planar shape of the droplet 32 seems to be nearly circular at the moment of landing. However, this planar shape is affected by the shape of the droplet during the flight after the droplet 32 is ejected from the inkjet head 21 of the inkjet device, and it is therefore fully conceivable that the shape is other than this. As shown in FIG. 3 (b), after the droplets 32 land, the droplets 32 are applied to the surfaces and end surfaces of the source electrode 15 and the drain electrode 17, the end surface of the n + type amorphous silicon layer 13, and the surface of the amorphous silicon layer 12. Touch.

In this embodiment, an ink jet apparatus is used as the pattern forming apparatus. However, the present invention is not particularly limited. In addition, the number of droplets discharged to each TFT gap portion 31 is not necessarily one, and two or more droplets may be discharged. Further, the volume of the droplet is merely an example, and is not particularly limited in the present invention. However, the volume of the droplet needs to be set appropriately according to the size of the target pattern.

[0074] Fig. 4 (a) is a schematic plan view showing a state in which the droplet 32 shown in Fig. 3 (a) has landed and deformed due to its fluidity, and (b) shows ( It is a schematic sectional drawing in the GG line of a). The droplet 32 changed into a shape like the droplet 33 shown in FIG. 4 after landing. Specifically, the TFT gap portion 31 is widened to fill, and the TFT gap portion 31 has a shape having an interface near both ends 34. The shape of the droplet 33 is given by the bank pattern shape (bank pattern) that also includes the edge force of the source electrode 15, the drain electrode 17 and the n + type amorphous silicon layer 13, and the surface treatment in the previous step. It is controlled and realized by the lyophobic property.

[0075] The shape change after landing of the droplet will be described in detail. First, the droplet 32 immediately after landing has a contact angle of 90 ° or less at the contact portion of the source electrode 15, the drain electrode 17, the amorphous silicon layer 12, and the like. So they try to get wet on those surfaces. The direction of wetting and spreading at this time is controlled by the step formed by the stacked structure of the source electrode 15 and the drain electrode 17 constituting both sides of the TFT gap portion 31 and the n + type amorphous silicon layer 13. The bank. This bank limits the direction of wetting and spreading of the droplet, and the droplet spreads in the TFT gap 31. In this embodiment, the source electrode 15 and the drain Since the contact angular force on the electrode 17 is higher than that on the gate insulating film 11, the droplet preferentially enters the TFT gap 31.

[0076] In this way, the liquid droplet extends and spreads in the TFT gap portion 31! /, But when the surface tension of the liquid droplet and the force to spread the liquid are balanced, Stops moving. Here, the droplet tends to stay in the TFT gap portion 31 and in the vicinity thereof as much as possible due to the capillary phenomenon and the surface tension of the droplet. In this example, by appropriately setting the amount, viscosity and the like of the droplet, it was possible to obtain the droplet 33 that spreads to the vicinity of both ends 34 of the TFT gap portion 31.

As described above, the open portion at both ends 34 of the TFT gap portion, and the bank portion having a laminated structure of the source electrode 15, the drain electrode 17 and the n + -type amorphous silicon layer 13 constituting both sides of the TFT gap portion 31, The shape of the droplet can be controlled by using the bank pattern including the.

As will be described later, the shape of the droplet 33 in this embodiment is merely an example, and is not particularly limited in the present invention.

FIG. 5-1 (a) is a schematic plan view showing a state in which the protective film 35 is formed in the TFT gap portion 31, and (b) is a schematic cross section taken along the line H—H in (a). FIG.

The protective film 35 was formed by heat-treating the substrate at 300 ° C. to volatilize the organic solvent contained in the droplet 33 and to hydrolyze and polymerize the metal alkoxide. Due to the volume contraction at this time, the inside of the droplet 33 temporarily becomes a negative pressure, a part of the droplet 33 protruding from both ends 34 of the TFT gap 31 is absorbed, and the protective film 35 is formed as shown in FIG. It was formed by slightly changing the shape from the shape of the droplet 33 in (a). By this action, the shape of the protective film 35 in the TFT gap 31 can easily be made constant as shown in Fig. 5-1, by absorbing variations in conditions such as the contact angle.

In this example, the evaporation of the organic solvent and the hydrolysis / polymerization of the metal alkoxide in the droplet 33 were performed by heating the substrate at 300 ° C. for 30 minutes. However, in the present invention, the method for volatilization of the organic solvent and hydrolysis of the metal alkoxide is not particularly limited. In the present invention, the method for heating the substrate is not particularly limited.

In the present embodiment, as shown in FIG. 3B, an insulating material is deposited only on the TFT gap portion 31 using an inkjet device. As a result, CV for forming the protective film 35 is formed. The D process and the photoetching process for patterning are not required, and the number of photolithography can be reduced by one. Along with this, the amount of chemicals used in photolithography, such as resist materials, developing solutions, resist stripping solutions, etc., could be reduced. Strictly speaking, a fluid material such as an insulating material is also used in the ink jet method, but since the material is selectively ejected, the amount used is overwhelmingly small. Therefore, with regard to TFT manufacturing, material costs can be reduced, and the impact on the surrounding environment (environmental impact) associated with the use of chemicals can be reduced!

[0081] In addition, when manufacturing TFTs on a large scale, along with a reduction in the number of times of photolithography, a very expensive exposure apparatus such as a proximity exposure apparatus or a stepped exposure apparatus (stepper) is used. Since the required number is reduced, the capital investment cost of the entire production line can be reduced. In general, there are many conflicts between the reduction in capital investment costs and the reduction in material costs, such as the necessity of using expensive materials to reduce capital investment costs. According to the method, both material cost and capital investment cost can be reduced.

[0082] In addition, the source electrode Z wiring and the drain electrode Z wiring do not require etching resistance during etching of the protective film, so that the choice of materials that can be used increases. For example, single layer structure, poor etching resistance, and ink wiring can be used.

[0083] Further, in this embodiment, the advantages of forming the protective film 35 by coating are as follows: (1) Amorphous silicon which needs to protect moisture, impurities, etc. by using the step of the source Z drain. The point that the channel region of the layer 12 can be efficiently and completely covered, and (2) the use of the above step makes the spread of the protective film material uniform (if the spread is uneven, the transmittance, (3) By using the above difference and surface contact angle, it is possible to form a thick film only on the required TFT gap 31. (4) Utilization efficiency of materials can be improved by selectively forming a film using an inkjet apparatus. In addition, for example, when the source metal is a three-layer structure of MoZAlZMo, it is difficult to make a forward taper shape. (5) By using a coating material, the source metal has a reverse taper shape. Even in some cases, it can be protected without interruption. Note that in the present embodiment, a material having a light shielding property may be used as the protective film material. Thereby, the light shielding layer (black matrix) of a counter electrode may be unnecessary. Further, in this example, the pattern of the semiconductor film (n + type amorphous silicon layer 13 and amorphous silicon layer 12) is not limited to the form shown in FIG. 5-1, but is the form shown in FIG. May be. In the form shown in FIG. 5-2, the semiconductor pattern is completely covered with the protective film 35 (SOG material) by forming the semiconductor film pattern smaller than the source Z drain pattern. As a result, the end face of the semiconductor film is not exposed, so that the protection can be improved.

Further, means for improving the dropping accuracy with respect to the TFT gap portion 31 include means such as control of the surface contact angle and device of the source Z drain pattern.

[0085] Note that it is conventionally known that a bank is provided on a substrate when using the ink jet method. For example, when forming a wiring or the like using the ink jet method, as shown in Patent Document 4, a bank pattern is formed so as to surround the wiring formation region, and the upper part of the bank pattern is made non-lyophilic. A technique is disclosed in which the wiring formation region is made lyophilic and the landing accuracy required for the ink jet apparatus is eased. However, this technique only drops droplets of ink material or the like in the area surrounded by the bank.

On the other hand, the bank pattern of the first embodiment has open portions at both ends 34 of the TFT gap portion 31 as described above. That is, the bank pattern used in Example 1 does not have banks at both ends 34 of the force TFT channel portion 31 having banks at positions where the source electrode 15 and the drain electrode 17 are located. In the present invention, when a bank pattern having an open portion is used, a pair of electrodes are provided on the same plane as the source electrode 15 and the drain electrode 17 of the TFT 7, and a droplet is dropped at a position corresponding to the gap portion. Thus, the thin film element such as a TFT can be manufactured with a smaller number of steps than the conventional manufacturing method.

[0087] In addition, the bank pattern in the prior art is purposely produced using photolithography for the purpose of forming wiring and the like, and does not lead to a reduction in the number of times of photolithography. However, in this embodiment, the source electrode 15, the drain electrode 17 and the n + type amorphous silicon film 13 on both sides of the TFT gap portion 31 manufactured in the original manufacturing process are stacked. Since the step formed by the structure is used as the bank pattern, it is possible to reduce the landing accuracy required for the ink jet apparatus without increasing the number of times of photolithography.

[0088] In Example 1, the force for obtaining the protective film 35 as shown in FIGS. 5-1 (a) and (b) In the present invention, the shape of the protective film 35 is not particularly limited. .

In Example 1, the surface treatment is performed by a plasma treatment method using carbon tetrafluoride (CF 3) gas.

Four

However, for example, a method of forming a desired lyophobic film (lyophobic film) on the surface may be used. The lyophobic film may be a thin film in which molecules are arranged three-dimensionally or may be a monomolecular film. Materials for forming the lyophobic film include silane materials such as alkyl silane, fluorinated alkyl silane, acrylic resin, novolac resin, silicone resin, and fluorine resin, and alcohol and fluorine-based solvents. A fluid material composed of an organic solvent such as water or the like can be used. In addition, examples of the method for forming the lyophobic film include a spray method, a vapor deposition method, a CVD method, a sputtering method, a spin coating method, a dipping method, an ink jet method, and the like, and may be combined with the plasma treatment method. Further, the lyophobic film may be left in the structure of TFT. For example, in FIG. 6A, the lyophobic film 76 is left in the TFT gap portion 31. FIG. 6B is a schematic cross-sectional view taken along the line O—O in FIG.

[Example 2]

In this example, the gate electrode Z wiring forming process, the gate insulating film Z lower semiconductor film Z upper semiconductor film forming process, the source Z drain electrode Z wiring forming process, the channel etching process (upper semiconductor film pattern) Are sequentially performed, followed by a protective film forming process, followed by a lower semiconductor film patterning process. That is, in this embodiment, as shown in the manufacturing process flow in FIG. 7, the lower semiconductor film patterning process is performed after the protective film 35 is formed, and is formed using the SOG material applied and formed in the TFT gap portion. The same process as in Example 1 can be performed except that the lower amorphous silicon film 27 is removed by etching using the protective film 35 and the source Z drain pattern as a mask. According to this example, a TFT having the planar pattern shown in FIG. 8 can be manufactured. 7A is a schematic cross-sectional view showing the TFT after the channel etching process of Example 2 and the configuration in the vicinity thereof, and FIG. 7B is a schematic view of the TFT after the protective film forming process of Example ^2. FIG. 4C is a schematic cross-sectional view showing the configuration in the vicinity thereof, and FIG. 5C is a schematic cross-sectional view showing the configuration of the TFT after the semiconductor film patterning step of Example 2 and the configuration in the vicinity thereof. FIG. 8 is a schematic plan view showing the configuration of the TFT and its vicinity after the semiconductor film patterning process of the second embodiment.

According to the present embodiment, the same effects as those of the first embodiment can be obtained, and the photoresist forming process for patterning the amorphous silicon film 27 can be reduced.

[Example 3]

In this embodiment, after the gate electrode Z wiring forming process, the gate insulating film forming process, and the source Z drain electrode Z wiring forming process are sequentially performed, the semiconductor layer forming process is performed. That is, in this embodiment, as shown in the manufacturing process flow in FIG. 9, a coating-type semiconductor material is applied and formed in the TFT gap portion by an inkjet apparatus. This eliminates the need for semiconductor layer deposition by a CVD apparatus. According to the present embodiment, a TFT having the planar pattern shown in FIG. 10 can be manufactured.

9A is a schematic cross-sectional view showing the structure of the TFT after the source Z drain electrode Z wiring formation step and its vicinity in Example 3, and FIG. 9B is a schematic cross-sectional view of the semiconductor layer of Example 3. It is a schematic sectional drawing which shows the structure of TFT after the formation process, and its vicinity. FIG. 10 is a schematic plan view showing the configuration of the TFT and its vicinity after the semiconductor layer forming step of the third embodiment.

[0091] Examples of the solid content of the semiconductor material include tin oxide, indium oxide, titanium oxide, strontium titanate, zinc oxide, gallium nitride, and copper indium oxide. Furthermore, on the semiconductor layer 36 made of a semiconductor material, a film such as an SOG material may be laminated as a protective film.

In this embodiment, the advantages of forming the semiconductor layer 36 by coating are as follows: (1) By using the step between the source Z and the drain, the TFT gap (channel groove) is made into a silicon (Si) layer. (2) By using the above step, the spread of the semiconductor layer material becomes uniform (because the area of the semiconductor layer becomes nonuniform when spread unevenly, Capacitance and IV characteristics may change between adjacent picture elements and display quality may deteriorate.) (3) By using the above step and surface contact angle, a thick film is formed only in the necessary TFT gap. The point which can be mentioned.

[0093] (Example 4)

In this example, a TFT with a positive stagger structure was manufactured. Specifically, after the electrode Z wiring formation process of the source Z drain and the lower semiconductor layer formation process are sequentially performed, the light shielding layer formation process is performed, followed by the upper semiconductor layer formation process and the gate insulation process. A film forming process and a gate electrode Z wiring forming process are sequentially performed. That is, in this embodiment, as shown in the manufacturing process flow in FIG. 11, a light shielding material is applied and formed by an inkjet device in the TFT gap portion after the source Z drain patterning. This eliminates the need for resist film formation, exposure, etching and stripping steps for forming the light shielding layer 37. In addition, the step portion formed by the lower semiconductor layer (for example, n + type amorphous silicon layer) and the electrode Z wiring of the source Z drain, that is, the channel groove, is filled with a light-shielding material having fluidity. It is possible to prevent breakage when forming a layer (for example, an amorphous silicon layer). According to this embodiment, a TFT having the planar pattern shown in FIG. 12 can be manufactured.

FIG. 11 (a) is a schematic cross-sectional view showing the TFT and the structure in the vicinity thereof after the lower semiconductor layer forming step of Example 4, and FIG. 11 (b) is after the light shielding layer forming step of Example 4. FIG. 6C is a schematic cross-sectional view showing the configuration of the TFT and its vicinity, and FIG. 6C is a schematic cross-sectional view showing the configuration of the TFT and its vicinity after the gate electrode Z wiring formation process of Example 4. FIG. 12 is a schematic plan view showing the configuration of the TFT and its vicinity after the gate electrode Z wiring forming process of the fourth embodiment.

In this embodiment, the advantages of forming the light shielding layer 37 by coating are as follows: (1) By using the step between the source Z drain, the TFT gap portion (channel groove) is made more efficient by the light shielding material. (2) Use of the above steps makes the spread of the light shielding material uniform (if the light shielding material spreads unevenly in unnecessary parts, the aperture ratio (3) By using the above step and surface contact angle, only the necessary TFT gap area can be obtained. It is possible to form a thick film.

[0095] (Other)

In Examples 2 and 4, on the source wiring and gate wiring, for the purpose of preventing corrosion, etc. When it is preferable to provide a functional film (a protective film or a light shielding layer), the functional film may be formed by applying a functional material such as an SOG material to the wiring portion simultaneously with the protection of the TFT portion. For example, it may be formed on the source wiring 14 as shown in FIG. As a result, corrosion of the wiring can be prevented, and if a low dielectric constant material is used, the capacitance with the upper layer can be reduced.

[0096] As a specific example of forming a functional film on the wiring, (1) by applying a functional material such as a low dielectric constant SOG material on the gate, the source, the pixel electrode, and the counter electrode The capacity of can be reduced. However, in this case, when the gate patterning is completed, it is necessary to apply and form a functional material using an ink jet apparatus using the gate pattern. (2) Capacitance between the pixel electrode and the counter electrode can be reduced by applying and forming a low dielectric constant functional material on the source. In this case, it can be formed at the same time as the functional material is applied to the TFT gap. (3) In the positive stagger structure, the capacitance between the gate and the counter electrode can be reduced by applying and forming a low dielectric constant functional material on the source. (4) In a positive staggered structure, if the functional material is applied and formed on the gate and the side surface of the semiconductor layer (eg, Si layer) can also be covered, the semiconductor layer (eg, Si layer) can be formed without increasing the number of masks. Protection is possible.

[0097] (Comparative Example 1)

As Comparative Example 1, a conventional method for manufacturing an inverted staggered amorphous silicon TFT will be described with reference to FIGS.

14A is a schematic cross-sectional view showing the TFT after the channel etching process of Comparative Example 1 and the configuration in the vicinity thereof, and FIG. 14B is the TFT after the protective film forming process of Comparative Example 1 and its TFT. FIG. 4C is a schematic cross-sectional view showing a configuration in the vicinity, and FIG. 5C is a schematic cross-sectional view showing a TFT after the protective film patterning process of Comparative Example 1 and the configuration in the vicinity thereof. FIG. 15 is a schematic plan view showing the configuration of the TFT and its vicinity after the protective film patterning process of Comparative Example 1. FIG. Further, FIG. 16 is a schematic cross-sectional view corresponding to (a) to (c) of FIG. 14 and showing the configuration of the source wiring and its vicinity after the channel etching process of Comparative Example 1, and (b) is a comparison. FIG. 6 is a schematic cross-sectional view showing the source wiring after the protective film formation process of Example 1 and the configuration in the vicinity thereof, and (c) shows the configuration of the source wiring after the protective film patterning process in Comparative Example 1 and the vicinity thereof. It is a schematic sectional drawing. [0098] In Comparative Example 1, the gate electrode Z wiring forming step, the gate insulating film Z the lower semiconductor film Z, the upper semiconductor film forming step, the lower and upper semiconductor film patterning steps, and the source Z drain electrode Z wiring After the formation process and the channel etching process are performed in order, a protective film formation process using a CVD method is performed, followed by a protective film patterning process for forming a photoresist, etching, and resist removal. Is called. That is, in Comparative Example 1, as shown in the manufacturing process flow in FIG. 14, after the protective film 35a is formed on the entire surface of the substrate by the CVD method, the patterning force photolithography of the protective film 35a is performed. Therefore, in Comparative Example 1, the number of photoresists is one more than in Example 1.

[0099] (Example 5)

In Examples 1 to 4, force showing the TFT manufacturing method of the present invention In Example 5, TFT shapes suitable for these manufacturing methods will be described with reference to FIGS. 17-1 and 17-2. . In the figure, components having substantially the same functions as those in the first embodiment are denoted by the same reference numerals.

[0100] Fig. 17-1 (a) is a schematic plan view showing the structure of the TFT of Example 5, and (b) is an X of (a).

It is a schematic sectional drawing in an X-ray.

As shown in FIGS. 17-1 (a) and (b), the TFT 121 of this embodiment has a bottom gate structure, and has a gate electrode 10 branched from the gate wiring 9 on the glass substrate 8 and an upper layer thereof. The gate insulating film 11, the amorphous silicon layer 12, the n + type amorphous silicon layer 13, the source wiring 14, the branched source electrode 15, and the drain electrode 122 connected to the drain connection wiring 16 are configured. Specifically, in the TFT 121, the drain electrode 122 has a partial notch at the end on the channel portion side.

Here, in the amorphous silicon layer 12, a TFT channel portion 18 is formed in a lower layer region of a gap portion formed between the source electrode 15 and the drain electrode 122, and the TFT channel portion 18 is formed in the gap portion. A protective film (functional film) 35 is formed to cover the film. The drain connection wiring 16 is formed, for example, for connecting a pixel electrode (not shown) and the drain electrode 122 in a display application.

[0102] Figure 17-1 Ding shown in (&) and (1))? Ding 121 has a notch 122a near the center of drain electrode 122. However, the notch 122a is also formed on the glass substrate 8 with the gate electrode 10 and the gate. Since the gate insulating film 11 and the amorphous silicon film 12 are stacked, it can function as a TFT channel.

Depth Wa of the notch 122a shown in FIG. 17- 1 (a) is Wa = 5 _i um, width Wb is set to Wb = 10 / zm. In Fig. 17-1 (a), L is L = 3 m and W is W = 60 m.

[0103] Hereinafter, the reason why such a notch 122a is provided in the present embodiment will be described.

It is assumed that the manufacturing method of Example 1 is used as the TFT manufacturing method of this example.

In the manufacturing method of Example 1, the protective film 35 is formed in the TFT gap portion 31. At this time, the protective film 35 is produced by landing droplets of an insulating material having fluidity on the substrate using an ink jet apparatus as described in the first embodiment. Expands to fill the TF T gap 31.

[0104] Therefore, first, under the design conditions described in Example 1, the volume of the liquid droplet filling the TFT gap 31 was calculated. That is, in the gap region between the source electrode 15 and the drain electrode 17, the height was calculated as the volume filling the step formed by the n + -type amorphous silicon layer 13 and the source electrode 15 or drain electrode 17 layer. As a result of calculation using the numerical values described in Example 1, the volume of the TFT gap portion 31 was 0.054 pl.

Therefore, when the production method of Example 1 is used, an appropriate droplet volume is too much if 0.5 pl is considered as a guide if the solid content concentration is 10% by volume. The surface tension limit is exceeded at both ends 34 of the TFT gap 31, and a large amount of droplets overflows from both ends 34 of the TFT gap 31.

[0105] On the other hand, considering the minimum volume of droplets that can be ejected by the inkjet apparatus, the volume of droplets ejected in Example 1 that is often about lpl or more was 1 to 2pl. This is due to the structure of the head of the ink jet device. In other words, the smaller the droplet, the smaller the diameter of the nozzle (discharge hole), so that high processing accuracy is required and the nozzle is likely to be clogged.

Therefore, the minimum volume of droplets that can be ejected by the ink jet apparatus is a value that is at least twice as large as the volume of the TFT gap portion 31 of Example 1 previously calculated.

In order to fill the gap between the two, as in this embodiment, the source electrode and the Z or drain It is preferable to provide a notch in the in-electrode. Thus, in the protective film forming step, the notch can be made a place for absorbing excess droplets.

In the TFT 121 of this embodiment, since the notch 122a is provided in the drain electrode 122, the volume of the TFT gear portion is 0.069pl, which can be close to the volume of droplets that can be ejected by the ink jet apparatus. Therefore, in the protective film formation step, the force at both ends 34 of the TFT gap portion 31 can be prevented from overflowing a large amount of droplets, and the shape of the TFT 121 can be manufactured more stably.

[0107] The present inventors can confirm the above-described effects by experiments in which respective patterns with or without the notches 122a are prepared, and it is effective to provide notches in the source electrode and the Z or drain electrode. I found out. Note that the notch 122a is provided in the drain electrode 122, so that the on-current value of the TFT is slightly reduced. This is achieved by optimizing the entire size, etc., so that the TFT having the desired electrical characteristics can be restored. Can be designed.

[0108] As described above, when a TFT is manufactured by the manufacturing method of Example 1, by providing a partial cutout at the end of at least one of the source electrode and the drain electrode on the channel side, The separation between the volume of the TFT channel portion and the minimum volume of droplets that can be ejected by the inkjet apparatus can be reduced, and the TFT can be manufactured with a stable shape. In addition, it is not limited to the manufacturing method of Example 1, When using the manufacturing method of Examples 2-4, the same effect can be obtained.

[0109] The shape of the notch may be a shape as shown in Fig. 17-2. That is, the drain electrode 124 has a notch 124a. The depth Wa of the notch 124a shown in FIG. 17-2 (a) is ϋ μm and the width Wb is Wb = 3; zm. The width Wb is the same value as the TFT channel length L. The protective film made of droplets becomes bowl-shaped (the cross-sectional shape is U-shaped), that is, the film thickness tends to decrease as the distance from the source or drain electrode within the TFT gap section increases. If the film thickness is reduced in this way, the role as a protective film may not be sufficiently fulfilled. Therefore, as in this embodiment, the cutout is provided with the same width as the TFT channel length formed using the best resolution of photolithography, so as to avoid a reduction in the thickness of the central portion as much as possible. Can do. A plurality of such notches may be provided. Yes.

[0110] (Example 6)

The TFT of the present invention may be a TFT including a U-shaped or U-shaped portion in the shape of the channel portion. This embodiment shows such a TFT.

An example of the TFT is a TFT 125 having a shape as shown in FIGS. 18 (a) and 18 (b). FIG. 18 (a) is a schematic plan view showing the TFT 125, and FIG. 18 (b) is a schematic cross-sectional view taken along line YY in FIG. 18 (a). The TFT 125 shown in FIG. 18 has a shape in which the TFT channel portion 18 has a U-shape (U-shape) and is bent at two locations. Similarly, the drain electrode 126 has a U-shaped shape. The force source electrode 127 has a linear shape. Here, since the shape of the TFT channel portion 18 is a U-shaped shape, it will fit within a smaller circle!

Such a shape of the TFT 125 is suitable for the manufacturing method of the first embodiment. This is related to the fact that the droplet immediately after landing on the substrate in the protective film forming step has a substantially circular planar shape. By keeping the shape of the TFT channel portion 18 in such a small circle, the liquid droplet can fill many locations in the TFT gap portion immediately after landing. Therefore, it is possible to produce a TFT having a substantially longer channel width and TFT without extending the distance of the droplet after landing so much, and the channel portion is particularly long in the method of the present invention!で Effective when manufacturing TFTs. In addition, the area ratio of the channel in the portion of the semiconductor layer constituting the semiconductor element can be increased, and the volume of the channel groove can be increased. As a result, the fluid material dropped into the channel groove can be easily retained in the groove, and the functional film can be formed with high accuracy.

[0112] For reference, when a TFT 125 was manufactured by the manufacturing method shown in Example 1, an allowable landing error of an ink jet apparatus was examined.

First, detailed shapes of the source electrode 127 and the drain electrode 126 will be described with reference to FIG. FIG. 19 is an enlarged schematic plan view showing the source electrode 127 and the drain electrode 126 in FIG. 18 (a). In the figure, the distance L between the source electrode 127 and the drain electrode 126 is L = 3 m, and the sizes of the source electrode 127 and the drain electrode 126 are Wl = 30 _i um, W2 = ll μm, W3 = 40 μm and W4 = 43 μm. Source electrode 127 and W3 and W4 are close Considering that the TFT channel part is formed in the TFT gap part 31, which is the gap between the drain electrodes 126, it can be said that the shape of the TFT 125 is almost nearly square. The effective TFT channel width W is not clear, but it seems to be equivalent to W = 59 to 71 μm, considering the lengths of the portions of the source electrode 127 and drain electrode 126 that are in contact with the channel. . Since TFT7 in Example 1 was W = 60 _i um, it is close to this value.

[0113] As an experimental method, an optical microscope was used in accordance with the shape of the protective film formed by landing a droplet at a position intentionally shifted from the center of the TFT gap 31 indicated by X in FIG. The method of observing at 500 times magnification was used. The judgment criteria were “good” when the protective film was within the TFT gap 31 and the boundary of the protective film was near both ends 34 of the TFT gap 31 and “bad” otherwise. In other words, when the formed protective film protrudes greatly outside the both ends 34 of the TFT gap portion 31, it is determined as “defective”. The results are shown in Table 1 below.

[0114] [Table 1]

I ^ 0 £ / 900Zdf / e :) d 8ε L06LU 900Z OAV [0115] The X coordinate and Y coordinate in the table represent the amount of shift from the center of the TFT gap portion 31, and the unit is / zm. The X and Y axes were oriented as shown in FIG. As shown in Table 1, in this example, the X coordinate is −9 m to +9 m, and the Y coordinate is −9 πι to + 6 / ζ πι, all being good.

[0116] It is also possible to combine the U-shape or U-shape as in this embodiment with the notch shown in Embodiment 5, and both effects can be obtained. As an example, FIGS. 20 (a) and (b) show such TFT128. Fig. 20 (a) is a schematic plan view, and Fig. 20 (b) is a schematic cross-sectional view along line ^-^ of Fig. 20 (&). Here, the drain electrode 129 has a U-shaped TFT channel portion 18 and further has two cutout portions 129a and 129b. The sizes of the notches 129a and 129b are both Wa = 5 m and Wb = 3 _i um.

A similar example is shown in FIGS. 21 (a) and (b). FIG. 21 (a) is a schematic plan view, and FIG. 21 (b) is a schematic cross-sectional view along the line AB-AB in FIG. 21 (a). The TFT 131 in these drawings has a source electrode 133 and a drain electrode 132 having a notch 132a. The size of the notch 132a is Wa = 5 _i um and Wb = llm. In the TFT 131 shown in FIG. 21, the channel length of the TFT corresponds to a portion provided with the partial force notch 132a in which the channel length is partially enlarged.

[0118] (Example 7)

The TFT of the present invention may be a TFT in which the source electrode and the drain electrode have corner portions (corner portions) near the end portion of the TFT channel portion. The present embodiment relates to such a TFT.

The TFT of this embodiment has the same form as TFT 7 shown in FIGS. 1 (a) and (b), for example.

Fig. 22 (a) is an enlarged view of the main part of the source electrode 15 etc. shown in Fig. 1 (a), partially extracted. In the figure, near the ends 141 and 142 of the TFT channel 18, the source The electrode 15 and the drain electrode 17 have corner portions 143, 144, 145, and 146.

As a result of intensive studies, the inventors of the present invention, when manufacturing TFTs by the method shown in Examples 1 to 4, near the ends of the TFT channel part as shown in FIG. It was found that TFTs with a drain electrode having a corner portion are preferable. Especially when the angle of the corner portion is 90 °, the shape of the TFT is stabilized. [0119] This can be confirmed, for example, by fabricating TFT 147 shown in Fig. 22 (b) by the method of Example 1 for comparison and comparing it with the case of Fig. 22 (a). Fig. 22 (b) is an enlarged view of the main part of the TFT source electrode 149, etc. partially extracted. In the figure, the source electrode 149 connected to the source wiring 148 and the drain connection wiring 150 are connected. And a TFT channel portion 152 made of an amorphous silicon film formed between the source electrode 149 and the drain electrode 151. Here, the source electrode 149 and the drain electrode 151 have corner portions 155 and 156 in the vicinity of the end portion 153 of the TFT channel portion 152, but only the source electrode 149 has a corner portion 157 in the vicinity of the other end portion 154. On the other hand, the drain connection wiring 150 and the drain electrode 151 are connected in a straight line shape, that is, have no corner portion.

[0120] As a result of manufacturing such TFT147, as shown in FIG. 22 (b), at the end 154 of the TFT channel portion 152, the contour line of the protective film extends to the drain connection wiring 150 side. Compared to the end 153, it was likely to be indefinite, such as variations among multiple TFTs.

This is related to the behavior of the droplets in the protective film formation process, and is thought to be due to the difference when the droplets slightly protruding from the end portions 153 and 154 recede due to drying of the organic solvent. That is, since the source electrode 149 and the drain electrode 151 have corner portions 155 and 156 at the end portion 153, the shape of the bank formed by these also has a corner portion, and the outline of the droplet is the two corner portions. Retreat to the line connecting On the other hand, since the end portion 154 does not have a corner portion on the drain electrode 151 side, it is difficult to determine the point at which the outline of the droplet recedes. Since the shape of the TFT channel portion 152 is determined by the contour line after the liquid droplet has receded, it is considered that the shape of the functional film is less likely to be determined at the end portion 154.

[0121] On the other hand, if the TFT has a source electrode and a drain electrode with corner portions near all ends of the TFT channel portion, such as TFT7 shown in FIG. The shape at both ends of the membrane was stable.

Thus, when a TFT is manufactured by the method shown in Examples 1 to 4, the source electrode and the drain electrode have corner portions near all the ends of the TFT channel portion as in this embodiment. The TFT shape is preferable, especially if the corner angle is 90 ° or less. Is stable.

Note that in this example, the same results were obtained for the manufacturing methods of Examples 2 to 4 described using the TFT manufacturing method described in Example 1 as an example.

[0123] In addition, it is possible to combine the form having the U-shaped or U-shaped channel shown in Example 6 with the form of this example, and both effects can be obtained. It is effective.

As an example, such a TFT 158 is shown in FIGS. FIG. 23 (a) is a schematic plan view, and FIG. 23 (b) is a schematic cross-sectional view of the AC—AC line of FIG. 23 (a). Here, the TFT 158 has a U-shape in a region 160 in the force diagram having the TFT channel portion 159.

[0124] (Example 8)

The TFTs and their manufacturing methods shown in Examples 1 to 7 can also be applied to diodes having the same structure as those of the TFTs. The present embodiment relates to such a diode.

Examples of the diode include those having the structure shown in FIGS. 24 (a) and (b). FIG. 24 (a) is a schematic plan view showing the configuration of the diode of this example and the vicinity thereof. Figure 24 (b) shows a schematic cross-sectional view along the line AD-AD.

[0125] The diode 171 of this example has an inverted staggered structure, and has a gate electrode 173, a gate insulating film 174, an amorphous silicon layer 175, and an n + type amorphous silicon layer 176 on a glass substrate 172. And a drain electrode 178 connected to the connection wiring 177, a source electrode 180 connected to the connection wiring 179, a protective film (functional film) 181 and a conductive film 182 for connection are stacked. Have A protective film 181 is formed between the drain electrode 178 and the source electrode 180. Under the protective film 181, a part of the amorphous silicon layer 175 forms a channel portion 183, and the TFT portion 185 having the same structure as the TFT is formed by this and the gate electrode 173 and the like. On the other hand, a contact portion 184 is formed in part of the connection wiring 179. In the contact portion 184, the gate insulating film 174 is opened, and a conductive film 182 for connection is provided in the upper layer with the opening as a center, and the gate electrode 173, the connection wiring 179, and the source electrode 180 are electrically connected. Here, the conductive film 182 for connection is made of ITO ( The other constituent elements are the same as in Example 1.

The diode 171 of this embodiment is formed so as to connect between arbitrary wirings such as adjacent source wirings and gate wirings in the active matrix substrate. The purpose of this is to prevent elements such as TFTs and wiring in the substrate from being burned out due to static electricity. For example, when static electricity accumulates on a certain wiring and has a sufficiently higher potential than the surroundings, the source electrode and gate electrode of the diode electrically connected to the potential also become high potential, Since the TFT section is turned on and conducted, static electricity on this wiring can be released. Therefore, the above-described burnout and the like can be prevented. On the other hand, if there is no accumulation of static electricity, the TFT portion is not in an on state, so that the wiring having high resistance can be substantially electrically separated.

As a manufacturing method of the diode 171, in addition to the manufacturing method of Example 1, a step of forming the conductive film for connection 182 may be added, and a film for forming this is formed on the entire surface of the substrate. And it can produce by patterning by photolithography. Here, the connection conductive film 182 was formed by a sputtering method.

Thus, since the protective film 181 is manufactured by the method of Example 1, the shape reflects the shape of the droplet of the insulating material having fluidity discharged using the ink jet apparatus. RU The shape of the protective film 181 is not circular because the direction in which the droplets flow is controlled by the banks that form the drain electrode 178 and the source electrode 180 and the volatilization of the organic solvent in the droplets. In some cases, liquid droplets were formed between the drain electrode 178 and the source electrode 180.

[0129] As shown in this example, the TFT fabrication methods of Examples 1 to 7 can be applied to a diode having a structure part of those TFTs inside, and this example is also an example. Like 1-7, it contributes to the reduction of the number of photolithography. Therefore, the same manufacturing merit can be obtained.

[0130] (Example 9)

The active matrix substrate (circuit substrate) of this example is a TFT array substrate and has the form shown in FIG. 25-1. Figure 25-1 shows the configuration of the active matrix substrate of Example 9. It is a schematic plan view.

The active matrix substrate 191 of this embodiment has a source wiring 192, a gate wiring 193, and a TFT 194, which is a kind of semiconductor element, corresponding to each intersection point thereof. In the active matrix substrate 191, a large number of TFTs 194 are formed, and can be divided into, for example, an effective region 195 used as an image display region and a peripheral region 196 located outside the effective region 196. The peripheral area 196 is an area for providing wiring for driving the active matrix substrate 191, terminals (not shown) for connection to an external substrate, and the like. In the active matrix substrate 191, a diode 197, which is a kind of semiconductor element, is provided in the peripheral region 196.

Here, the TFT 194 is connected to a pixel electrode (not shown) for performing image display and the like, a source wiring 192 and a gate wiring 193, and the shape thereof has the shape shown in the first embodiment. . In addition, the diode 197 has a shape shown in Embodiment 8 by connecting adjacent gate wirings 193 to serve as a protective element for preventing the wiring and elements from being burned by static electricity. In addition, as these production methods, the methods described in Examples 1 to 4 and 8 can be used.

[0132] As shown in Fig. 25-1, the active matrix substrate 191 of this embodiment is characterized in that a TFT 194 and a diode 197 are arranged in a straight line group (parallel line group) with an equal interval in the gate wiring direction. That is. Here, the TFT 194 is a semiconductor element in the effective area 195, and the diode 197 is a semiconductor element in the peripheral area 196, and the semiconductor elements for different purposes in such different areas are in a straight line. Is characteristic.

[0133] When the TFT 194 and the diode 197 are manufactured, an ink jet apparatus is used as a pattern forming apparatus capable of discharging or dropping a fluid insulating material or the like as droplets at a selective place on a substrate surface. Was used.

The ink jet apparatus includes an ink jet head, and ejects droplets while changing the relative position between the ink jet head and the substrate. At this time, the movement of the inkjet head viewed from the substrate side repeats scanning in one direction in the plane, and moves the ink jet head by a predetermined amount in the direction perpendicular to the scanning direction between the scans. It is common. At this time, in order to efficiently process the substrate, the number of scans If you reduce the amount of

On the other hand, since the nozzles for ejecting droplets are arranged at equal intervals in the ink jet head, the droplets cannot be ejected to the substrate region located between the nozzles. Drops can be dropped in a single scan only at locations on the straight line group at equal intervals through which each nozzle passes. Therefore, in order to minimize the number of scans, it is preferable that the positions where droplets or the like are landed, that is, the locations where the semiconductor elements are formed are on a group of straight lines as equally spaced as possible.

For these reasons, the arrangement of TFT 194 and diode 197 in this example is suitable for the TFT manufacturing method of Examples 1 to 4 and the diode manufacturing method of Example 8, and the number of scans of the ink jet head. This makes it possible to efficiently process the substrate. Although not shown, in this embodiment, semiconductor elements such as TFTs and diodes other than TFT 194 and diode 197 are provided in either or both of effective region 195 and peripheral region 196 on active matrix substrate 191. However, all the semiconductor elements that need to be arranged must be arranged on a group of equally spaced lines.

As a modification of the present embodiment, as shown in FIG. 25-2, an active matrix substrate in which the TFT 199 and the diode 200 are located on a straight line group 201 at equal intervals in the source wiring direction. 202 may be used. Here, FIG. 25-2 is a schematic plan view showing a configuration of an active matrix substrate 202 which is a modification of the present embodiment. Here, although not shown, TFTs other than TFT 199 and diode 200, semiconductor elements such as diodes, and the like may be provided in either or both of effective region 195 and peripheral region 196 on active matrix substrate 202. Good.

[0137] Note that in an active matrix substrate generally used for a liquid crystal display device or the like, the interval between the gate lines is often wider than the interval between the source lines. Therefore, the inkjet head is viewed from the substrate side. Therefore, it is preferable to scan in the gate wiring direction. This is because the interval between the nozzles provided in the ink jet head can be widened, so that the number of nozzles is reduced, and processing accuracy and uniformity of droplet landing distribution between the nozzles can be easily maintained.

[0138] In the present invention, the active matrix substrate is provided in the effective area, and the source wiring. An active matrix substrate having a plurality of semiconductor elements arranged corresponding to each intersection of the gate wiring and the gate wiring, and these semiconductor elements are an active matrix substrate on a group of evenly spaced lines. Moyo.

For example, as shown in FIG. 25-3, the active matrix substrate 207 may be located on the TFTs 203 and 204, the diode 205, and the straight line group 206 at equal intervals in the force source wiring direction. Here, FIG. 25-3 is a schematic plan view showing a configuration of an active matrix substrate 207 which is a modification of the present embodiment. Here, although not shown, even if semiconductor elements such as TFTs and diodes other than TFTs 203 and 204 and diodes 205 are provided in either or both of the effective region 195 and the peripheral region 196 on the active matrix substrate 207. Good.

[0139] In the present invention, the active matrix substrate is an active matrix substrate having a plurality of source wirings, a plurality of gate wirings, and semiconductor elements on a (glass) substrate, and a large number of the semiconductor elements are formed. The semiconductor element force arranged in the effective region is arranged on two equally-spaced straight line groups in the gate wiring direction and the Z or source wiring direction. However, the active region substrate may be an active matrix substrate in which the (second) semiconductor element in the peripheral region is arranged on the straight line group! For example, as shown in FIG. 25-4, TFTs 208 and 209 are provided in the vicinity of the intersection of the source wiring 192 and the gate wiring 193, and the TFT 208 and the diode 210 are equally spaced from each other in the gate wiring direction. The TFT 209 located on the straight line group 211 may be an active matrix substrate 213 located on the second straight line group 212 in the gate wiring direction that is equally spaced from each other. Here, FIG. 25-4 is a schematic plan view showing a configuration of an active matrix substrate 213 which is a modification of the present embodiment. Here, although not shown in the figure, semiconductor elements such as TFTs and diodes other than TFTs 209 and 209 and diodes 210 may be provided in either or both of the effective region 195 and the peripheral region 196 on the active matrix substrate 213. Good.

[0140] In the present invention, the active matrix substrate is an active matrix substrate having a plurality of source wirings, a plurality of gate wirings, and semiconductor elements on a (glass) substrate, and a large number of the semiconductor elements are formed. Effective area and surrounding area around it, Semiconductor element power disposed in the effective area has a portion disposed on at least one equally spaced line group in the gate wiring direction and z or source wiring direction, and is an integral part of the distance between the straight line group from the straight line group. The active matrix substrate may be an active matrix substrate in which the (second) semiconductor element in the peripheral region is arranged on a straight line determined by a distance of 1.

For example, as shown in FIG. 25-5, a TFT 214 is provided, and on a fourth straight line group 216 determined by a distance 12 from a third straight line group 215 equally spaced from each other corresponding to the arrangement of the TFT 214, An active matrix substrate 218 having a diode 217 in the peripheral region may be used. Here, when the interval between the third straight line groups 215 in which the TFTs 214 are arranged is II, 12 = 11/3. FIG. 25-5 is a schematic plan view showing the configuration of an active matrix substrate 218 which is a modification of the present embodiment. Although not shown here, semiconductor elements such as TFTs and diodes other than TFT 214 and diode 217 may be provided in either or both of effective region 195 and peripheral region 196 on active matrix substrate 218. .

[0142] This application claims priority (based on 35 USC 119), based on Japanese Patent Application 2005-132810 filed April 28, 2005. The contents of this application are hereby incorporated by reference in their entirety.

Further, “above” and “below” in this specification include the numerical values.

Brief Description of Drawings

[0144] [FIG. 1] (a) is a schematic plan view showing a TFT fabricated using the manufacturing method of Example 1 and the configuration in the vicinity thereof, and (b) is an A—A diagram of (a). It is a schematic sectional drawing in a line.

FIG. 2 is a schematic perspective view showing the configuration of the ink jet apparatus.

[FIG. 3] (a) is a schematic plan view showing a state at the moment when a droplet has landed on the TFT gap portion 31, and (b) is a schematic cross-sectional view taken along the line FF in (a).

[FIG. 4] (a) is a schematic plan view showing a state in which the liquid droplet 32 shown in FIG. 3 (a) has landed and then deformed due to its fluidity, and (b) is (a) It is a schematic sectional drawing in the GG line of).

[FIG. 5-1] (a) is a schematic plan view showing a state in which a protective film 35 is formed in the TFT gap portion 31, and (b) is a schematic cross-sectional view taken along line H—H in (a). It is.

[FIG. 5-2] (a) is a schematic plan view showing another example of a state in which the protective film 35 is formed in the TFT gap portion 31, and (b) is a line H—H in (a). FIG. 圆 6] (a) is a schematic plan view showing a state in which the lyophobic film 76 is left in the TFT gap portion 18, and (b) is a schematic cross-sectional view taken along the line OO in (a). .

[FIG. 7] (a) is a schematic cross-sectional view showing the TFT after the channel etching process of Example 2 and the configuration in the vicinity thereof, and (b) is the TFT after the protective film forming process of Example 2 and its FIG. 5C is a schematic cross-sectional view showing a configuration in the vicinity, and FIG. 5C is a schematic cross-sectional view showing a configuration of the TFT after the semiconductor film patterning process of Example 2 and the configuration in the vicinity thereof.

FIG. 8 is a schematic plan view showing the configuration of the TFT and its vicinity after the semiconductor film patterning process of Example 2.

[FIG. 9] (a) is a schematic cross-sectional view showing the configuration of the TFT after the source Z drain electrode Z wiring formation step and its vicinity in Example 3, and (b) is a semiconductor layer of Example 3. It is a schematic sectional drawing which shows the structure of TFT after the formation process, and its vicinity.

FIG. 10] A schematic plan view showing the configuration of the TFT and its vicinity after the semiconductor layer formation step of Example 3.

[FIG. 11] (a) is a schematic cross-sectional view showing the configuration of the TFT after the source Z drain electrode Z wiring formation process and its vicinity in Example 4, and (b) is a light shielding layer of Example 4. FIG. 6C is a schematic cross-sectional view showing the configuration of the TFT after the formation process and the vicinity thereof, and FIG. 6C is a schematic cross-sectional view showing the configuration of the TFT after the formation process of the gate electrode Z wiring of Example 4 and the vicinity thereof.

12] A schematic plan view showing the configuration of the TFT and its vicinity after the light shielding layer forming step of Example 4. FIG.

[FIG. 13] (a) is a schematic cross-sectional view showing an arrangement state of the source wiring 14 before forming the protective film 35 in Examples 2 and 4, and (b) is a protective film on the source wiring 14. 6 is a schematic cross-sectional view showing a configuration after forming 35. FIG.

[FIG. 14] (a) is a schematic cross-sectional view showing the TFT after the channel etching process of Comparative Example 1 and the configuration in the vicinity thereof, and (b) is the TFT after the protective film forming process of Comparative Example 1 and its TFT FIG. 5C is a schematic cross-sectional view showing a configuration in the vicinity, and FIG. 5C is a schematic cross-sectional view showing a configuration of the TFT after the protective film patterning process of Comparative Example 1 and the configuration in the vicinity thereof.

15] A schematic plan view showing the structure of the TFT after the protective film patterning process of Comparative Example 1 and the configuration in the vicinity thereof. FIG. 16 is a schematic cross-sectional view corresponding to (a) to (c) of FIG. 14 and showing the arrangement state of the source wiring after the channel etching process of Comparative Example 1, and (b) of FIG. FIG. 7 is a schematic cross-sectional view showing the arrangement state of the source wiring after the protective film forming step, and (c) is a schematic cross-sectional view showing the arrangement state of the source wiring after the protective film patterning step of Comparative Example 1 .

[FIG. 17-1] (a) is a schematic plan view showing the configuration of the TFT of Example 5, and (b) is a schematic cross-sectional view taken along line XX of (a).

FIG. 17-2 is a schematic plan view showing another example of the structure of the TFT of Example 5.

[FIG. 18] (a) is a schematic plan view showing a TFT 125, and (b) is a schematic cross-sectional view taken along line Y—Y in (a).

FIG. 19 is an enlarged schematic plan view showing the source electrode 127 and the drain electrode 126 in FIG. 18 (a).

FIG. 20 (a) shows a TFT 1 implemented by combining the embodiment in which the drain electrode shown in Example 5 has a notch and the embodiment shown in Example 6 in which the channel has a U-shape or U-shape. 28 is a schematic plan view showing the configuration of 28, and (b) is a schematic sectional view taken along the line AA-AA in (a).

FIG. 21 (a) shows a TFT 1 implemented by combining the embodiment in which the drain electrode shown in Example 5 has a notch and the embodiment shown in Example 6 in which the channel has a U-shape or U-shape. FIG. 32 is a schematic plan view showing the configuration of 31, and (b) is a schematic sectional view taken along line AB-AB of (a).

[Fig. 22] (a) is an enlarged view of the main part of the source electrode 15 shown in Fig. 1 (a), partially extracted, and (b) is for comparison with the case of (a). FIG. 9 is an enlarged view of a main part, partially showing a TFT source electrode 149 and the like manufactured by the method of Example 1 (Example 7).

[FIG. 23] A form having a U-shaped channel or a U-shaped channel as shown in Example 6, and a portion where the source and drain electrodes are corners near all ends of the TFT channel part shown in Example 7. FIG. 2 is a schematic plan view showing a configuration of a TFT 158 implemented in combination with a configuration having a line (b), and (b) is a schematic cross-sectional view taken along an AC-AC line in (a).

FIG. 24 (a) is a schematic plan view showing the configuration of the diode of Example 8 and the vicinity thereof, and (b) is a schematic cross-sectional view taken along the line AD-AD in (a). FIG. 25-1 is a schematic plan view showing an example of the configuration of the active matrix substrate of Example 9.

FIG. 25-2 is a schematic plan view showing an example of the configuration of the active matrix substrate of Example 9. FIG. 25-3 is a schematic plan view showing an example of the configuration of the active matrix substrate of Example 9. 25-4] A schematic plan view showing an example of the configuration of the active matrix substrate of Example 9. [FIG. 25-5] A schematic plan view showing an example of the configuration of the active matrix substrate of Example 9.

7: TFT

8: Glass substrate

9: Gate wiring

10: Gate electrode

11: Gate insulation film

12: Amonorefus silicon layer

13: n + type amorphous silicon layer

14: Source wiring

15: Source electrode

16: Drain connection wiring

17: Drain electrode

18: TFT channel

19: Board

20: Mounting table

21: Inkjet head

22: X direction drive

23: Y direction drive : Ink supply system: Control group: Amorphous silicon film: n + type amorphous silicon film: TFT gap

: Functional material droplet

: Both ends of TFT gap: Protective film

a: Protective film (before patterning) b: Protective film (after patterning): Semiconductor layer

: Light shielding layer

: Lipophilic film

1: TFT

2: Drain electrode

2a: Drain electrode notch 3: TFT

4: Drain electrode

4a: Drain electrode notch 5: TFT

6: Drain electrode

7: Source electrode

8: TFT

9: Drain electrode

9a: drain electrode notch 9b: drain electrode notch 0: source electrode 131: TFT

132: Drain electrode

132a: Notch of drain electrode

133: Source electrode

141:: TFT channel 18 edge

142:: End of TFT channel 18

143:: Source electrode 15 corner

144: ： Drain electrode 17 corner

145:: Corner of source electrode 15

146:: Corner of drain electrode 17

147:: TFT

148: Source wiring

149:: Source electrode

150:: Drain connection wiring

151:: Drain electrode

152:: TFT channel

153:: End of TFT channel 152

154:: End of TFT channel 152

155:: Corner of source electrode 149

156:: Corner of drain electrode 151

157:: Corner of source electrode 149

158:: TFT

159:: TFT channel

160:: Area

171:: Diode

172: Glass substrate

173:: Gate electrode

174:: Gate insulating film 175 :: Amorphous silicon layer

176:: n + type amorphous silicon layer

177:: Connection wiring

178:: Drain electrode

179:: Connection wiring

180:: Source electrode

181:: Protective film

182:: Conductive film for connection

183:: Channel section

184:: Contact

185:: TFT 咅

191: Active matrix substrate

192: Source wiring

193:: Gate wiring

194:: TFT

195:: Effective area (shaded area)

196: Peripheral area

197: Diode

198:: Line group

199:: TFT

200:: Diode

201:: Line group

202:: Active matrix substrate

203:: TFT

204:: TFT

205:: Diode

206:: Line group

207:: Active matrix substrate 208: TFT

209: TFT

210: Diode

211: First line group

212:: second line group

213:: Active matrix substrate

214:: TFT

215:: third line group

216:: Fourth line group

217:: Diode

218:: Active matrix substrate

Claims

The scope of the claims

[1] A method of manufacturing a semiconductor device having a channel,

The manufacturing method includes a step of forming a functional layer by dropping a functional material having fluidity into a channel groove.

2. The method for manufacturing a semiconductor element according to claim 1, wherein the functional material is an insulating material.

[3] The method of manufacturing a semiconductor element includes a step of sequentially forming a gate electrode, a gate insulating film, a semiconductor layer, and a source electrode and a drain electrode on a substrate;

Forming a protective layer by dropping an insulating material having fluidity into a channel groove formed by at least the source electrode and the drain electrode.

The method of manufacturing a semiconductor device according to claim 2, wherein:

[4] The semiconductor layer includes a lower semiconductor layer and a pair of upper semiconductor layers,

The channel groove is formed by a pair of upper semiconductor layers, a source electrode, and a drain electrode.

The method for manufacturing a semiconductor device according to claim 3, wherein:

[5] The method for manufacturing the semiconductor element includes a step of sequentially forming a gate electrode, a gate insulating film, a semiconductor film, and a source electrode and a drain electrode on a substrate;

Forming a protective layer by dropping a fluid insulating material into a channel groove formed by at least a source electrode and a drain electrode; and

3. The method of manufacturing a semiconductor element according to claim 2, further comprising: patterning a semiconductor film using the protective layer to form a semiconductor layer.

[6] The semiconductor film comprises a lower semiconductor film and a pair of upper semiconductor layers,

The channel groove is formed by a pair of upper semiconductor layers, a source electrode and a drain electrode,

The lower semiconductor film is patterned using the protective layer to form the lower semiconductor layer.

6. The method for manufacturing a semiconductor device according to claim 5, wherein:

7. The functional layer made of the insulating material is further formed on the wiring. The manufacturing method of the semiconductor element of description.

8. The method for manufacturing a semiconductor element according to claim 1, wherein the functional material is a semiconductor material.

[9] The method for manufacturing the semiconductor element includes a step of sequentially forming a gate electrode, a gate insulating film, and a source electrode and a drain electrode on a substrate;

9. The method of manufacturing a semiconductor element according to claim 8, further comprising: forming a semiconductor layer by dropping a semiconductor material having fluidity into a channel groove formed by at least the source electrode and the drain electrode. .

10. The method for manufacturing a semiconductor element according to claim 1, wherein the functional material is a light shielding material.

[11] The method for manufacturing a semiconductor device includes a step of sequentially forming a source electrode and a drain electrode on a substrate;

Forming a light shielding layer by dropping a fluid light shielding material into a channel groove formed by the source electrode and the drain electrode;

The method for manufacturing a semiconductor device according to claim 10, further comprising: sequentially forming a semiconductor layer, a gate insulating layer, and a gate electrode on the light shielding layer.

[12] The method for manufacturing the semiconductor element includes a step of sequentially forming a source electrode and a drain electrode, and a pair of lower semiconductor layers on a substrate;

In a channel groove formed by a pair of lower semiconductor layers, a source electrode and a drain electrode

A step of forming a light-shielding layer by dropping a light-shielding material having fluidity;

11. The method of manufacturing a semiconductor element according to claim 10, further comprising a step of sequentially forming an upper semiconductor layer, a gate insulating layer, and a gate electrode on the lower semiconductor layer and the light shielding layer.

13. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of bonding fluorine atoms and Z or a fluorine compound to the substrate surface before dropping the functional material having fluidity. A method for manufacturing a semiconductor device.

14. The method for manufacturing a semiconductor element according to claim 1, wherein the method for manufacturing a semiconductor element includes a surface treatment step using a plasma before dropping the functional material having fluidity.

[15] The method of manufacturing a semiconductor element according to claim 14, wherein the surface treatment step is performed in a plasma containing a fluorine-based gas.

16. The method for manufacturing a semiconductor element according to claim 1, wherein the method for manufacturing a semiconductor element includes a dry etching step before dropping the functional material having fluidity.

17. The method for manufacturing a semiconductor element according to claim 1, wherein the functional material having fluidity is applied using a coating apparatus having a multi-nozzle type discharge head and a substrate stage.

18. The method for manufacturing a semiconductor element according to claim 17, wherein the coating device is an ink jet device.

[19] The functional material having fluidity includes ethylene glycols, diethylene glycols, triethylene glycols, polyethylene glycols, propylene glycols, dipropylene glycols having a boiling point of 180 ° C or higher at 1 atm. Characterized by containing at least one ether, ester, diester and Z or ether ester selected from the group consisting of tripropylene glycols, polypropylene glycols, and butylene glycols, or hydrocarbons The method for manufacturing a semiconductor device according to claim 18.

20. A method for manufacturing a circuit board, comprising forming a semiconductor element on a substrate using the method for manufacturing a semiconductor element according to claim 1.

[21] The circuit board constitutes a display device or an imaging device, and a semiconductor element in a display region or an imaging region and a non-display region or a non-imaging region is formed by extending a gate wiring and a Z or source wiring. Are arranged on a group of parallel lines extending in the direction,

The functional layer forming step has fluidity by continuously moving the ejection head or the substrate stage in the extending direction of the gate wiring and Z or source wiring in the display area or imaging area and non-display area or non-imaging area. Item 22. The method for manufacturing a circuit board according to Item 20, wherein the functional material is applied.

[22] A semiconductor device manufactured using the method for manufacturing a semiconductor device according to [1].

[23] A semiconductor device having a channel, The semiconductor element includes a functional layer having an end portion located between the source electrode and the drain electrode having a curved shape.

[24] a semiconductor device having a channel,

The source electrode and the Z or drain electrode have a notch at the end on the channel side.

[25] A semiconductor device having a channel,

The semiconductor element has a dummy channel in the vicinity of the channel.

[26] A semiconductor device having a channel,

The semiconductor element has a dummy electrode between a source electrode and a drain electrode.

[27] A semiconductor device having a channel,

A semiconductor element, wherein a channel of the semiconductor element is bent to 2 or more.

28. The semiconductor device according to claim 27, wherein the channel has a U shape or a U shape.

[29] A semiconductor device having a channel,

The semiconductor element, wherein the source electrode and the drain electrode have corner portions on both sides of an end portion of the channel.

[30] The semiconductor element according to claim 22, wherein the semiconductor element is a thin film transistor or a thin film diode.

[31] The semiconductor element according to claim 23, wherein the semiconductor element is a thin film transistor or a thin film diode.

[32] The semiconductor element according to claim 24, wherein the semiconductor element is a thin film transistor or a thin film diode.

[33] The semiconductor element according to claim 25, wherein the semiconductor element is a thin film transistor or a thin film diode.

[34] The semiconductor element according to claim 26, wherein the semiconductor element is a thin film transistor or a thin film diode.

[35] The semiconductor element according to claim 27, wherein the semiconductor element is a thin film transistor or a thin film diode.

[36] The semiconductor element according to claim 29, wherein the semiconductor element is a thin film transistor or a thin film diode.

[37] A circuit board comprising the semiconductor element according to [22].

38. A circuit board comprising the semiconductor element according to claim 23.

[39] A circuit board comprising the semiconductor element according to claim 24.

40. A circuit board comprising the semiconductor element according to claim 25.

41. A circuit board comprising the semiconductor element according to claim 26.

[42] A circuit board comprising the semiconductor element according to claim 27.

[43] A circuit board comprising the semiconductor element according to [29].

[44] A circuit board having a gate wiring, a source wiring, and a semiconductor element on a substrate, the circuit board constituting a display device or an imaging device, wherein the semiconductor element in the display region or the imaging region is a gate Including a configuration arranged on a parallel line group extending in the extending direction of the wiring and the Z or source wiring, and including a configuration arranged on the semiconductor element force of the non-display region or the non-imaging region. Feature circuit board.

[45] A circuit board having a gate wiring, a source wiring, and a semiconductor element on a substrate, the circuit board constituting a display device or an imaging device, wherein the semiconductor element in the display region or the imaging region is a gate Including a structure arranged on a group of parallel lines extending in the extending direction of the wiring and Z or source wiring, and the semiconductor element in the non-display area or the non-imaging area is a distance of an integer of the interval between the parallel lines A circuit board comprising a configuration arranged on a straight line group determined by:

46. The circuit board according to claim 44, wherein the circuit board includes a configuration in which the semiconductor elements in the display area or the imaging area are arranged on a group of parallel lines extending in the extending direction of the gate wiring.

47. The circuit board according to claim 45, wherein the circuit board includes a configuration in which the semiconductor elements in the display area or the imaging area are arranged on a group of parallel lines extending in the extending direction of the gate wiring.

[48] A plurality of semiconductor elements arranged in the display region or the imaging region are arranged at each intersection of the gate wiring and the source wiring,

The plurality of semiconductor elements arranged at the intersection include a configuration arranged on one parallel line group extending in the extending direction of the gate wiring or the source wiring.

45. The circuit board according to claim 44, wherein:

[49] A plurality of semiconductor elements arranged in the display region or the imaging region are arranged at each intersection of the gate wiring and the source wiring,

46. The circuit board according to claim 45, wherein:

50. The circuit board according to claim 44, wherein the semiconductor element disposed in the display area is a thin film transistor.

51. The circuit board according to claim 45, wherein the semiconductor element disposed in the display area is a thin film transistor.

52. The circuit board according to claim 44, wherein the semiconductor element disposed in the non-display area is a thin film diode.

53. The circuit board according to claim 45, wherein the semiconductor element disposed in the non-display area is a thin film diode.

54. An electronic device comprising a circuit board manufactured using the circuit board manufacturing method according to claim 20.

[55] An electronic device comprising the circuit board according to [37].

56. An electronic device comprising the circuit board according to claim 38.

[57] An electronic device comprising the circuit board according to [39].

58. An electronic device comprising the circuit board according to claim 40.

59. An electronic device comprising the circuit board according to claim 41.

[60] An electronic device comprising the circuit board according to [42].

[61] An electronic device comprising the circuit board according to [43].

62. An electronic device comprising the circuit board according to claim 44. 63. An electronic device comprising the circuit board according to claim 45.