JP2008058455A - Method for manufacturing active matrix substrate and method for manufacturing liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the number of steps of combining a dry process and photolithographic etching. <P>SOLUTION: The method comprises: a first step of forming wirings of a grid pattern on a substrate P; a second step of forming a layered part comprising an insulating film and a semiconductor film on a part of the wiring; a third step of forming a transparent insulating film 12 covering the wiring and the layered part; and a fourth step of forming a pixel electrode that is electrically connected to the wiring through the semiconductor film on the transparent insulating film 12. The fourth step comprises: a step of forming a resist 59 on the transparent insulating film 12, the resist 59 corresponding to a connection electrode that penetrates the transparent insulating film 12 to electrically connect the pixel electrode and the semiconductor film, to a pixel region where the pixel electrode is formed, and to a segmenting part that segments the pixel region in each pixel; and a step of exposing the resist 59 in such a manner that a resist corresponding to the connection electrode is exposed with a first energy quantity, a rest corresponding to the pixel region is exposed with a second energy quantity smaller than the first energy quantity, and a resist corresponding to the segmenting part is not exposed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing an active matrix substrate and a method for manufacturing a liquid crystal display device.

  With the spread of portable devices such as notebook computers and mobile phones, thin and light liquid crystal display devices are widely used. In this type of liquid crystal display device or the like, a liquid crystal layer is sandwiched between an upper substrate and a lower substrate.

  The lower substrate is a glass substrate, a gate scanning electrode and a source electrode wired so as to cross each other on the glass substrate, a drain electrode similarly wired on the glass substrate, and a pixel connected to the drain electrode An electrode (ITO), an insulating layer interposed between the gate scanning electrode and the source electrode, and a TFT (Thin Film Transistor) made of a thin film semiconductor are included.

  In the formation of each metal wiring on the lower substrate, for example, as shown in Patent Document 1, a method of repeating a process combining a dry process and photolithography etching a plurality of times is used.

  In the technique described in Patent Document 1, at least four photolithography steps are required for forming a gate wiring, a capacitor line, an element, a source / drain line, and a pixel electrode.

  Therefore, in Patent Document 2, the gate line, the capacitor line, and the source line divided at the intersection with the gate line are formed in the same layer, and the divided source lines are electrically connected in different layers, A technique for reducing the photolithography process to three times is disclosed.

  In addition, since an insulating film is only interposed between the pixel electrode and the gate wiring (or source wiring, hereinafter referred to as transistor wiring), parasitic capacitance is generated between the wiring and the pixel electrode via the insulating film. In order to prevent the loss and delay of signals applied to these wirings, the pixel electrode is designed to be shifted inward from the gate wiring and the source wiring. As a result, the pixel electrode area is reduced. This is a cause of a decrease in aperture ratio.

  Therefore, conventionally, a photosensitive transparent resin is interposed between the pixel electrode and the transistor wiring in order to reduce the parasitic capacitance.

In this configuration, since the parasitic capacitance is reduced due to the presence of the photosensitive transparent resin, it is not necessary to design the pixel electrode inward from the gate wiring and the source wiring, and a decrease in the aperture ratio can be suppressed.
Japanese Patent No. 3261699 JP 2006-065021 A

  However, the following problems exist in the conventional technology as described above.

  Even by patterning the pixel electrode on the photosensitive transparent resin, two photolithography processes are required. Specifically, the transparent resin is removed in a first photolithography process for at least the contact portion between the pixel electrode and the drain line. Then, after forming a transparent pixel electrode by sputtering or a droplet discharge method, a second photolithography process is performed to form a slit pattern for vertical alignment and a fine slit pattern for partitioning the pixels on the transparent pixel electrode. Process and dry etching are performed.

  Therefore, even if the technique described in Patent Document 2 is used, five photolithography processes are required.

  This photolithography process requires large-scale equipment such as a vacuum apparatus and a complicated process. The material use efficiency is about several percent, and most of the material must be discarded, and the manufacturing cost is high.

  Therefore, liquid crystal display devices and the like that are required to reduce the product cost are required to further reduce the number of processes combining the dry process and photolithography etching from the viewpoint of reducing the manufacturing cost and improving the productivity. ing.

  The present invention has been made in consideration of the above points, and provides an active matrix substrate manufacturing method and a liquid crystal display manufacturing method capable of reducing the number of processes combining a dry process and photolithography etching. The purpose is to do.

  In order to achieve the above object, the present invention employs the following configuration.

  The manufacturing method of the active matrix substrate of the present invention includes a first step of forming a lattice pattern wiring on the substrate, and a second step of forming a laminated portion made of an insulating film and a semiconductor film on a part of the wiring. A third step of forming a transparent insulating film covering the wiring and the stacked portion; and a fourth step of forming a pixel electrode electrically connected to the wiring through the semiconductor film on the transparent insulating film. And in the fourth step, a connection electrode that penetrates the transparent insulating film to electrically connect the pixel electrode and the semiconductor film, a pixel region in which the pixel electrode is formed, and each pixel Forming on the transparent insulating film a resist corresponding to a partition portion that partitions the pixel region, and exposing the resist corresponding to the connection electrode of the resist with a first energy amount. , Corresponding to the pixel area The resist against exposed by the second amount of energy smaller than the first amount of energy, is characterized in that it comprises the step of a non-exposure to the resist corresponding to the compartment portion.

  Therefore, in the manufacturing method of the active matrix substrate of the present invention, the resist exposed with the first energy amount and the transparent insulating film are removed by developing and etching the resist exposed with the first energy amount and the second energy amount. Thus, a through-hole for forming a connection electrode through the transparent insulating film can be formed, and a part of the resist exposed with the second energy amount can be removed. In the present invention, the remaining portions of the resist exposed with the second energy amount are removed by subsequent etching, and the partition walls can be formed corresponding to the pixel regions by the unexposed partition portions.

  Therefore, in the present invention, it is possible to form a connection electrode and a pixel electrode electrically connected to the semiconductor film by this connection electrode on the transparent insulating film by a single photolithography process, thereby reducing manufacturing cost and production. It can contribute to the improvement of sex.

  Further, in the present invention, since the distance between the pixel electrode and the wiring can be set large by the transparent insulating resin, it becomes possible to reduce the parasitic capacitance generated between the pixel electrode and the wiring, and the pixel electrode is placed on the upper part of the wiring. Thus, the aperture ratio can be improved.

  In the present invention, a procedure in which the third step includes a step of providing a liquid repellent layer on the surface of the transparent insulating film can be suitably employed.

  As a result, in the present invention, it becomes possible to impart liquid repellency to the surface of the partition portion where the surface is not removed. Therefore, when the liquid droplet containing the pixel electrode forming material is applied onto the transparent insulating film, the liquid repellency is obtained. The pixel electrode can be formed by patterning in the pixel region due to the contrast between the property and the lyophilic property.

  As a method for forming this liquid repellent layer, a method of forming on the transparent insulating film by plasma treatment using a gas having a fluorine component, or a liquid material having a fluorine component is applied on the transparent insulating film. The method to do can be used suitably.

  In the present invention, in the fourth step, a procedure using a mask that transmits exposure light with the first energy amount and the second energy amount can be suitably employed according to the exposure area of the resist.

  Accordingly, in the present invention, it is possible to expose the resist with different energy amounts without using a plurality of masks and without performing exposure light irradiation a plurality of times, which can contribute to an improvement in productivity.

  Moreover, in this invention, it has the process of forming the conductive layer which electrically connects the said divided | segmented wiring on the said laminated | stacked part by dividing either wiring of a 1st direction or a 2nd direction in an intersection part. A procedure can also be suitably employed.

  Thereby, in the present invention, since the contact of the wiring of the lattice pattern is avoided, it becomes possible to simultaneously form these wirings on the same surface, it is possible to reduce the processing combined with the dry process and photolithography etching, Manufacturing cost can be reduced and yield can be improved. Further, one of the divided wirings can be electrically connected by a conductive layer.

  As the wiring, a configuration in which a source line, a gate line, and a capacitor line extending substantially linearly along the gate line are provided, and the source line is divided at the intersecting portion can be suitably employed.

  Therefore, in the present invention, since the contact of these wirings is avoided, these wirings can be formed on the same plane simultaneously (in the same process).

  As the first step, a procedure including a step of disposing a conductive material by a droplet discharge method can be suitably employed.

  Thereby, in this invention, it becomes possible to reduce further the process which combined the dry process and the photolitho etching.

  The method for manufacturing a liquid crystal display device of the present invention is a method for manufacturing a liquid crystal display device having an active matrix substrate, wherein the active matrix substrate is manufactured by the method for manufacturing an active matrix substrate described above. To do.

  Therefore, the method for manufacturing a liquid crystal display device of the present invention can contribute to a reduction in manufacturing cost and an improvement in productivity.

  Further, in the present invention, the resist is formed corresponding to a liquid crystal alignment pattern provided in a region surrounded by the partition portion, and in the fourth step, the resist corresponding to the liquid crystal alignment pattern is A procedure of non-exposure with the partitioning part can also be suitably employed.

  Accordingly, in the present invention, the liquid crystal alignment pattern can be formed in the same process as the pixel electrode.

  Embodiments of an active matrix substrate manufacturing method and a liquid crystal display manufacturing method according to the present invention will be described below with reference to FIGS.

In each drawing used for the following description, the scale of each member is appropriately changed to make each member a recognizable size.
<Active matrix substrate>
FIG. 1 is an enlarged view of a part of an active matrix substrate according to the present invention.

  On the active matrix substrate 20, gate wirings (gate lines) 40 and source wirings (source lines) 42 wired in a lattice pattern (lattice pattern) are provided. That is, the plurality of gate wirings 40 are formed to extend in the X direction (first direction), and the source wirings 42 are formed to extend in the Y direction (second direction).

  A gate electrode 41 is connected to the gate wiring 40, and a TFT (switching element) 30 is disposed on the gate electrode 41 via an insulating layer. On the other hand, a source electrode 43 is connected to the source wiring 42, and one end of the source electrode 43 is connected to the TFT 30.

  A pixel electrode 45 is disposed in a region surrounded by the gate wiring 40 and the source wiring 42, more specifically, a pixel region surrounded by a pixel bank GB formed in a lattice shape and partitioned for each pixel. It is connected to the TFT 30 through the electrode 10, the lead wiring 11, and the drain electrode 44. The connection electrode 10 connects the lead wiring 11 and the pixel electrode 45.

  Further, in the region surrounded by the pixel bank GB, a plurality of vertical alignment slits (actually protrusions) HS are arranged in parallel and spaced apart from each other at substantially the same height as the pixel bank GB.

  The routing wiring 11 has one end side electrically connected to the drain electrode 44 and extends in the Y-axis direction, and the other end side extends from the source wiring 42 in the X-axis direction and protrudes through the end of the wiring 13 and the insulating film. Arranged in an opposed state.

  On the active matrix substrate 20, a capacitor line 46 is wired so as to be substantially parallel to the gate wiring 40.

  Note that the gate wiring 40, the gate electrode 41, the source wiring 42, and the capacitor line 46 are formed on the same surface.

  The source line 42 is divided at an intersection 56 between the gate line 40 and the capacitor line 46. The end of the source line 42 divided by the gate line 40 is connected to the lower end of the through electrode 14 that penetrates the insulating film. The upper end portions of these through electrodes 14 are connected to a conductive layer 49 across an intersecting portion 56 with an insulating film interposed between them and the gate wiring 40. Similarly, the end of the source wiring 42 divided by the capacitor line 46 is connected to the lower end of the through electrode 15 that penetrates the insulating film. The upper end portions of the through electrodes 15 are connected to the conductive layer 49 across the crossing portion 56 with an insulating film interposed between them and the capacitor line 46. Further, the source electrode 43 is electrically connected to the source wiring 42 via the connection portion 50, the conductive layer 49, and the through electrode 14.

  FIG. 2 is an equivalent circuit diagram of the active matrix substrate 20 when used in a liquid crystal display device.

  When the active matrix substrate 20 is used in a liquid crystal display device, a plurality of pixels 100a are configured in a matrix in the image display area. Each of these pixels 100 a is formed with a pixel switching TFT 30, and a source wiring 42 for supplying pixel signals S 1, S 2,..., Sn is electrically connected to the source of the TFT 30 via a source electrode 43. Has been. The pixel signals S1, S2,..., Sn supplied to the source wiring 42 may be supplied line-sequentially in this order, or may be supplied for each group to a plurality of adjacent source wirings 42. Good.

  A gate wiring 40 is electrically connected to the gate of the TFT 30 via a gate electrode 41. The scanning signals G1, G2,..., Gm are applied to the gate wiring 40 in a line-sequential order in this order at a predetermined timing.

  The pixel electrode 45 is formed on the transparent insulating film 12 covering the TFT 30 and the like (see FIG. 21), and is electrically connected to the drain of the TFT 30 via the drain electrode 44. Then, by turning on the TFT 30 as a switching element for a certain period, the pixel signals S1, S2,..., Sn supplied from the source wiring 42 are written to each pixel at a predetermined timing. The pixel signals S1, S2,..., Sn written in the liquid crystal through the pixel electrode 45 in this way are held for a certain period with the counter electrode 121 of the counter substrate 120 shown in FIG.

  In order to prevent the held pixel signals S1, S2,..., Sn from leaking, the storage capacitor 48 is provided in parallel with the liquid crystal capacitor formed between the pixel electrode 45 and the counter electrode 121 by the capacitor line 46. It has been added. For example, the voltage of the pixel electrode 45 is held by the storage capacitor 48 for a time that is three orders of magnitude longer than the time when the source voltage is applied. Thereby, the charge retention characteristics are improved, and the liquid crystal display device 100 with a high contrast ratio can be realized.

Note that a charge is also held between the capacitor line 46 and the lead wiring 11 to form a capacitor. However, a reset is made by applying a voltage from the source line 42 and injecting a new charge from the lead wiring 11. Is done.
<Method for manufacturing active matrix substrate>
Next, a method for manufacturing the active matrix substrate 20 will be described with reference to FIGS.

  The active matrix substrate 20 is manufactured by a first step of forming a grid pattern wiring on the substrate P and a second step of forming the stacked portion 35, the TFT 30, the pixel electrode 45, and the like.

Hereinafter, each process will be described in detail.
(First step: wiring formation)
FIG. 3 and FIG. 4 are diagrams for explaining the wiring forming process which is the first process. FIGS. 3B, 3C, and 4B are cross-sectional views taken along the line AA ′ in FIGS. 3A and 4A, respectively.

  Various materials such as glass, quartz glass, Si wafer, plastic film, and metal plate can be used as the substrate P on which the wiring of the lattice pattern such as the gate wiring 40 and the source wiring 42 is formed. Also included are those in which a semiconductor film, a metal film, a dielectric film, an organic film or the like is formed as a base layer on the surface of these various material substrates.

  First, as shown in FIG. 3C, the bank 51 made of an insulating organic resin is formed on the substrate P shown in FIG. The bank is for arranging wiring ink, which will be described later, at a predetermined position on the substrate P.

  Specifically, as shown in FIG. 3A, a bank 51 having a plurality of openings 52, 53, 54, 55 corresponding to the positions where the wiring of the lattice pattern is formed on the upper surface of the cleaned substrate P is photo-photographed. It forms based on the lithography method.

As a material of the bank 51, for example, a polymer material such as an acrylic resin, a polyimide resin, an olefin resin, or a melamine resin is used. The bank 51 is subjected to a liquid repellent treatment so that the wiring pattern ink can be satisfactorily disposed in the openings 52, 53, 54, and 55. As the liquid repellent treatment, CF ₄ plasma treatment or the like (plasma treatment using a gas having a fluorine component) is performed. Instead of the CF ₄ plasma treatment or the like, the material of the bank 51 itself may be filled with a liquid repellent component (fluorine group or the like) in advance.

  The openings 52, 53, 54, and 55 formed by the bank 51 correspond to the lattice pattern wiring such as the gate wiring 40 and the source wiring 42. That is, by arranging wiring ink in the openings 52, 53, 54, and 55 of the bank 51, a grid pattern wiring such as the gate wiring 40 and the source wiring 42 is formed.

  Specifically, the openings 52 and 53 formed so as to extend in the X direction correspond to the formation positions of the gate wiring 40 and the capacitor line 46, respectively. An opening 54 corresponding to the formation position of the gate electrode 41 is connected to the opening 52 corresponding to the formation position of the gate wiring 40. The opening 55 formed so as to extend in the Y direction corresponds to the position where the source wiring 42 is formed. The opening 55 is connected to an opening 13 a corresponding to the position where the wiring 13 is formed. The opening 55 extending in the Y direction is formed so as to be divided at the intersection 56 so as not to intersect with the openings 52 and 53 extending in the X direction.

  Next, wiring ink containing conductive fine particles is discharged and arranged in the openings 52, 53, 54, and 55 by a droplet discharge device IJ described later, and the gate wiring 40 is formed on the substrate as shown in FIG. In addition, a grid pattern wiring composed of the source wiring 42 and the like is formed.

  The wiring ink is composed of a dispersion in which conductive fine particles are dispersed in a dispersion medium, or a solution in which an organic silver compound or silver oxide nanoparticles are dispersed in a solvent (dispersion medium). As the conductive fine particles, for example, metal fine particles such as gold, silver, copper, tin, lead and the like, oxides thereof, and fine particles of conductive polymer or superconductor are used. These conductive fine particles can be used by coating the surface with an organic substance or the like in order to improve dispersibility.

  The particle diameter of the conductive fine particles is preferably 1 nm or more and 0.1 μm or less. If it is larger than 0.1 μm, there is a risk of clogging in the nozzles of the droplet discharge head described later. On the other hand, if it is smaller than 1 nm, the volume ratio of the coating agent to the conductive fine particles becomes large, and the ratio of the organic matter in the obtained film becomes excessive.

  The dispersion medium is not particularly limited as long as it can disperse the conductive fine particles and does not cause aggregation. For example, in addition to water, alcohols such as methanol, ethanol, propanol, butanol, n-heptane, n-octane, decane, dodecane, tetradecane, toluene, xylene, cymene, durene, indene, dipentene, tetrahydronaphthalene, decahydro Hydrocarbon compounds such as naphthalene and cyclohexylbenzene, ethylene glycol dimethyl ether, ethylene glycol diethyl ether, ethylene glycol methyl ethyl ether, diethylene glycol dimethyl ether, diethylene glycol diethyl ether, diethylene glycol methyl ethyl ether, 1,2-dimethoxyethane, bis (2- Methoxyethyl) ether, ether compounds such as p-dioxane, propylene carbonate, γ- Butyrolactone, N- methyl-2-pyrrolidone, dimethylformamide, dimethyl sulfoxide, can be exemplified polar compounds such as cyclohexanone. Of these, water, alcohols, hydrocarbon compounds, and ether compounds are preferred from the viewpoints of fine particle dispersibility and dispersion stability, and ease of application to the droplet discharge method (inkjet method). More preferred dispersion media include water and hydrocarbon compounds.

  The surface tension of the dispersion liquid of conductive fine particles is preferably in the range of 0.02 N / m or more and 0.07 N / m or less, for example. When the liquid is ejected by the ink jet method, if the surface tension is less than 0.02 N / m, the wettability of the ink composition to the nozzle surface increases, and thus flight bending tends to occur, exceeding 0.07 N / m. Since the meniscus shape at the nozzle tip is not stable, it becomes difficult to control the discharge amount and the discharge timing. In order to adjust the surface tension, a small amount of a surface tension regulator such as a fluorine-based, silicone-based, or nonionic-based material may be added to the dispersion within a range that does not significantly reduce the contact angle with the substrate. The nonionic surface tension modifier improves the wettability of the liquid to the substrate, improves the leveling property of the film, and helps prevent the occurrence of fine irregularities in the film. The surface tension modifier may contain an organic compound such as alcohol, ether, ester, or ketone, if necessary.

The viscosity of the dispersion is preferably, for example, from 1 mPa · s to 50 mPa · s.
When the liquid material is ejected as droplets using the inkjet method, if the viscosity is less than 1 mPa · s, the nozzle periphery is easily contaminated by the outflow of the ink, and if the viscosity is greater than 50 mPa · s, the nozzle hole The clogging frequency of the liquid becomes high, and it becomes difficult to smoothly discharge the droplets.

  After the wiring ink is discharged onto the substrate P, a drying process and a baking process are performed as necessary to remove the dispersion medium.

  The drying process can be performed, for example, by a heating process using a normal hot plate or an electric furnace that heats the substrate P. For example, heating at 180 ° C. is performed for about 60 minutes.

  The treatment temperature for the calcination treatment is appropriately determined in consideration of the boiling point (vapor pressure) of the dispersion medium, thermal behavior such as fine particle dispersibility and oxidation, the presence and amount of coating agent, and the heat resistance temperature of the substrate. The For example, it is necessary to bake at about 250 ° C. in order to remove the coating agent made of organic matter.

  By such drying and baking treatment, electrical contact between the conductive fine particles is ensured and converted to a conductive film.

  Note that a metal protective film 47 may be formed on the wiring such as the gate wiring 40 and the source wiring 42. The metal protective film 47 is a thin film for suppressing an (electro) migration phenomenon or the like of a conductive film made of silver, copper, or the like. As a material for forming the metal protective film 47, nickel is preferable. The metal protective film 47 made of nickel is also formed on the substrate P by the droplet discharge method.

  As a result of the above steps, a layer composed of the bank 51 and the wiring of the lattice pattern is formed on the substrate P as shown in FIG.

By the way, as a discharge technique of the droplet discharge method, there are a charge control method, a pressure vibration method, an electromechanical conversion method, an electrothermal conversion method, an electrostatic suction method, and the like. In the charge control method, a charge is applied to a material by a charging electrode, and the flight direction of the material is controlled by a deflection electrode and discharged from a nozzle. In addition, the pressure vibration method is a method in which an ultra-high pressure of, for example, about 30 kg / cm ² is applied to the material and the material is discharged to the nozzle tip side. When no control voltage is applied, the material moves straight from the nozzle. When discharged and a control voltage is applied, electrostatic repulsion occurs between the materials, and the materials are scattered and are not discharged from the nozzle. The electromechanical conversion method utilizes the property that a piezoelectric element (piezoelectric element) is deformed by receiving a pulse-like electric signal. The piezoelectric element is deformed through a flexible substance in a space where material is stored. Pressure is applied, and the material is extruded from this space and discharged from the nozzle.

  In the electrothermal conversion method, a material is rapidly vaporized by a heater provided in a space in which the material is stored to generate bubbles, and the material in the space is discharged by the pressure of the bubbles. In the electrostatic attraction method, a minute pressure is applied in a space in which the material is stored, a meniscus of the material is formed on the nozzle, and an electrostatic attractive force is applied in this state before the material is drawn out. In addition to this, techniques such as a system that uses a change in the viscosity of a fluid due to an electric field and a system that uses a discharge spark are also applicable. The droplet discharge method has an advantage that the use of the material is less wasteful and a desired amount of the material can be accurately disposed at a desired position. The amount of one drop of the liquid material (fluid) discharged by the droplet discharge method is, for example, 1 to 300 nanograms.

  For example, a droplet discharge device IJ shown in FIG. 5 is used as the droplet discharge device IJ used when forming the wiring of the lattice pattern.

  The droplet discharge device (inkjet device) IJ discharges (drops) droplets from the droplet discharge head onto the substrate P. The droplet discharge head 301, the X-direction drive shaft 304, and the Y-direction A guide shaft 305, a control device CONT, a stage 307, a cleaning mechanism 308, a base 309, and a heater 315 are provided. The stage 307 supports the substrate P on which ink (liquid material) is provided by the droplet discharge device IJ, and includes a fixing mechanism (not shown) that fixes the substrate P at a reference position.

  The droplet discharge head 301 is a multi-nozzle type droplet discharge head provided with a plurality of discharge nozzles, and the longitudinal direction and the Y-axis direction are made to coincide. The plurality of ejection nozzles are provided on the lower surface of the droplet ejection head 301 in the Y axis direction at regular intervals. From the discharge nozzle of the droplet discharge head 301, the ink containing the conductive fine particles described above is discharged onto the substrate P supported by the stage 307.

  An X direction drive motor 302 is connected to the X direction drive shaft 304. The X-direction drive motor 302 is a stepping motor or the like, and rotates the X-direction drive shaft 304 when an X-direction drive signal is supplied from the control device CONT. When the X-direction drive shaft 304 rotates, the droplet discharge head 301 moves in the X-axis direction.

  The Y-direction guide shaft 305 is fixed so as not to move with respect to the base 309. The stage 307 includes a Y direction drive motor 303. The Y direction drive motor 303 is a stepping motor or the like, and moves a stage 307 in the Y direction when a drive signal in the Y direction is supplied from the control device CONT.

  The control device CONT supplies a droplet discharge control voltage to the droplet discharge head 301. Further, a drive pulse signal for controlling the movement of the droplet discharge head 301 in the X direction is supplied to the X direction drive motor 302, and a drive pulse signal for controlling the movement of the stage 307 in the Y direction is supplied to the Y direction drive motor 303.

  The cleaning mechanism 308 is for cleaning the droplet discharge head 301. The cleaning mechanism 308 includes a Y-direction drive motor (not shown). The cleaning mechanism moves along the Y-direction guide shaft 305 by driving the Y-direction drive motor. The movement of the cleaning mechanism 308 is also controlled by the control device CONT.

  Here, the heater 315 is means for heat-treating the substrate P by lamp annealing, and performs evaporation and drying of the solvent contained in the liquid material applied on the substrate P. The heater 315 is also turned on and off by the control device CONT.

  The droplet discharge device IJ discharges droplets onto the substrate P while relatively scanning the droplet discharge head 301 and the stage 307 that supports the substrate P. Here, in the following description, the X direction is a scanning direction, and the Y direction orthogonal to the X direction is a non-scanning direction.

  Accordingly, the discharge nozzles of the droplet discharge head 301 are provided side by side at regular intervals in the Y direction, which is the non-scanning direction. In FIG. 5, the droplet discharge head 301 is arranged at a right angle to the traveling direction of the substrate P, but the angle of the droplet discharging head 301 is adjusted so as to intersect the traveling direction of the substrate P. It may be. In this way, the pitch between the nozzles can be adjusted by adjusting the angle of the droplet discharge head 301. Further, the distance between the substrate P and the nozzle surface may be arbitrarily adjusted.

  FIG. 6 is a cross-sectional view of the droplet discharge head 301.

  The droplet discharge head 301 is provided with a piezo element 322 adjacent to a liquid chamber 321 that stores a liquid material (such as wiring ink). The liquid material is supplied to the liquid chamber 321 via a liquid material supply system 323 including a material tank that stores the liquid material.

  The piezo element 322 is connected to a drive circuit 324, and a voltage is applied to the piezo element 322 via the drive circuit 324 to deform the piezo element 322, whereby the liquid chamber 321 is deformed and the liquid material is discharged from the nozzle 325. Is discharged.

In this case, the amount of distortion of the piezo element 322 is controlled by changing the value of the applied voltage. Further, the strain rate of the piezo element 322 is controlled by changing the frequency of the applied voltage. Since the droplet discharge by the piezo method does not apply heat to the material, it has an advantage of hardly affecting the composition of the material.
(2nd process: Laminate part formation)
7-15 is a figure explaining the lamination | stacking part formation process which is a 2nd process. 7B to FIG. 8B are cross-sectional views taken along line AA ′ in FIG. 7A to FIG. 8A, respectively, and FIG. It is sectional drawing which follows the BB 'line in a).

  In the second step, the laminated portion 35 made of the insulating film 31 and the semiconductor film (contact layer 33, active layer 32) is formed at a predetermined position on the layer made of the bank 51 and the wiring of the lattice pattern.

  First, the insulating film 31, the active layer 32, and the contact layer 33 are continuously formed on the entire surface of the substrate P by plasma CVD. Specifically, as shown in FIG. 7, a silicon nitride film is used as the insulating film 31, an amorphous silicon film is used as the active layer 32, and an n + type silicon film is used as the contact layer 33 by changing the source gas and plasma conditions. Form.

  Next, as shown in FIG. 8, resists 58 (58 a to 58 b) are arranged at predetermined positions using photolithography. As shown in FIG. 8A, this resist is provided at a crossing 56 between the gate wiring 40 and the source wiring 42 and the resist 58a provided across the gate electrode 41 and the crossing 56 between the capacitor line 46 and the source wiring 42. And a resist 58c provided in a region excluding the panel peripheral circuit portion so as to surround the resists 58a and 58b outside the region of the intersecting portion 56.

  For these resists 58a to 58c, the same material as that of the bank 51 was applied on the entire surface of the substrate P by a technique such as spin coating, and then the transmittance of exposure light was adjusted according to the shape of the resists 58a to 58c. After batch exposure using a mask, development and dry etching are performed, thereby patterning into a predetermined shape and a predetermined thickness.

  More specifically, as shown in FIG. 8B, the resist 58a is formed at positions corresponding to the openings 14a, the source electrode 43, and the drain electrode 44 formed so as to penetrate the positions corresponding to the through electrodes 14, respectively. Openings 43a and 44a formed through, channel part C separating source electrode 43 and drain electrode 44 (openings 43a and 44a), opening 49a formed at a position corresponding to conductive layer 49, conductive layer 49, the opening 50a formed at a position corresponding to the connection portion 50 between the source electrode 43, the opening 11a formed at a position corresponding to the routing wiring 11, and around these openings 11a, 43a, 44a, 49a. For example, it has the wall part (non-exposure part) 9a formed in width about 1-10 micrometers.

  Similarly, as illustrated in FIG. 8C, the resist 58 b includes an opening 15 a formed so as to penetrate a position corresponding to the through electrode 15, an opening 49 a formed at a position corresponding to the conductive layer 49, Around the opening 49a, there is a wall portion (non-exposed portion) 9b formed with a width of about 1 to 10 μm, for example.

  The openings 14 a, 15 a, 43 a, 44 a formed through the above-described openings are subjected to full exposure to irradiate the exposure light transmitted through the mask with the first energy amount without being substantially shielded from light. After performing, it is formed by development and dry etching. In addition, the openings 11a, 49a, 50a in which the resist remains with a thickness thinner than the walls 9a, 9b, and the resist 58c are smaller than the first energy amount with respect to these exposure regions (for example, approximately Half) formed by developing and etching after half exposure (halftone exposure) of irradiating exposure light transmitted through the mask with the second energy amount. In this case, the mask is meshed at a position where it is transmitted with the second energy amount, and a part of the exposure light is shielded, so that the energy amount of the transmitted exposure light is a predetermined value (second energy amount). Reduced to

  The walls 11a, 9b and the channel portion C, which are formed thicker than the openings 11a, 49a, 50a, and the resist 58c, are developed and etched by making the exposure light shielded by a mask. The film is formed to a predetermined thickness without being removed.

  In this manner, resists 58a to 58c having through portions and two types of thicknesses (three types of thicknesses including through portions where the resist thickness is zero) are formed by one dry process and photolithography etching. The

  Subsequently, as shown in FIG. 9A, droplets containing a metal material such as nickel (Ni) or cobalt (Co) are applied to the openings 43a and 44a using the droplet discharge device IJ. Then, a barrier layer 70 for the source electrode 43 and the drain electrode 44 is formed by performing a drying / firing process. By such drying and baking treatment, electrical contact between the conductive fine particles is ensured and converted to a conductive film.

  The drying process can be performed, for example, by a heating process using a normal hot plate or an electric furnace that heats the substrate P. For example, heating at 180 ° C. is performed for about 60 minutes.

  The treatment temperature for the firing treatment and the treatment temperature is appropriately determined in consideration of the boiling point (vapor pressure) of the dispersion medium, the thermal behavior such as fine particle dispersibility and oxidation, the presence and amount of the coating agent, the heat resistance temperature of the substrate, etc. Is done. For example, it is necessary to bake at about 250 ° C. in order to remove the coating agent made of organic matter.

  9 to 15, (a) in each drawing is a cross-sectional view taken along the line AA ′ in FIG. 8 (a), and (a) in each drawing is B- in FIG. 8 (a). It is sectional drawing which follows a B 'line.

  Next, as shown in FIGS. 10A and 10B, dry etching is performed using the resists 58a to 58c and the barrier layer 70 as a mask to expose the insulating film 31, the active layer 32, and the contact exposed in the openings 14a and 15a. Layer 33 is removed.

  Subsequently, anisotropic ashing is performed, and as shown in FIGS. 11A and 11B, resists 58a, 58b and resist 58c exposed in the openings 11a, 49a, and 50a formed by half exposure are formed. Remove. Thereby, the resists of the wall portions 9a and 9b and the channel portion C are also lowered.

  Next, dry etching is performed, and as shown in FIGS. 12A and 12B, using the walls 9a and 9b and the channel C as a mask, the active layer 32 and the contact exposed in the area where the resist is removed. The layer 33 is removed, and the insulating film 31 is exposed in the area.

  Thereafter, as shown in FIGS. 13A and 13B, nickel (Ni) is used in the openings 11a, 14a, 15a, 49a, and 50a by using the droplet discharge device IJ as necessary. Barrier layers 71 to 73 similar to the barrier layer 70 are respectively formed by applying droplets containing a metal material such as) and cobalt (Co), and performing drying and baking treatment.

  Note that the barrier layers 71 to 73 are not necessarily required, and may be selectively used as appropriate depending on a material to be used.

  Subsequently, as shown in FIG. 14A, a droplet containing the above-described wiring forming metal material (for example, at least one of Ag, Cu, and Al) is used by using the droplet discharge device IJ. , The region surrounded by the wall 9a and the channel C, and the region surrounded by the wall 9b as shown in FIG. 14B. After the droplets are discharged onto the substrate P, a drying process and a baking process are performed as necessary to remove the dispersion medium. The drying process can be performed, for example, by a heating process using a normal hot plate or an electric furnace that heats the substrate P. For example, heating at 180 ° C. is performed for about 60 minutes.

  The treatment temperature for the calcination treatment is appropriately determined in consideration of the boiling point (vapor pressure) of the dispersion medium, thermal behavior such as fine particle dispersibility and oxidation, the presence and amount of coating agent, and the heat resistance temperature of the substrate. The For example, it is necessary to bake at about 250 ° C. in order to remove the coating agent made of organic matter. By such a drying / firing process, electrical contact between the conductive fine particles is ensured and converted into a conductive film as shown in FIG.

  Next, as shown in FIGS. 15A and 15B, after the remaining resist (resist in the wall portions 9a and 9b and the channel portion C) is completely removed by ashing or the like, FIG. The contact layer 33 is removed by fluorine-containing plasma treatment using the conductive film formed in the process shown in FIG. 5B as a mask, and channel etching between the source electrode 43 and the drain electrode 44 is performed.

  As a result, as shown in FIG. 15B, the through electrode 15 is connected to the divided source wiring 42, intersects the capacitor line 46 through the insulating film 31, and straddles the intersecting portion 56. A conductive layer 49 is formed to connect the two. Similarly, as shown in FIG. 15A, the TFT 30 connected to the source electrode 43 and the drain electrode 44 is formed, and the source electrode 43 is connected to the source via the connection portion 50, the conductive layer 49 and the through electrode 14. An active matrix substrate 20 connected to the wiring 42 and having the drain electrode 44 connected to the routing wiring 11 is formed.

Thus, the active matrix substrate 20 having the TFT 30 is manufactured through two photolithography processes.
(Third step: transparent insulating film formation)
Next, the transparent insulating film 12 is formed.

  16A is a cross-sectional view taken along line A-A ′ in FIG. 1, and FIG. 16B is a cross-sectional view taken along line D-D ′ in FIG. 1.

  As shown in these drawings, first, an insulating film 75 is formed so as to cover the TFT 30 (laminated portion 35), the source electrode 43, the drain electrode 44, the lead wiring 11, the conductive layer 49, and the like. This insulating film 75 is formed of the same material as that of the insulating film 31. In addition, a transparent transparent insulating film material such as a photosensitive organic resin containing photosensitive acrylic resin or Si is applied so as to cover the insulating film 75, and the transparent insulating film 12 is, for example, about 1.5 to 7.5 μm. A film is formed with a thickness.

Further, a liquid repellent layer 76 containing a fluorine component (fluorine atom) is formed on the transparent insulating film 12. As the liquid repellent layer 76, for example, a method of forming a film by performing the above-described CF ₄ plasma treatment or a method of forming a film by applying an organic compound containing a fluorine group or the like can be employed. A film is formed with a thickness.
(Fourth process: pixel electrode formation)
Subsequently, the pixel electrode 45 is formed.

  17 to 21 are sectional views taken along line D-D 'in FIG.

  As shown in FIG. 17, subsequently, a resist 59 is disposed at a predetermined position on the transparent insulating film 12 and the liquid repellent layer 76 by using a photolithography method. The resist 59 also has a transmittance of exposure light after the same material as the resists 58a to 58c is applied over the entire surface of the substrate P (on the transparent insulating film 12 and the liquid repellent layer 76) by a technique such as spin coating. After collectively exposing using a mask adjusted according to the shape of the resist 59, patterning is performed to a predetermined shape and a predetermined thickness by performing development and dry etching.

  More specifically, the resist 59 includes an opening 10a formed through the position corresponding to the connection electrode 10 shown in FIG. 1, an opening 45a formed at a position corresponding to the pixel electrode 45, and the pixel described above. Wall portions (non-exposed portions) 77 and 78 are formed at positions corresponding to the bank GB and the vertical alignment slit HS, respectively. In the wall portion 77 corresponding to the pixel bank GB, the gate wiring 40 and the source line 42 are separated from the pixel electrode 45 through the transparent insulating film 12 and the parasitic capacitance is small. It is arranged at a position overlapping the source line 42 in a plan view. Therefore, a large arrangement area of the pixel electrode 45 can be secured, and a high aperture ratio can be obtained.

  The opening 10a formed through the opening is exposed to exposure light that has passed through the mask with a first energy amount without being substantially shielded from light, and then is developed and dried. It is formed by etching. Further, the opening 45a where the resist remains with a thickness smaller than that of the wall 77 passes through the mask with a second energy amount smaller than (for example, approximately half) the first energy amount with respect to the exposure region. It is formed by developing and etching after half exposure to irradiating exposure light. Also in the mask used in this case, a mesh is applied at a position where light is transmitted with the second energy amount, and a part of the exposure light is shielded, so that the energy amount of the transmitted exposure light is a predetermined value (second energy). Amount).

  The wall 77 formed thicker than the openings 10a and 45a is a non-exposed portion in which the exposure light is shielded by a mask so that the wall 77 has a predetermined thickness without being removed even after development and etching. Formed.

  As described above, the resist 59 having the through portion and two types of thicknesses (three types of thickness including the through portion where the resist thickness is zero) is formed by one dry process and photolithography etching.

  Next, as shown in FIG. 18, dry etching is performed using the resist 59 as a mask, and the liquid repellent layer 76 and the transparent insulating film 12 are removed through the opening 10a.

  Subsequently, anisotropic ashing is performed to remove the resist 59 exposed in the opening 45a formed by the half exposure as shown in FIG. Thereby, the resist of the wall parts 77 and 78 is also lowered.

  Next, dry etching is performed to remove the liquid repellent layer 76 exposed in the area where the resist has been removed using the walls 77 and 78 as a mask as shown in FIG. After the portion is removed, the remaining resist (resist on the wall portions 77 and 78) is completely removed by ashing or the like.

  As a result, the pixel bank GB and the vertical alignment slit HS having the liquid repellent layer 76 on the surface and formed by protruding a part of the transparent insulating film 12 are formed.

  Subsequently, the insulating film 75 exposed in the opening 10a is removed by etching, and the routing wiring 11 is exposed.

  Next, droplets containing a transparent conductive film material such as ITO (Indium Tin Oxide) are applied onto the transparent insulating film 12 by the above-described droplet discharge device IJ.

  Thereby, as shown in FIG. 21, the pixel electrode 45 is formed in the opening 45a surrounded by the pixel bank GB. At this time, since the liquid repellent layer 76 has been removed in advance in the opening 45a, the transparent conductive film material can be applied without hindrance.

  Further, since the liquid repellent layer 76 remains on the surface of the pixel bank GB and the vertical alignment slit HS which are non-exposed portions, the transparent conductive film material applied to the pixel bank GB and the vertical alignment slit HS. Therefore, the fine pixel bank GB and the vertical alignment slit HS are formed without being covered with the transparent conductive film material, and the pixel region surrounded by the pixel bank GB (excluding the vertical alignment slit HS). The pixel electrode 45 can be formed.

  Of the transparent conductive film material, the material applied to the opening 10 a reaches the lower routing wiring 11, thereby causing contact between the routing wiring 11 (that is, the drain electrode 44) and the pixel electrode 45, and capacitance. A capacitive contact with the line 46 is ensured.

  And after discharging a transparent conductive material to the board | substrate P, in order to remove a dispersion medium, a drying process and a baking process are performed as needed. By the drying and firing treatment, electrical contact between the conductive fine particles is ensured and converted into a conductive film.

  As the firing treatment conditions, a firing temperature of 250 ° C. or less is preferable in an oxygen-containing atmosphere, and a firing temperature of 300 ° C. or less is preferred in an atmosphere containing non-oxygen and 0.1% or more of hydrogen.

  The active matrix substrate 20 is manufactured through the above steps.

  As described above, in this embodiment, the pixel electrode 45 and the vertical alignment are formed in one photolithography process by forming the through-hole and the resist 59 having two kinds of thicknesses by performing full exposure and half exposure. The slit for HS can be easily formed. Therefore, in this embodiment, it becomes possible to reduce the photolithographic etching (and dry process) process which requires a large-scale installation and a complicated process compared with the past (for example, technology described in patent documents 2), Further cost reduction and productivity improvement can be realized.

  In the present embodiment, since the full exposure and half exposure are performed using a single mask, the amount of energy applied to the resist can be easily adjusted, and production can be performed compared to the case where a plurality of masks are used. It can contribute to improvement of efficiency.

  In this embodiment, since the transparent insulating film 12 is provided between the pixel electrode 45 and the wiring (gate wiring 40, source wiring 42, and capacitor line 46) to ensure the distance, the parasitic capacitance can be reduced. The loss and delay of signals applied to the gate wiring 40 and the source wiring 42 can be suppressed, and the pixel electrode 45 (pixel bank GB) can be disposed above the gate wiring 40 and the source wiring 42. The aperture ratio can be increased.

  In addition, when forming the gate wiring 40, the source wiring 42, the TFT 30 and the like described above, it is sufficient to perform two photolithographic steps by performing full exposure and half exposure, thereby further reducing cost and improving productivity. realizable.

  In addition, by performing the photolithography process three times including the formation of the TFT 30 and the pixel electrode 45 in this manner, the active matrix substrate 20 that has a high aperture ratio and contributes to cost reduction and productivity can be easily formed. It becomes possible to do.

  In this case, the wall portions 77 and 78 may be removed by ashing or the like after the pixel electrode 45 is formed, and the vertical alignment slit HS is formed in a concave shape instead of a protruding shape.

Further, in this configuration, it is necessary to provide a step of removing the walls 77 and 78, but this step is provided if a configuration in which patterning is performed based on the contrast of the liquid repellent / lyophilic solution as in the above-described embodiment. This is unnecessary and can contribute to the improvement of productivity.
<Electro-optical device>
Next, a liquid crystal display device 100 that is an example of an electro-optical device using the active matrix substrate 20 will be described.

  22 is a plan view of the liquid crystal display device 100 as viewed from the counter substrate side, and FIG. 23 is a cross-sectional view taken along the line H-H ′ of FIG. 22.

  In each drawing used in the following description, the scale is different for each layer and each member so that each layer and each member can be recognized on the drawing.

  22 and 23, in a liquid crystal display device (electro-optical device) 100, a TFT array substrate 110 including an active matrix substrate 20 and a counter substrate 120 are bonded together by a sealing material 152 that is a photo-curable sealing material. The liquid crystal 150 is sealed and held in a region partitioned by the sealing material 152. An alignment film (not shown) is formed on the surface of the TFT array substrate 110 facing the liquid crystal 150 so as to cover the pixel electrode 45 and the vertical alignment slit HS.

  The sealing material 152 is formed in a frame shape that is closed in a region within the substrate surface, does not include a liquid crystal injection port, and does not have a trace sealed with the sealing material.

  A peripheral parting part 153 made of a light shielding material is formed in a region inside the region where the sealing material 152 is formed. A data line driving circuit 201 and a mounting terminal 202 are formed along one side of the TFT array substrate 110 in a region outside the sealing material 152, and the scanning line driving circuit 204 is formed along two sides adjacent to the one side. Is formed. On the remaining one side of the TFT array substrate 110, a plurality of wirings 205 are provided for connecting between the scanning line driving circuits 204 provided on both sides of the image display area. Further, at least one corner portion of the counter substrate 120 is provided with an inter-substrate conductive material 206 for establishing electrical continuity between the TFT array substrate 110 and the counter substrate 120.

  Instead of forming the data line driving circuit 201 and the scanning line driving circuit 204 on the TFT array substrate 110, for example, a TAB (Tape Automated Bonding) substrate on which a driving LSI is mounted and a peripheral portion of the TFT array substrate 110 The terminal group formed in the above may be electrically and mechanically connected via an anisotropic conductive film.

  In the liquid crystal display device 100, the type of liquid crystal 150 to be used, that is, an operation mode such as a TN (Twisted Nematic) mode, a C-TN method, a VA method, an IPS method mode, normally white mode / normally black, etc. Depending on the mode, a retardation plate, a polarizing plate, and the like are arranged in a predetermined direction, but the illustration is omitted here.

  In the case where the liquid crystal display device 100 is configured for color display, for example, red (R), green (G), blue (in the region facing the pixel electrodes of the TFT array substrate 110 in the counter substrate 120. The color filter of B) is formed together with the protective film.

  The electro-optical device using the active matrix substrate 20 can be applied to, for example, an organic EL (electroluminescence) display device.

  An organic EL display device has a configuration in which a thin film containing a fluorescent inorganic and organic compound is sandwiched between a cathode and an anode, and excitons are obtained by injecting electrons and holes into the thin film to excite them. It is an element that generates (exciton) and emits light by utilizing light emission (fluorescence / phosphorescence) when the exciton is recombined.

  Then, on the active matrix substrate 20 having the TFT 30, among the fluorescent materials used for the organic EL display element, materials exhibiting red, green and blue emission colors, that is, a light emitting layer forming material and a hole injection / electron transport layer. A self-luminous full-color organic EL display device can be manufactured by patterning each of the materials for forming the ink.

  Further, the active matrix substrate 20 is a surface conduction electron that utilizes a phenomenon in which electrons are emitted by flowing a current in parallel to the film surface through a PDP (plasma display panel) or a small-area thin film formed on the substrate. The present invention can also be applied to an emission element or the like.

Thus, when manufacturing the liquid crystal display device 100 provided with the active matrix substrate 20 described above, it is possible to contribute to cost reduction and productivity improvement.
<Electronic equipment>
Next, specific examples of the electronic device of the present invention will be described.

  FIG. 24A is a perspective view showing an example of a mobile phone. In FIG. 24A, reference numeral 600 denotes a mobile phone main body, and reference numeral 601 denotes a display unit including the liquid crystal display device 100 of the above embodiment.

  FIG. 24B is a perspective view illustrating an example of a portable information processing apparatus such as a word processor or a personal computer. In FIG. 24B, reference numeral 700 denotes an information processing device, 701 denotes an input unit such as a keyboard, 703 denotes an information processing body, and 702 denotes a display unit including the liquid crystal display device 100 of the above embodiment.

  FIG. 24C is a perspective view showing an example of a wristwatch type electronic device. In FIG. 24C, reference numeral 800 denotes a watch body, and reference numeral 801 denotes a display unit including the liquid crystal display device 100 of the above embodiment.

  As described above, since the electronic apparatus shown in FIGS. 24A to 24C includes the liquid crystal display device 100 of the above-described embodiment, it can be manufactured with reduced cost and improved productivity. is there.

  The present embodiment can also be used for large liquid crystal panels such as televisions and monitors.

  In addition, although the electronic device of this embodiment shall be provided with the liquid crystal display device 100, it can also be set as the electronic device provided with other electro-optical apparatuses, such as an organic electroluminescent display apparatus and a plasma type display apparatus.

  As described above, the preferred embodiments according to the present invention have been described with reference to the accompanying drawings, but the present invention is not limited to the examples. Various shapes, combinations, and the like of the constituent members shown in the above-described examples are examples, and various modifications can be made based on design requirements and the like without departing from the gist of the present invention.

  For example, in the above embodiment, the pixel electrode 45 is patterned with the liquid repellent / lyophilic contrast by forming the liquid repellent layer 76 on the upper surfaces of the pixel bank GB and the vertical alignment slit HS. In addition, the walls 77 and 78 are formed at a height corresponding to the thickness of the pixel electrode 45 and the vertical alignment slit HS, and the walls 77 and 78 are used as partition walls to surround the pixels surrounded by the walls 77 and 78. A film may be formed by applying droplets containing a pixel electrode forming material to the region.

  In the above embodiment, the pixel electrode 45 is formed by the droplet discharge method. However, the present invention is not limited to this, and any coating method that can be patterned by the contrast of the lyophobic / lyophilic liquid is used. Other liquid phase methods such as coating may be used.

  Further, although the active matrix substrate 20 shown in the above embodiment has been described as having a vertical alignment slit HS, the vertical alignment slit HS is not necessarily provided.

It is a partially enlarged view of an active matrix substrate. It is an equivalent circuit diagram of an active matrix substrate. It is a figure which shows the procedure which manufactures an active matrix substrate. It is a figure which shows the procedure following FIG. It is a schematic perspective view of a droplet discharge device. It is sectional drawing of a droplet discharge head. It is a figure which shows the procedure following FIG. It is a figure which shows the procedure following FIG. It is a figure which shows the procedure following FIG. FIG. 10 is a diagram illustrating a procedure following FIG. 9. It is a figure which shows the procedure following FIG. It is a figure which shows the procedure following FIG. It is a figure which shows the procedure following FIG. It is a figure which shows the procedure following FIG. It is a figure which shows the procedure following FIG. It is a figure which shows the procedure following FIG. It is a figure which shows the procedure following FIG. It is a figure which shows the procedure following FIG. It is a figure which shows the procedure following FIG. It is a figure which shows the procedure following FIG. It is a figure which shows the procedure following FIG. It is the top view which looked at the liquid crystal display device from the counter substrate side. It is sectional drawing of a liquid crystal display device. It is a figure which shows the specific example of an electronic device. It is a figure which shows another form of an active matrix substrate.

Explanation of symbols

GB: Pixel bank (partition part), IJ: Droplet ejection device, P: Substrate, 9a, 9b, 77, 78 ... Wall part (non-exposed part), 10: Connection electrode, 12 ... Transparent insulating resin (Transparent insulating film) , 14, 15 through electrodes, 20 active matrix substrate, 30 TFT (switching element), 32 active layer (semiconductor film), 33 contact layer (semiconductor film), 35 laminated portion, 40 gate wiring (Gate line), 42 ... source wiring (source line), 46 ... capacitance line, 49 ... conductive layer, 50 ... connecting portion, 58, 58a to 58c, 59 ... resist, 76 ... liquid repellent layer, 100 ... liquid crystal display device (Electro-optical device), 600 ... mobile phone body (electronic device), 700 ... information processing device (electronic device), 800 ... watch body (electronic device)

Claims (10)

A first step of forming a grid pattern wiring on the substrate;
A second step of forming a laminated portion made of an insulating film and a semiconductor film on a part of the wiring;
A third step of forming a transparent insulating film covering the wiring and the laminated portion;
Forming a pixel electrode electrically connected to the wiring through the semiconductor film on the transparent insulating film;
In the fourth step, a connection electrode that electrically connects the pixel electrode and the semiconductor film through the transparent insulating film, a pixel region in which the pixel electrode is formed, and the pixel region is partitioned for each pixel Forming a resist corresponding to the partitioning portion on the transparent insulating film,
Of the resist, the resist corresponding to the connection electrode is exposed with a first energy amount, and the resist corresponding to the pixel region is exposed with a second energy amount smaller than the first energy amount. A method of manufacturing an active matrix substrate, comprising the step of non-exposure to the resist corresponding to the partition portion. In the manufacturing method of the active-matrix board | substrate of Claim 1,
The method of manufacturing an active matrix substrate, wherein the third step includes a step of providing a liquid repellent layer on the surface of the transparent insulating film. In the manufacturing method of the active-matrix board | substrate of Claim 2,
An active matrix substrate, wherein the liquid repellent layer is formed on the transparent insulating film by plasma treatment using a gas having a fluorine component. In the manufacturing method of the active-matrix board | substrate of Claim 2,
An active matrix substrate, wherein the liquid repellent layer is formed by applying a liquid material having a fluorine component on the transparent insulating film. In the manufacturing method of the active matrix substrate in any one of Claim 1 to 4,
In the fourth step, a mask that transmits exposure light with the first energy amount and the second energy amount is used in accordance with the exposure region of the resist. In the manufacturing method of the active-matrix substrate in any one of Claim 1 to 5,
The wiring in either the first direction or the second direction is divided at the intersection,
An active matrix substrate comprising a step of forming a conductive layer for electrically connecting the divided wirings on the stacked portion. In the manufacturing method of the active-matrix board | substrate of Claim 6,
The wiring includes a source line, a gate line, and a capacitor line extending substantially linearly along the gate line, and the source line is divided at the intersection. . In the manufacturing method of the active-matrix board | substrate in any one of Claim 1 to 7,
The method of manufacturing an active matrix substrate, wherein the first step includes a step of disposing a conductive material by a droplet discharge method. A method of manufacturing a liquid crystal display device having an active matrix substrate,
A method for manufacturing a liquid crystal display device, wherein the active matrix substrate is manufactured by the method for manufacturing an active matrix substrate according to claim 1. A method of manufacturing a liquid crystal display device according to claim 9,
The resist is formed corresponding to a liquid crystal alignment pattern provided in a region surrounded by the partition part,
In the fourth step, the resist corresponding to the liquid crystal alignment pattern is unexposed together with the partition portion.

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