WO2006116162A2 - Semiconductor package - Google Patents

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Publication number
WO2006116162A2
WO2006116162A2 PCT/US2006/015205 US2006015205W WO2006116162A2 WO 2006116162 A2 WO2006116162 A2 WO 2006116162A2 US 2006015205 W US2006015205 W US 2006015205W WO 2006116162 A2 WO2006116162 A2 WO 2006116162A2
Authority
WO
WIPO (PCT)
Prior art keywords
package
conductive
semiconductor device
conductive clip
power semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2006/015205
Other languages
French (fr)
Other versions
WO2006116162A3 (en
Inventor
Martin Standing
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies Americas Corp
Original Assignee
International Rectifier Corp USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Rectifier Corp USA filed Critical International Rectifier Corp USA
Priority to DE112006000954T priority Critical patent/DE112006000954B4/en
Publication of WO2006116162A2 publication Critical patent/WO2006116162A2/en
Publication of WO2006116162A3 publication Critical patent/WO2006116162A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/20—Conductive package substrates serving as an interconnection, e.g. metal plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/20—Conductive package substrates serving as an interconnection, e.g. metal plates
    • H10W70/24—Conductive package substrates serving as an interconnection, e.g. metal plates characterised by materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/424—Cross-sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/435—Shapes or dispositions of insulating layers on leadframes, e.g. bridging members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/456—Materials
    • H10W70/457—Materials of metallic layers on leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/688—Flexible insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/60—Strap connectors, e.g. thick copper clips for grounding of power devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/17—Containers or parts thereof characterised by their materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07131—Means for applying material, e.g. for deposition or forming coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/076—Connecting or disconnecting of strap connectors
    • H10W72/07631—Techniques
    • H10W72/07636—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/076—Connecting or disconnecting of strap connectors
    • H10W72/07631—Techniques
    • H10W72/07637—Techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/60—Strap connectors, e.g. thick copper clips for grounding of power devices
    • H10W72/631—Shapes of strap connectors
    • H10W72/634—Cross-sectional shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/60—Strap connectors, e.g. thick copper clips for grounding of power devices
    • H10W72/651—Materials of strap connectors
    • H10W72/652—Materials of strap connectors comprising metals or metalloids, e.g. silver
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/60—Strap connectors, e.g. thick copper clips for grounding of power devices
    • H10W72/651—Materials of strap connectors
    • H10W72/655—Materials of strap connectors of outermost layers of multilayered strap connectors, e.g. material of a coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/856—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/926—Multiple bond pads having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/761—Package configurations characterised by the relative positions of pads or connectors relative to package parts of strap connectors
    • H10W90/764—Package configurations characterised by the relative positions of pads or connectors relative to package parts of strap connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49128—Assembling formed circuit to base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
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    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49174—Assembling terminal to elongated conductor

Definitions

  • the present invention relates to semiconductor packages. [0003] In the recent years, chip-scale packages have become very important. The present invention relates to power semiconductor packages and methods of manufacturing power semiconductor packages.
  • a package 10 includes a conductive can 12, and- a power semiconductor die 14.
  • Can 12 is typically formed with an electrically conductive material such as copper or a copper-based alloy, and may be coated with silver, gold or the like.
  • Die 14 may be a vertical conduction type power semiconductor MOSFET having its drain electrode 16 electrically and mechanically attached to an interior surface of can 12 by a conductive adhesive 18 such as solder or a conductive epoxy (e.g. silver epoxy).
  • Source electrode 20, and gate electrode 22 of die 14 each includes a solderable body which facilitates its direct connection to a respective conductive pad 24, 26 of a circuit board 28 by a conductive adhesive (e.g. solder or conductive epoxy) as illustrated by Fig. 4.
  • die 14 further includes passivation body 30 which partially covers source electrode 20 and gate electrode 22, but includes openings to allow access at least to the solderable portions thereof for electrical connection.
  • conductive can 12 includes web portion 13 (to which die 14 is electrically and mechanically connected), wall 15 surrounding web portion 13, and two oppositely disposed rails 32 extending from wall 15 each configured for connection to a respective conductive pad 34 on circuit board 28.
  • die 14 is spaced from wall 13 of can 12; i.e. wall 13 surrounds die 14.
  • a moat 36 is present between die 14 and wall 13.
  • source electrode 20, and gate electrode 22 are soldered down by the user. Specifically, the user applies solder to, for example, the pads of a circuit board, and the electrodes of the die are attached to the pads by the solder so placed.
  • a package as described above is disclosed in U.S. 6,624,522.
  • DESCRIPTION OF PROCESS FOR FABRICATING DEVICE [0007] m some applications it is desirable to co-package two or more die in the same package. For example, it is desirable to co-package a power semiconductor die such as a power MOSFET with an IC die or the like for driving the die.
  • a power semiconductor die such as a power MOSFET with an IC die or the like for driving the die.
  • a semiconductor package includes a can-shaped conductive clip having an interior surface, a dielectric body disposed over at least a portion of the interior surface of the conductive clip, at least one I/O terminal, a conductive pad, a track connecting the pad to the I/O terminal, an IC having at least one pad electrically connected to the die pad, and a power semiconductor device having at least one power electrode electrically and mechanically connected to another portion of the interior surface of the conductive clip.
  • the clip is configured to receive a power MOSFET with an IC die for driving the power die.
  • Fig. 1 is a perspective view of a package according to prior art.
  • FIG. 2 is another perspective view of the package of Fig. 1.
  • Fig. 3 is a cross-sectional view of the package of Fig. 1 along line 3-3 in
  • Fig. 4 shows the package of Fig. 1 as assembled on a circuit board.
  • Fig. 5 shows a perspective bottom view of a package according to the present invention.
  • Figs. 6-8 illustrate selected steps in the fabrication of a package according to the present invention.
  • a package 38 includes conductive can 40, which includes a web portion 42, a wall 44 surrounding web portion 42, a first rail 46 disposed at one side of wall 44, and second rail 48 disposed at a second side of wall 44 opposite the first side. Note that according to one aspect of the present invention second rail 48 is spaced laterally further'away than first wall 46 by a lateral lip portion 50.
  • Conductive can 48 is preferably made from copper or a copper alloy, and may be coated with silver, gold or the like.
  • Package 38 further includes a power semiconductor device 52.
  • Power semiconductor device is preferably a power MOSFET that includes identical or similar features as die 14 in a semiconductor package; however, device 52 may also be an IGBT or the like.
  • device 52 includes source electrode 20, a gate electrode 22 on one surface thereof, and drain electrode (not shown) on an opposite surface thereof electrically and mechanically connected to web portion 42 by a conductive adhesive 54.
  • a passivation body 56 is disposed on a surface of device 52 and surrounds source electrode 20, and gate electrode 22 in the same manner as described above with reference to the prior art.
  • source electrode 20, and gate electrode 22 may be rendered solderable for direct connection with a conductive adhesive or the like to a conductive pad of, for example, a circuit board.
  • Package 38 further includes an integrated circuit semiconductor device (IC) 58.
  • IC 58 includes a driver circuit that is capable of driving power MOSFET 52.
  • IC 58 is electrically connected to a plurality of input/output terminals (I/O) terminals 60.
  • VO terminals 60 reside over an insulation body disposed on lip portion 50. The purpose of I/O terminals 60 is to transmit input signals to IC 58, and receive output signals from IC 58.
  • I/O terminals 60 are coplanar with first and second tracks 46, 48.
  • VO terminals 60 may be electrically and mechanically connected to corresponding pads on a circuit board (e.g. by a conductive adhesive such as solder or conductive epoxy) ihat are coplanar with and adjacent to a pad designated for receiving second rail 48.
  • a dielectric body 62 is deposited on a portion of web portion 42 extending along a portion of wall 44 and lip 50.
  • Dielectric body 62 is preferably made from a polymer-based material, and can be deposited through stenciling, drop-on-demand deposition, or any other suitable method.
  • Drop-on-demand deposition is disclosed in U.S. Patent Application No. 11/367,725, assigned to the assignee of the present invention, and incorporated herein by this reference. Drop-on-demand deposition is a preferred method for the advantages set forth in U.S. Patent Application No. 11/367,725.
  • Dielectrics capable of the isolation desired for a package according to the present invention have been used in the production of plasma panel displays.
  • Such dielectric materials include dielectric particles loaded in an organic base, which may be any of the following depending upon the application requirements: epoxy, acrylic based (acrylate), polyimide or organopolysiloxane.
  • UV curing materials are preferred to reduce the process time, although other materials such as thermally curable materials may be used without deviating from the present invention.
  • the dielectric material would be typically a metal oxide such as alumina or aluminum nitride.
  • the dielectric material has a low and very controlled particle size to allow for drop-on-demand deposition.
  • a plurality of conductive input/output leads are formed on dielectric body 62.
  • Each 170 lead includes a conductive pad 64 which is electrically connected to a respective I/O terminal 60 via a respective conductive track 66.
  • I/O leads can also be formed through any printing method such as stenciling, or deposition method such as drop-on-demand deposition.
  • an organic based trace layer can be first deposited and cured. The cured trace will then form a seed layer for the construction of VO pads 64, tracks, and VO terminals 60.
  • the material used for forming I/O leads and I/O terminals 60 may be a polymer that is impregnated with micronized, highly conductive particles.
  • the dispersion of micronized, highly conductive particles within a polymer matrix can allow for relatively low resistance I/O leads and 170 terminals suitable for carrying signals to and from IC 58.
  • the conductive materials suitable for a package according to the present invention should be very similar in formulation to the dielectrics regarding the base materials.
  • the conductive micronized fillers tend to be materials that are both highly conductive and have low tendencies to oxidize. Typical materials deemed suitable include gold, silver, platinum, rhodium etc, or combinations thereof.
  • the conductive material may be a mixture of reflowing (solders) and non-reflowing (metal particles) mixed in with a fluid to form a slurry, which is then printed to form a reflowable, fusible material, similar to the solder paste referred to above and disclosed in U.S. Patent Application No. 11/367,725.
  • the alternative conductive material may increase the choices of metals, as the fluid used for the slurry could be used to reduce or protect the metals from oxidation.
  • a protective body 68 is deposited over at least conductive tracks 66. Note that pads 64, and terminals 60 remain exposed.
  • Protective body 68 may be a solder resist material; i.e. a material that is unwettable by liquid solder, and may serve as a passivation.
  • protective body 68 is polymer-based.
  • Protective body 68 may be printed using any known method such a stenciling, or deposited using drop-on-demand deposition.
  • a thick layer of conductive adhesive material is printed onto I/O pads 64 to be used as a die-bonding medium for IC 58.
  • a highly solvent thinned, low resin loaded slurry material is printed onto the VO terminals 60. The slurry material acts as a base layer for tinning or possible plating.
  • device 52 and IC 58 are installed. Specifically, with a conductive adhesive the drain electrode of device 52 is electrically and mechanically connected to web portion 42 of can 40, and the electrodes (not shown) of IC 58 are electrically and mechanically connected to pads 64 using a conductive adhesive such as solder or a conductive epoxy, thereby realizing package 38 as illustrated in Fig. 5.
  • a conductive adhesive such as solder or a conductive epoxy
  • conductive epoxy is used for the connection of IC 58 and device 52. Specifically, conductive epoxy is deposited on web 42, and on I/O pads, device 52 and IC 58 are placed on the conductive epoxy deposits, and the arrangement is subject to a curing step.
  • a solder paste such as the solder paste disclosed in U.S. Pat. Appln. No. 10/970,165, is then deposited onto source electrode 20 and gate electrode 22 of device 52, and also I/O terminals 60.
  • the arrangement is then subjected to a reflow heating step followed by a cleaning step.
  • IC 58 may be then underfilled using a volatile free organopolysiloxane, and the whole assembly (except for rails 46,48, I/O terminals 60, source electrode 20, and gate electrode 22) is covered with an organopolysiloxane.
  • the assembly is then subjected to an appropriate curing step.
  • IC 58 can be electrically connected to device 52 through conductive tracks on a circuit board, once package 38 is assembled in place.

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Die Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.

Description

SEMICONDUCTOR PACKAGE
RELATED APPLICATION
[0001] This application is based on and claims benefit of United States Provisional Application No. 60/674,162, filed on April 21, 2005, entitled Semiconductor Package, to which a claim of priority is hereby made and the disclosure of which is incorporated by reference.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to semiconductor packages. [0003] In the recent years, chip-scale packages have become very important. The present invention relates to power semiconductor packages and methods of manufacturing power semiconductor packages.
[0004] Referring to Figs. 1-4, a package 10 according to the prior art includes a conductive can 12, and- a power semiconductor die 14. Can 12 is typically formed with an electrically conductive material such as copper or a copper-based alloy, and may be coated with silver, gold or the like. Die 14 may be a vertical conduction type power semiconductor MOSFET having its drain electrode 16 electrically and mechanically attached to an interior surface of can 12 by a conductive adhesive 18 such as solder or a conductive epoxy (e.g. silver epoxy). Source electrode 20, and gate electrode 22 of die 14 (which are disposed on a surface opposite to the drain electrode) each includes a solderable body which facilitates its direct connection to a respective conductive pad 24, 26 of a circuit board 28 by a conductive adhesive (e.g. solder or conductive epoxy) as illustrated by Fig. 4. Note that die 14 further includes passivation body 30 which partially covers source electrode 20 and gate electrode 22, but includes openings to allow access at least to the solderable portions thereof for electrical connection. Further note that in package 10 conductive can 12 includes web portion 13 (to which die 14 is electrically and mechanically connected), wall 15 surrounding web portion 13, and two oppositely disposed rails 32 extending from wall 15 each configured for connection to a respective conductive pad 34 on circuit board 28. Also, note that die 14 is spaced from wall 13 of can 12; i.e. wall 13 surrounds die 14. Thus, a moat 36 is present between die 14 and wall 13. [0005] In a package according to the prior art, source electrode 20, and gate electrode 22 are soldered down by the user. Specifically, the user applies solder to, for example, the pads of a circuit board, and the electrodes of the die are attached to the pads by the solder so placed. [0006] A package as described above is disclosed in U.S. 6,624,522.
DESCRIPTION OF PROCESS FOR FABRICATING DEVICE [0007] m some applications it is desirable to co-package two or more die in the same package. For example, it is desirable to co-package a power semiconductor die such as a power MOSFET with an IC die or the like for driving the die. [0008] A semiconductor package according to the present invention includes a can-shaped conductive clip having an interior surface, a dielectric body disposed over at least a portion of the interior surface of the conductive clip, at least one I/O terminal, a conductive pad, a track connecting the pad to the I/O terminal, an IC having at least one pad electrically connected to the die pad, and a power semiconductor device having at least one power electrode electrically and mechanically connected to another portion of the interior surface of the conductive clip. [0009] In a package according to the preferred embodiment of the present invention the clip is configured to receive a power MOSFET with an IC die for driving the power die.
[0010] Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.
BRIEF DESCRIPTION OF THE FIGURES
[0011] Fig. 1 is a perspective view of a package according to prior art.
[0012] Fig. 2 is another perspective view of the package of Fig. 1.
[0013] Fig. 3 is a cross-sectional view of the package of Fig. 1 along line 3-3 in
Fig. 2.
[0014] Fig. 4 shows the package of Fig. 1 as assembled on a circuit board.
[0015] Fig. 5 shows a perspective bottom view of a package according to the present invention.
[0016] Figs. 6-8 illustrate selected steps in the fabrication of a package according to the present invention.
DETAILED DESCRIPTION OF EMBODIMENT [0017] Referring next to Fig. 5, a package 38 according to the preferred embodiment of the present invention includes conductive can 40, which includes a web portion 42, a wall 44 surrounding web portion 42, a first rail 46 disposed at one side of wall 44, and second rail 48 disposed at a second side of wall 44 opposite the first side. Note that according to one aspect of the present invention second rail 48 is spaced laterally further'away than first wall 46 by a lateral lip portion 50. Conductive can 48 is preferably made from copper or a copper alloy, and may be coated with silver, gold or the like. Package 38 further includes a power semiconductor device 52. Power semiconductor device is preferably a power MOSFET that includes identical or similar features as die 14 in a semiconductor package; however, device 52 may also be an IGBT or the like. Specifically, device 52 includes source electrode 20, a gate electrode 22 on one surface thereof, and drain electrode (not shown) on an opposite surface thereof electrically and mechanically connected to web portion 42 by a conductive adhesive 54. Note that similar to die 14, a passivation body 56 is disposed on a surface of device 52 and surrounds source electrode 20, and gate electrode 22 in the same manner as described above with reference to the prior art. Note that source electrode 20, and gate electrode 22 may be rendered solderable for direct connection with a conductive adhesive or the like to a conductive pad of, for example, a circuit board.
[0018] Package 38 further includes an integrated circuit semiconductor device (IC) 58. hi the preferred embodiment, IC 58 includes a driver circuit that is capable of driving power MOSFET 52. IC 58 is electrically connected to a plurality of input/output terminals (I/O) terminals 60. VO terminals 60 reside over an insulation body disposed on lip portion 50. The purpose of I/O terminals 60 is to transmit input signals to IC 58, and receive output signals from IC 58. Note that preferably I/O terminals 60 are coplanar with first and second tracks 46, 48. As a result, when assembled, VO terminals 60 may be electrically and mechanically connected to corresponding pads on a circuit board (e.g. by a conductive adhesive such as solder or conductive epoxy) ihat are coplanar with and adjacent to a pad designated for receiving second rail 48.
[0019] Referring next to Figs. 6-8, to fabricate package 38 first a dielectric body 62 is deposited on a portion of web portion 42 extending along a portion of wall 44 and lip 50. Dielectric body 62 is preferably made from a polymer-based material, and can be deposited through stenciling, drop-on-demand deposition, or any other suitable method. Drop-on-demand deposition is disclosed in U.S. Patent Application No. 11/367,725, assigned to the assignee of the present invention, and incorporated herein by this reference. Drop-on-demand deposition is a preferred method for the advantages set forth in U.S. Patent Application No. 11/367,725. [0020] Dielectrics capable of the isolation desired for a package according to the present invention have been used in the production of plasma panel displays. Such dielectric materials include dielectric particles loaded in an organic base, which may be any of the following depending upon the application requirements: epoxy, acrylic based (acrylate), polyimide or organopolysiloxane. UV curing materials are preferred to reduce the process time, although other materials such as thermally curable materials may be used without deviating from the present invention. The dielectric material would be typically a metal oxide such as alumina or aluminum nitride. Preferably, the dielectric material has a low and very controlled particle size to allow for drop-on-demand deposition.
[0021] Referring next to Fig. 7, a plurality of conductive input/output leads (I/O leads) are formed on dielectric body 62. Each 170 lead includes a conductive pad 64 which is electrically connected to a respective I/O terminal 60 via a respective conductive track 66. I/O leads can also be formed through any printing method such as stenciling, or deposition method such as drop-on-demand deposition. In one alternative embodiment, an organic based trace layer can be first deposited and cured. The cured trace will then form a seed layer for the construction of VO pads 64, tracks, and VO terminals 60.
[0022] The material used for forming I/O leads and I/O terminals 60 may be a polymer that is impregnated with micronized, highly conductive particles. The dispersion of micronized, highly conductive particles within a polymer matrix can allow for relatively low resistance I/O leads and 170 terminals suitable for carrying signals to and from IC 58. [0023] The conductive materials suitable for a package according to the present invention should be very similar in formulation to the dielectrics regarding the base materials. The conductive micronized fillers tend to be materials that are both highly conductive and have low tendencies to oxidize. Typical materials deemed suitable include gold, silver, platinum, rhodium etc, or combinations thereof. [0024] Alternatively, the conductive material may be a mixture of reflowing (solders) and non-reflowing (metal particles) mixed in with a fluid to form a slurry, which is then printed to form a reflowable, fusible material, similar to the solder paste referred to above and disclosed in U.S. Patent Application No. 11/367,725. The alternative conductive material may increase the choices of metals, as the fluid used for the slurry could be used to reduce or protect the metals from oxidation. [0025] Referring next to Fig. 8, a protective body 68 is deposited over at least conductive tracks 66. Note that pads 64, and terminals 60 remain exposed. Protective body 68 may be a solder resist material; i.e. a material that is unwettable by liquid solder, and may serve as a passivation. Preferably, protective body 68 is polymer-based. Protective body 68 may be printed using any known method such a stenciling, or deposited using drop-on-demand deposition. [0026] Thereafter, a thick layer of conductive adhesive material is printed onto I/O pads 64 to be used as a die-bonding medium for IC 58. At the same time a highly solvent thinned, low resin loaded slurry material is printed onto the VO terminals 60. The slurry material acts as a base layer for tinning or possible plating. [0027] Next, device 52 and IC 58 are installed. Specifically, with a conductive adhesive the drain electrode of device 52 is electrically and mechanically connected to web portion 42 of can 40, and the electrodes (not shown) of IC 58 are electrically and mechanically connected to pads 64 using a conductive adhesive such as solder or a conductive epoxy, thereby realizing package 38 as illustrated in Fig. 5. [0028] In one preferred embodiment, conductive epoxy is used for the connection of IC 58 and device 52. Specifically, conductive epoxy is deposited on web 42, and on I/O pads, device 52 and IC 58 are placed on the conductive epoxy deposits, and the arrangement is subject to a curing step. Optionally, a solder paste, such as the solder paste disclosed in U.S. Pat. Appln. No. 10/970,165, is then deposited onto source electrode 20 and gate electrode 22 of device 52, and also I/O terminals 60. The arrangement is then subjected to a reflow heating step followed by a cleaning step. With or without the solder paste, optionally, IC 58 may be then underfilled using a volatile free organopolysiloxane, and the whole assembly (except for rails 46,48, I/O terminals 60, source electrode 20, and gate electrode 22) is covered with an organopolysiloxane. The assembly is then subjected to an appropriate curing step. As a result, IC 58 can be electrically connected to device 52 through conductive tracks on a circuit board, once package 38 is assembled in place. [0029] Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art.

Claims

WHAT IS CLAIMED IS:
1. A semiconductor package comprising: a conductive clip having an interior surface; a dielectric body disposed over at least a portion of said interior surface of said conductive clip; at least one I/O tenninal; a conductive pad; a track connecting said pad to said I/O terminal; an IC having at least one pad electrically connected to said die pad; and a power semiconductor device having at least one power electrode electrically and mechanically connected to another portion of said interior surface of said conductive clip.
2. The package of claim 1, wherein said power semiconductor device is a power MOSFET.
3. The package of claim 1, wherein said power semiconductor device is an IGBT.
4. The package of claim 1, wherein said IC includes a driver circuit for driving said power semiconductor device.
5. The package of claim 1, wherein said conductive clip is can-shaped.
6. The package of claim 1, wherein said conductive clip is comprised of copper.
7. The package of claim 1, wherein said conductive clip is plated with either gold or silver.
8. The package of claim 1, further comprising a solder resist body covering at least said track.
9. The package of claim 1, wherein said dielectric body is comprised of a polymer.
10. A process for fabricating a semiconductor package comprising: depositing a dielectric body over a portion of an interior surface of a conductive clip; forming at least one I/O lead over said dielectric body, said I/O lead including a conductive pad portion, an I/O terminal, and a track connecting said conductive pad to said I/O terminal; connecting an electrode of an IC to said conductive pad portion; electrically and mechanically connecting a power electrode of a power semiconductor device to said interior surface of said conductive clip.
11. The process of claim 10, wherein said dielectric body is drop-on- demand deposited.
12. The process of claim 10, wherein said I/O lead is drop-on-demand deposited.
13. The process of claim 10, further comprising depositing a solder resist over at least a portion of said terminal.
14. The process of claim 13, wherein said solder resist is drop-on-demand deposited.
15. The process of claim 10, wherein said power semiconductor device is a power MOSFET.
16. The process of claim 10, wherein said power semiconductor device is an IGBT.
17. The process of claim 10, wherein said IC includes a driver circuit for driving said power semiconductor device.
18. The process of claim 10, wherein said conductive clip is can-shaped.
19. The process of claim 10, wherein said conductive clip is comprised of copper.
20. The process of claim 10, wherein said conductive clip is plated with either gold or silver.
21. The process of claim 10, wherein said dielectric body is comprised of a polymer.
PCT/US2006/015205 2005-04-21 2006-04-21 Semiconductor package Ceased WO2006116162A2 (en)

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US9799623B2 (en) 2017-10-24
US20060237840A1 (en) 2006-10-26
CN100524705C (en) 2009-08-05
US20160300811A1 (en) 2016-10-13
US20150255376A1 (en) 2015-09-10
TWI312185B (en) 2009-07-11
US8061023B2 (en) 2011-11-22
DE112006000954B4 (en) 2012-10-25
DE112006000954T5 (en) 2008-02-21
CN101138083A (en) 2008-03-05
US9391004B2 (en) 2016-07-12
WO2006116162A3 (en) 2007-07-05
US20180012859A1 (en) 2018-01-11
US7230333B2 (en) 2007-06-12
US20080066303A1 (en) 2008-03-20
US20150255382A1 (en) 2015-09-10
US9391003B2 (en) 2016-07-12
US7368325B2 (en) 2008-05-06
US9041191B2 (en) 2015-05-26
US20120061725A1 (en) 2012-03-15
TW200644217A (en) 2006-12-16
US20070202631A1 (en) 2007-08-30

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