JP3964319B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP3964319B2
JP3964319B2 JP2002369459A JP2002369459A JP3964319B2 JP 3964319 B2 JP3964319 B2 JP 3964319B2 JP 2002369459 A JP2002369459 A JP 2002369459A JP 2002369459 A JP2002369459 A JP 2002369459A JP 3964319 B2 JP3964319 B2 JP 3964319B2
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electrode
circuit board
formed
electrodes
semiconductor device
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JP2004200552A (en
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敬村 中西
聖明 門井
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セイコーインスツル株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Description

【0001】 [0001]
【産業上の利用分野】 BACKGROUND OF THE INVENTION
本発明は、絶縁回路基板に実装された半導体装置に関し、特に、半導体基板の突起電極を絶縁回路基板の接続パッドに異方性導電膜を介して接続して成る半導体装置に関する。 The present invention relates to a semiconductor device mounted on the insulating circuit board, in particular, it relates to a semiconductor device formed by connecting via the anisotropic conductive film protruding electrodes of the semiconductor substrate to the connection pads of the insulating circuit board.
【0002】 [0002]
【従来の技術】 BACKGROUND OF THE INVENTION
電気機器の小型化に伴い、半導体素子の実装方法として、突起電極を有するベアチップを回路基板上の端子電極に裏返して接続するフリップチップ実装という方法が開発された。 Along with miniaturization of electric equipment, as a mounting method of a semiconductor device, a method of flip-chip mounting of connecting Turn the bare chip having a protruding electrode to the terminal electrode on the circuit board it has been developed. その方法の一つに、回路基板上の実装領域に異方性導電膜を介在させて、その上から半導体素子を装着機で位置決めすると共に、加熱及び加圧手段により硬化させて実装する方法が知られている。 One of the methods, by interposing an anisotropic conductive film mounting area on the circuit board, along with positioning the semiconductor element thereon with placement machine, how to implement is cured by heating and pressing means Are known. この異方性導電膜は、ファインピッチの接続端子間の接続に優れ、一般の回路基板における半導体素子の実装や、TABやCOG等に使用されている。 The anisotropic conductive film is excellent in the connection between the connection terminals of the fine-pitch, mounting and the semiconductor device in a general circuit board, it is used in TAB or COG or the like.
【0003】 [0003]
図2は、異方性導電接着剤によって半導体素子と回路基板とを接続する従来の半導体装置の構成を示す断面図である。 Figure 2 is a sectional view showing a configuration of a conventional semiconductor device for connecting the semiconductor element and the circuit board by an anisotropic conductive adhesive. 図において、1は半導体素子、2は半導体素子1の上に形成された電極パッド、3は保護絶縁膜、4は保護絶縁膜3の電極パッド2に対応する領域に開けられた開口部に形成されたバリアメタル、5はバリアメタル4上に形成された突起電極、7は異方性導電膜、7aは導電性粒子、8は回路基板上の端子電極、9は回路基板を示す。 In FIG, 1 semiconductor device, 2 is the electrode pads formed on the semiconductor element 1, 3 is a protective insulating film, 4 is formed in the opening bored in a region corresponding to the electrode pads 2 of the protective insulating film 3 It has been the barrier metal, 5 projecting electrodes formed on the barrier metal 4, the anisotropic conductive film 7, 7a of the conductive particles, 8 terminal electrodes on the circuit board, 9 denotes a circuit board. なお、異方性導電膜とは、接着剤中に金属粒子、プラスチックボールの表面に金属をめっきした粒子などを分散したもので、圧力が加えられると接着剤が排除され、電気的な導通が得られるものである。 Note that the anisotropic conductive film, metal particles in the adhesive, which was like dispersed particles plated with metal on the surface of the plastic ball, adhesive and pressure is applied is eliminated, the electrical conduction it is obtained. 回路基板9上の端子電極8上に異方性導電膜7を形成し、突起電極5の下の部分の異方性導電膜7は圧力が加えられた方向に導通する。 An anisotropic conductive film 7 is formed on the terminal electrodes 8 on the circuit board 9, the anisotropic conductive film of the lower part of the projection electrodes 5 7 conducts in the direction in which pressure is applied. これにより、突起電極5と端子電極8は導通する。 Thus, the projection electrodes 5 and the terminal electrode 8 is conductive. 同時に、半導体素子1は回路基板9に異方性導電膜7の接着作用により固着され、外部からの湿気やほこりの侵入を防止することができる。 At the same time, the semiconductor element 1 is fixed by the adhesive action of the anisotropic conductive film 7 on the circuit board 9, it is possible to prevent moisture and dust from entering from the outside. また、半導体素子1の下面は異方性導電膜7によって全面的に回路基板9に接着しているので接着面積が広くなり接合強度も強くなる。 The lower surface of the semiconductor element 1 is also stronger bonding strength bonding area becomes larger because the adhered entirely on the circuit board 9 by an anisotropic conductive film 7.
【0004】 [0004]
また、図3(特許文献1参照)は、異方性導電接着剤によって半導体素子と回路基板とを接続する従来の半導体装置の構成を示す断面図である。 Further, FIG. 3 (see Patent Document 1) is a sectional view showing a configuration of a conventional semiconductor device for connecting the semiconductor element and the circuit board by an anisotropic conductive adhesive. 図において、1は半導体素子、2は半導体素子1の上に形成された電極パッド、5は電極2上に形成された突起電極、7は異方性導電膜、7aは導電性粒子、8は回路基板上の端子電極、9は回路基板、10は導電性粒子7aを含まない接着剤のみの層を示す。 In FIG, 1 is a semiconductor element, 2 is the electrode pads formed on the semiconductor element 1, the protruding electrodes are formed on the electrode 2 5, an anisotropic conductive film 7, 7a of the conductive particles, the 8 terminal electrodes on the circuit board, 9 circuit board, 10 denotes a layer of adhesive only without conductive particles 7a. 上記公報では、半導体素子1の表面の電極2上にワイヤーボンディングにより突起電極5を形成し、半導体素子1と回路基板9との間にあり半導体素子1の側に導電性粒子7aを含まない接着剤のみの層を設けることで電極間の絶縁性を確保している。 In the above publication, the projection electrodes 5 are formed by wire bonding on the electrode 2 on the surface of the semiconductor element 1, it does not contain conductive particles 7a located on the side of the semiconductor element 1 between the semiconductor element 1 and the circuit board 9 bond It has secured insulation between the electrodes by providing a layer of material only.
【0005】 [0005]
【特許文献1】 [Patent Document 1]
特開平10−125725号公報【0006】 Japanese Unexamined Patent Publication No. 10-125725 [0006]
【発明が解決しようとする課題】 [Problems that the Invention is to Solve
しかしながら、異方性導電膜を用いた従来の実装方法では、近年における産業界の要求に応じて導電接続の対象である端子の間隔、すなわちピッチを狭くするとき、半導体素子表面での隣り合う突起電極間に存在する導電性粒子によって当該一対の突起電極間の絶縁抵抗が劣化したり、異方性導電膜中の導電粒子の接触によりショートが発生して電極間の接続信頼性が低下するという問題点があった。 However, in the conventional mounting method using the anisotropic conductive film, the spacing of the terminal that is the subject of the conductive connection in accordance with industry requirements in recent years, that is, when narrowing the pitch, adjacent the semiconductor element surface projections deteriorated insulation resistance between the pair of projections electrodes by the conductive particles existing between the electrodes, that the connection reliability between the short occurs electrodes by contact of the conductive particles in the anisotropic conductive film is reduced there is a problem. また、電極の狭ピッチ化において、実装方法としてワイヤーボンディングを用いる事は困難になりつつある。 Further, the pitch of the electrode, the use of wire bonding as a mounting method is becoming difficult. 本発明は、上記の問題点に鑑みて成されたものであって、端子間ピッチが狭くなる場合でも導電粒子による端子間のショートの発生を防止でき、しかも従来の技術を用いて実装を行うことができる半導体装置及びその実装方法を提供することを目的とする。 The present invention, which was made in view of the above problems, it is possible to prevent the occurrence of short circuit between the terminals by the conductive particles, even if the inter-terminal pitch is narrow, yet performs implemented using conventional techniques and to provide a semiconductor device and a mounting method thereof capable.
【0007】 [0007]
【課題を解決するための手段】 In order to solve the problems]
本発明は、上記目的を達成するために、半導体基板の主表面上に形成された電極パッドと、前記電極パッドと半導体基板の主表面を覆う保護絶縁膜と、前記保護絶縁膜の前記電極パッドに対応する領域に開けられた開口部を覆うように、前記電極パッドと接続して形成されたバリアメタルと、前記バリアメタル上に形成された突起電極と、前記バリアメタル及び突起電極の外周側面を覆う保護絶縁膜と、前記突起電極と対向する位置に配設された端子電極を有する絶縁回路基板と、前記絶縁回路基板と半導体基板の間の間隙を充填し、突起電極と絶縁回路基板上の端子電極とを導通させる異方性導電膜の層とを備えたものである。 The present invention, in order to achieve the above object, an electrode pad formed on the main surface of the semiconductor substrate, and a protective insulating film covering the major surface of the electrode pad and the semiconductor substrate, the electrode pad of the insulation layer so as to cover the opening bored in a region corresponding to the outer peripheral side surface of the electrode pad and the barrier metal formed by connecting the projecting electrodes formed on the barrier metal, the barrier metal and the projecting electrodes a protective insulating film covering the insulating circuit board having protruding electrodes opposed to disposed the terminal electrodes to position, fills the gap between the insulated circuit substrate and the semiconductor substrate, the projection electrodes and the insulating circuit board anisotropic conductive film for electrically connecting the terminal electrodes of those having a layer. また、この発明に係る半導体装置は、バリアメタル及び突起電極の外周側面を覆う保護絶縁膜として、窒化膜、Si酸化膜、ポリイミド有することを特徴とするものである。 The semiconductor device according to the present invention, as the protective insulating film covering the outer peripheral side surface of the barrier metal and the protruding electrodes, nitride, Si oxide film, is characterized in that it has a polyimide.
【0008】 [0008]
【発明の実施の形態】 DETAILED DESCRIPTION OF THE INVENTION
以下、本発明の一実施の形態を図面に基づいて説明する。 Hereinafter, an embodiment of the present invention with reference to the accompanying drawings. 尚、図において従来と同一符号は従来のものと同一あるいは相当のものを表す。 Incidentally, conventionally the same reference numerals in the drawing represent one of the same or corresponding to those of the prior art.
【0009】 [0009]
図1は、本発明の一実施の形態による半導体装置の構成を示す断面図である。 Figure 1 is a sectional view showing a structure of a semiconductor device according to an embodiment of the present invention. 図において、1は半導体素子、2は半導体素子1の主表面上に形成された電極パッド、3は保護絶縁膜である。 In FIG, 1 is a semiconductor element, 2 is the electrode pads formed on the main surface of the semiconductor element 1, 3 is a protective insulating film. 保護絶縁膜3は、半導体素子1の主表面と電極パッド2の外周部を覆っている。 Protective insulating film 3 covers the outer periphery of the main surface and the electrode pad 2 of semiconductor device 1. 保護絶縁膜3には、電極パッド2に対応する領域に開けられた開口部に形成されている。 The protective insulating film 3 is formed in an opening bored in a region corresponding to the electrode pads 2. 4は、開口部と開口部周辺の保護絶縁膜3を覆うように設けられたバリアメタル、5はバリアメタル4上に形成された突起電極である。 4, the opening and the opening periphery of the protective insulating film 3 so as to cover provided with a barrier metal, is 5 a projection electrode formed on the barrier metal 4. 6はバリアメタル4及び突起電極5の外周側面の全面を覆う絶縁膜である。 6 is an insulating film covering the entire surface of the outer peripheral side surface of the barrier metal 4 and the projecting electrodes 5. 7は異方性導電膜、7aは導電性粒子である。 7 anisotropic conductive film, 7a is electrically conductive particles. 半導体素子1の対向する位置に回路基板9が設けられており、回路基板9上には、端子電極8が電極パッド2に対応する位置に形成されている。 And the circuit board 9 is provided at a position facing the semiconductor element 1, on the circuit board 9, the terminal electrode 8 is formed at a position corresponding to the electrode pads 2. 回路基板9は例えばガラス基板からなる絶縁回路基板である。 Circuit board 9 is an insulating circuit substrate such as a glass substrate. 本実施の形態においては、バリアメタル4及び突起電極5の外周側面を覆うように絶縁膜が形成されているので、各突起電極間に導電性粒子7a同士の接触によるショートが発生しても、電極間のショートにまでは至る確率は低くなり、良好な絶縁性を確保することができる。 In the present embodiment, since the insulating film so as to cover the outer peripheral side surface of the barrier metal 4 and the projection electrodes 5 are formed, even if short-circuit occurs due to contact between the conductive particles 7a between the projecting electrodes, probability of reaching up to the short circuit between the electrodes is lowered, it is possible to ensure good insulation.
【0010】 [0010]
尚、バリアメタル4及び突起電極5の外周側面を覆う絶縁膜6の材料は、CVD法などにより形成される窒化膜やSi酸化膜、または、塗布法により形成されるポリイミドから成る。 The material of the insulating film 6 covering the outer peripheral side surface of the barrier metal 4 and the protruding electrodes 5, a nitride film and Si oxide film is formed by CVD or the like, or made of polyimide which is formed by a coating method. また、半導体素子1の電極パッド2上の突起電極5の材料はAu、Ag、Cu、Al、Bi、Zn、Ni、In、Pd、Si、はんだ、またはこれらの合金等の金属であれば良い。 Further, the material of the bump electrode 5 on the electrode pads 2 of the semiconductor element 1 may Au, Ag, Cu, Al, Bi, Zn, Ni, In, Pd, Si, if metal such as solder or their alloys . その形成方法は写真製版技術とめっきまたは蒸着等の金属の成膜技術を用いて行うことができる。 Its forming method can be carried out using deposition techniques metal such as plating or vapor deposition and photolithography.
【0011】 [0011]
更に、導電性粒子7aは直径が5μm程度のエポキシ等のプラスチック粒子に金等の金属膜を形成したものから成る。 Further, conductive particles 7a is consist of a diameter to form a metal film such as gold on the plastic particles such as epoxy of about 5 [mu] m. 他に、Ni、Au、Ag、またはこれらの合金等の金属粒子を用いても良い。 Other, Ni, Au, Ag, or may be used metal particles, such as those alloys. 異方性導電膜の主剤としてエポキシ樹脂等の熱硬化性樹脂、ポリエチレン樹脂等の熱可塑性樹脂、アクリル系樹脂等の光硬化性樹脂などから成る樹脂フィルムを用いても良い。 Thermosetting resin having an epoxy resin as a main component of the anisotropic conductive film, thermoplastic resin such as polyethylene resin, may be used a resin film made of a photocurable resin such as an acrylic resin.
【0012】 [0012]
【発明の効果】 【Effect of the invention】
以上説明したように、本発明の半導体装置によれば、半導体基板の主表面上に形成された電極パッドと、前記電極パッドと半導体基板の主表面を覆う保護絶縁膜と、前記保護絶縁膜の前記電極パッドに対応する領域に開けられた開口部を覆うように、前記電極パッドと接続して形成されたバリアメタルと、前記バリアメタル上に形成された突起電極と、前記バリアメタル及び突起電極の外周側面を覆う保護絶縁膜と、前記突起電極と対向する位置に配設された端子電極を有する回路基板と、前記回路基板と半導体基板の間の間隙を充填し、突起電極と回路基板上の端子電極とを導通させる異方性導電膜の層とで構成したので、半導体素子と絶縁回路基板との間で所要の電気的接続が確実に達成され、隣接する突起電極間の絶縁性を確保して絶 As described above, according to the semiconductor device of the present invention, an electrode pad formed on the main surface of the semiconductor substrate, and a protective insulating film covering the major surface of the electrode pad and the semiconductor substrate, the protective insulating film wherein as the electrode pad covering the opening bored in the corresponding region, the electrode pad and the barrier metal formed by connecting the projecting electrodes formed on the barrier metal, the barrier metal and the projecting electrodes a protective insulating film covering the outer peripheral side surface of the circuit board having the protruding electrodes opposed to disposed the terminal electrodes to position, fills the gap between the circuit board and the semiconductor substrate, the projection electrodes and the circuit board since it is configured with a layer of anisotropic conducting film for electrically connecting the terminal electrodes of the necessary electrical connections between the semiconductor element and the insulating circuit board is reliably achieved, the insulation between the adjacent protruding electrodes absolute to ensure 回路基板に搭載することが可能な構造の半導体装置を提供できるという効果がある。 There is an effect that it is possible to provide a semiconductor device structure which can be mounted on the circuit board.
【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS
【図1】本発明の一実施の形態による半導体装置の断面図である。 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
【図2】従来の半導体装置の断面図である。 2 is a cross-sectional view of a conventional semiconductor device.
【図3】他の従来の半導体装置の断面図である。 3 is a cross-sectional view of another conventional semiconductor device.
【符号の説明】 DESCRIPTION OF SYMBOLS
1 半導体基板2 電極パッド3 保護絶縁膜4 バリアメタル5 突起電極6 絶縁膜7 異方性導電膜8 端子電極9 回路基板 1 semiconductor substrate 2 electrode pads 3 protective insulating film 4 barrier metal 5 protruding electrodes 6 insulating film 7 anisotropic conductive film 8 terminal electrodes 9 circuit board

Claims (2)

  1. 半導体素子の主表面上に形成された電極パッドと、 An electrode pad formed on the main surface of the semiconductor element,
    前記電極パッドの一部を開口して、前記電極パッドと前記半導体基板の主表面を覆う保護絶縁膜と、 Open a portion of the electrode pad, and a protective insulating film covering the major surface of the semiconductor substrate and the electrode pads,
    前記電極パッドに対応する領域に開けられた開口を覆うように、前記電極パッドと接続して形成されたバリアメタルと、 So as to cover the opening bored in a region corresponding to the electrode pad, a barrier metal formed by connecting to the electrode pads,
    前記バリアメタル上に形成された突起電極と、 A protruding electrode formed on the barrier metal,
    前記バリアメタル及び突起電極の外周側面を覆う窒化膜からなる保護絶縁膜と、 A protective insulating film made of the barrier metal and the nitride film covering the outer peripheral side surface of the protrusion electrodes,
    前記突起電極と対向する位置に配設された端子電極を有する絶縁回路基板と、 An insulating circuit board having disposed the terminal electrode at a position facing the protrusion electrodes,
    前記絶縁回路基板と半導体基板の間の間隙を充填し、突起電極と絶縁回路基板上の端子電極とを導通させる異方性導電膜の層とを備えたことを特徴とする半導体装置。 The isolation circuit fills the gap between the substrate and the semiconductor substrate, a semiconductor device characterized by comprising a layer of anisotropic conductive film for electrically connecting the terminal electrodes of the bump electrode insulating circuit board.
  2. 半導体素子の主表面上に形成された電極パッドと、 An electrode pad formed on the main surface of the semiconductor element,
    前記電極パッドの一部を開口して、前記電極パッドと前記半導体基板の主表面を覆う保護絶縁膜と、 Open a portion of the electrode pad, and a protective insulating film covering the major surface of the semiconductor substrate and the electrode pads,
    前記電極パッドに対応する領域に開けられた開口を覆うように、前記電極パッドと接続して形成されたバリアメタルと、 So as to cover the opening bored in a region corresponding to the electrode pad, a barrier metal formed by connecting to the electrode pads,
    前記バリアメタル上に形成された突起電極と、 A protruding electrode formed on the barrier metal,
    前記バリアメタル及び突起電極の外周側面を覆うSi酸化膜からなる保護絶縁膜と、 A protective insulating film made of Si oxide film covering the outer peripheral side surface of the barrier metal and the projecting electrodes,
    前記突起電極と対向する位置に配設された端子電極を有する絶縁回路基板と、 An insulating circuit board having disposed the terminal electrode at a position facing the protrusion electrodes,
    前記絶縁回路基板と半導体基板の間の間隙を充填し、突起電極と絶縁回路基板上の端子電極とを導通させる異方性導電膜の層とを備えたことを特徴とする半導体装置。 The isolation circuit fills the gap between the substrate and the semiconductor substrate, a semiconductor device characterized by comprising a layer of anisotropic conductive film for electrically connecting the terminal electrodes of the bump electrode insulating circuit board.
JP2002369459A 2002-12-20 2002-12-20 Semiconductor device Active JP3964319B2 (en)

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