Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
  • H04N25/67—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
  • H04N25/671—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction
  • H04N25/677—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction for reducing the column or line fixed pattern noise
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/70—SSIS architectures; Circuits associated therewith
  • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
  • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Definitions

• the invention relates generally to semiconductor imaging devices, and more particularly to reducing the noticeability of fixed pattern noise in a solid state imager.
• CMOS active pixel imagers can have one or more active transistors within the pixel unit cell, can be made compatible with CMOS technologies, and promise higher readout rates compared to passive pixel sensors.
• FIG. 1 shows a conventional imager 200 that includes an array of pixels 230 and a timing and control circuit or controller 232 which provides timing and control signals to control the reading out of signals stored in the pixels in a manner commonly known to those skilled in the art.
• Exemplary arrays have dimensions of M times N pixels, with the size of the array 230 depending on the particular application.
• the imager is read out a row at a time using a column parallel readout architecture.
• the controller 232 selects a particular row of pixels in the array 230 by controlling the operation of row addressing circuit 234 and row drivers 240. Charge signals stored in the selected row of pixels are provided on column lines 170 (FIG. 2) to a readout circuit 242 as conventionally known.
• FIG. 2 column lines 170
• FIG. 2 more clearly shows the rows and columns 349 of pixel array 230 and the associated readout circuit 242.
• Each column 349 includes multiple rows of pixels 350.
• the readout circuit 242 includes sample and hold circuitry 351 for storing the pixel reset (Vrst) and integrated charge signals (Vsig). Signals from the pixels 350 in a particular column 349 can be read out through a column line 170 to the sample and hold circuit 351 associated with that column.
• Vrst is stored in capacitor cjrst and Vsig is stored in capacitor c_sig in the sample and hold circuit 351.
• the gain of the sample and hold circuit 351 is a function of a biasing current Iln connected to the column line 170.
• Signals stored in the readout circuit 242 can be read out sequentially column-by-column to an output stage 354, which is common to die entire array of pixels 330.
• Output stage 359 provides two output signals Voutl, Vout2 that correspond to the Vsig, Vrst signals, respectively.
• the analog output signals Voutl, Vout2 can then be sent, for example, to a differential analog circuit, which subtracts the reset and integrated charge signals and sends the subtracted signal to an analog- to-digital converter (ADC); alternatively, the reset and integrated charge signals can be supplied directly to the analog- to-digital converter.
• ADC analog- to-digital converter
• each imaging pixel array is usually tested individually. Tests detect defective pixel circuits, pixel signal level, and other array attributes, and the information is stored based on lot and individual device identification numbers. The information developed during testing can be utilized to enhance the operation of the device by, for example, compensating for defective pixels, differing pixel signal levels, and other tested pixel attributes.
• capacitors c_rst and c_sig will be different, ideally only slightly different. However, it is not easy or cheap to test the capacitance value of each capacitor c_rst, c_sig and then modify the capacitors to have the same capacitance value. Thus, capacitors c_rst and c_sig of each sample and hold circuit 351 will add a different amount of column-wise fixed pattern noise to the readout process.
• the bias current Iln will vary from column to column. Although the difference may not be large, nonetheless, the different Iln current values will add different amounts of gain during read out of each sample and hold circuit 351. Thus, the bias current Hn of each sample and hold circuit 351 will add a different amount of column- wise fixed pattern noise to the relevant process.
• the human eye is sensitive to column-wise noise, which may manifest as a column in an image being different from surrounding columns of the image. Therefore, it is desirable to modify the imager to reduce the visual obviousness of columnwise fixed pattern noise
• An imager is provided in an exemplary embodiment that reduces the visual obviousness of column- wise fixed pattern noise by randomly mixing and applying fixed pattern noise to different columns in the imager's array.
• signals from the columns of the pixel array are read out to varying sample and hold circuits selected at random.
• pixel columns are randomly matched to sample and hold circuits.
• FIG. 1 is a block diagram of a conventional digital system having an active pixel sensor array and associated processing circuitry;
• FIG. 2 is a block diagram showing a portion of the sensor of FIG. 1 in greater detail;
• FIG. 3 is a block diagram of a digital system having an active pixel sensor array and associated processing circuitry in accordance with an exemplary embodiment of the invention.
• FIG. 4 is a block diagram showing a processor system incorporating at least one imaging device constructed in accordance with an embodiment of the invention.
• FIG. 3 depicts a signal processing system 400, which includes an active pixel sensor ("APS") array 230 and a readout circuit 442 constructed in accordance with an exemplary embodiment of the invention.
• the signal processing system 400 differs from the system 200 illustrated in FIGs. 1 and 2 in several respects, which are described in greater detail below.
• the illustrated system 400 includes pixel array 230 connected to the readout circuit 442.
• Readout circuit 442 includes a first switching circuit 441, second switching circuit 443, and a controller 450 for controlling the switching circuits 441, 443.
• the readout circuit 442 is different from the conventional readout circuit 242 (FIG. 2) in that sample and hold circuits 35la-d of readout circuit 442 are not always associated with the same pixel column 349a-d (explained in more detail below).
• Each pixel column 349a-d is coupled to the first switching circuit 441.
• the switch setting of the first switching circuit 441 determines which pixel column 349a-d is selectively coupled to which sample and hold circuit 351a-d.
• FIG. 3 depicts: the first pixel column 349a coupled through the first switching circuit 441 to the second sample and hold circuit 351b; the second pixel column 349b coupled through the first switching circuit 441 to the third sample and hold circuit 351c; the third pixel column 349c coupled through the first switching circuit 441 to the fourth sample and hold circuit 35 Id; and the fourth pixel column 349d coupled through the first switching circuit 441 to the first sample and hold circuit 351a.
• the first switching circuit 441 enables each pixel column 349a-d to be substantially simultaneously coupled to an associated selected sample and hold circuit 35la-d. In another aspect, only a single pixel column is coupled to its associated selected sample and hold circuit at a time.
• the controller 450 provides signals to the first switching circuit 441 indicating which pixel column 349a-d is to be coupled to which sample and hold circuit 351a-d,
• the controller's 450 matching of pixel columns 349a- d and sample and hold circuits 35la-d is done on a random basis.
• the matching may occur in pseudo-random, or any other varying matching fashion.
• the controller 450 re-matches, i.e., generates new matches between, pixel columns 349a-d and sample and hold circuits 351a- d before each read out from a row in the pixel array 230. For example, the controller 450 determines a match and then the selected row is readout, then the controller 450 determines a match and the next row is readout. In another aspect, the controller 450 rematches periodically; that is to say that the time interval between the controller establishing another set of matches is a set time interval. The controller 450 establishes the time interval before reading out from the image array.
• the controller 450 rematches before each fifth read out from a row in the pixel array 230.
• the controller 450 re-matches at various time intervals, where the time intervals are generated on a varying fashion, ideally in a random fashion. For example, if the time interval to re-match is random, then the controller 450 re-matches before the first, fifth, and thirteenth read outs from rows in the pixel array 230.
• this invention is described with reference to a conventional readout from an array (e.g., sequentially reading a row from the first column on the left to the last column on the right and then repeating for the next row), the invention is not so limited.
• the imager may be readout in an interleaved fashion. Additionally, there are times when not all of the rows or columns are read out, e.g., when varying the resolution of the imager.
• each sample and hold circuit 351a-d is coupled to the second switching circuit 443.
• the selection of the second switching circuit 443 determines which sample and hold circuit 35la-d is coupled to the output stage 354.
• the controller 450 provides signals to the second switching circuit 443 indicating which sample and hold circuit 351a-d is to be coupled to the output stage 354.
• the controller 450 provides a signal to the second switching circuit 443 before the read out of a sample and hold circuit 351a-d.
• the controller's 450 matching of sample and hold circuits 35la-d to output stage 354 is performed based on the current matching of pixel columns 349a-d to sample and hold circuits 35la-d by the controller 450.
• the controller 450 provides an appropriate signal to the second switching circuit 443 to couple the second sample and hold circuit 351b to the output stage 354.
• the controller 450 For the next read out, the controller 450 provides an appropriate signal to the second switching circuit 443, to couple the third sample and hold circuit 351c to the output stage 354. For the next read out, the controller 450 provides an appropriate signal to the second switching circuit 443 to couple the fourth sample and hold circuit 35 Id to the output stage 354. For the next read out, the controller 450 provides an appropriate signal to the second switching circuit 443 to couple the first sample and hold circuit 351a to the output stage 354. In an alternative embodiment, the controller 450 provides a signal to a separate processing circuit (not shown) indicating the match for each row and the sample and hold circuits 351a-d will be read out sequentially left to right (i.e. circuits 351a to 35ld).
• the separate processing circuit coordinates re-ordering the signals from each column such that they are representative of the order in which they originate in the image array.
• a second switching circuit 442 is not required as the sample and hold circuits 351a-d are coupled directly to the output stage 354.
• Signals stored in the readout circuits 442 can then be read sequentially column-by-column to the output stage 354, which is common to the entire array of pixels 230.
• the analog output signals can then be sent, for example, to a differential analog circuit, which subtracts the reset and integrated charge signals and sends the subtracted signal to an analog-to-digital converter (ADC); alternatively, the reset and integrated charge signals can be supplied directly to the analog-to-digital converter.
• ADC analog-to-digital converter
• an imager that reduces the visual obviousness of column -wise fixed pattern noise by randomly mixing and applying fixed pattern noise to different columns of the array.
• Fixed pattern noise is not necessarily reduced, however, fixed pattern noise from a sample and hold circuit is not always associated with a single pixel column but is instead associated with different pixels. As the noise is applied to different columns, the human eye is less likely to notice the noise.
• FIG. 4 shows system 1100, a typical processor system modified to include an APS System 400 containing the readout system, as exemplified by FIG.3.
• the system 1100 is exemplary of a system having digital circuits that could include image sensor devices. Without being limiting, such a system could include a computer system, camera system, scanner, machine vision, vehicle navigation, video phone, surveillance system, auto focus system, star tracker system, motion detection system, image stabilization system, and others.
• System 1100 for example a camera system, generally comprises a central processing unit (CPU) 1110, such as a microprocessor, that communicates with an input/output (I/O) device 1150 over a bus 1170.
• CPU central processing unit
• I/O input/output
• Imaging device 400 also communicates with the CPU 1110 over the bus 1170.
• the system 1100 also includes random access memory (EAM) 1160, and can include removable memory 1130, such as flash memory, which also communicate with the CPU 1110 over the bus 1170.
• EAM random access memory
• removable memory 1130 such as flash memory
• the imaging device 400 may be combined with a processor, such as a CPU, digital signal processor, or microprocessor, with or without memory storage on a single integrated circuit or on a different chip than the processor.
• a method of manufacturing an CMOS readout circuit includes the steps of providing, over a portion of a substrate corresponding to a single integrated circuit, at least a pixel array and readout circuit of FIGs. 3 an 4 as described above using known semiconductor fabrication techniques.
• the method of manufacturing the readout circuit includes forming a plurality of sample and hold circuits over said substrate; and forming a switching circuit over said substrate for switchingly coupling one of said plurality of columns of pixels in said pixel array to one of said sample and hold circuits.
• the method of manufacturing may further include forming a control circuit over said substrate; and forming an electrical pathway for coupling said control circuit to said switching circuit. Additionally, the method of manufacturing may include the step of forming a second switching circuit over said substrate for switchingly coupling one of said sample and hold circuits to said downstream circuit.

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• Engineering & Computer Science (AREA)
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• Transforming Light Signals Into Electric Signals (AREA)
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• 2005
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