WO2006105320A1 - Heat treatment for forming interconnect structures with reduced electro and stress migration and/or resistivity - Google Patents
Heat treatment for forming interconnect structures with reduced electro and stress migration and/or resistivity Download PDFInfo
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- WO2006105320A1 WO2006105320A1 PCT/US2006/011695 US2006011695W WO2006105320A1 WO 2006105320 A1 WO2006105320 A1 WO 2006105320A1 US 2006011695 W US2006011695 W US 2006011695W WO 2006105320 A1 WO2006105320 A1 WO 2006105320A1
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- metal
- metal line
- heat treatment
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- metal lines
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
Definitions
- the present invention relates to the formation of microstructures, such as advanced integrated circuits, and, more particularly, to the formation of conductive structures, such as metal lines in metallization layers of integrated circuits.
- Advanced integrated circuits including transistor elements having a critical dimension of 0.13 ⁇ m and even less, may, however, require significantly increased current densities in the individual interconnect lines despite the provision of a relatively large number of metallization layers, owing to the significant number of circuit elements per unit area.
- Operating the interconnect lines at elevated current densities may entail a plurality of problems related to stress-induced line degradation, which may finally lead to a premature failure of the integrated circuit.
- One prominent phenomenon in this respect is the current-induced material transportation in metal lines, also referred to as "electromigration,” which may lead to the formation of voids within and hillocks next to the metal line, thereby resulting in reduced performance and reliability or complete failure of the device.
- metal lines embedded into silicon dioxide and/or silicon nitride are frequently used as metal for metallization layers, wherein, as explained above, advanced integrated circuits having critical dimensions of 0.13 ⁇ m or less, may require significantly reduced cross-sectional areas of the metal lines and, thus, increased current densities, which may render aluminum less attractive for the formation of metallization layers, due to significant electromigration effects.
- silicon nitride is a dielectric material that effectively prevents the diffusion of copper atoms
- selecting silicon nitride as an interlayer dielectric material is less than desirable, since silicon nitride exhibits a moderately high permittivity, thereby increasing the parasitic capacitances of neighboring copper lines.
- a thin conductive barrier layer that also imparts the required mechanical stability to the copper is formed to separate the bulk copper from the surrounding dielectric material, and only a thin silicon nitride or silicon carbide or silicon carbonitride layer in the form of a capping layer is frequently used in copper-based metallization layers.
- barrier layer may comprise two or more sub-layers of different composition so as to meet the requirements in terms of diffusion suppressing and adhesion properties.
- damascene process first, a dielectric layer is formed that is then patterned to include trenches and vias which are subsequently Filled with copper, wherein, as previously noted, prior to filling in the copper, a conductive barrier layer is formed on the sidewalls of the trenches and vias.
- the deposition of the bulk copper material into the trenches and vias is usually accomplished by wet chemical deposition processes, such as electroplating and electroless plating, thereby requiring the reliable filling of vias with an aspect ratio of 5 and more with a diameter of approximately 0.1 ⁇ m or even less in combination with trenches having a width ranging from approximately 0.1 ⁇ m or less to several ⁇ m.
- electrochemical deposition processes for copper are well established in the field of electronic circuit board fabrication, a substantially void-free filling of high aspect ratio vias is an extremely complex and challenging task, wherein the characteristics of the finally obtained copper metal line significantly depend on process parameters, materials and geometry of the structure of interest.
- interconnect structures Since the geometry of interconnect structures is determined by the design requirements and may, therefore, not be significantly altered for a given microstructure, it is of great importance to estimate and control the impact of manufacturing processes involved in the fabrication of metallization layers and of materials, such as conductive and non-conductive barrier layers, of the copper microstructure and their mutual interaction on the characteristics of the interconnect structure so as to insure both high yield and the required product reliability.
- Empirical research results indicate that the degree of electro and stress migration may frequently -i ⁇ epend oiffhe material composition of the metal, the crystalline structure of the metal, the condition of any interfaces to neighboring materials, such as conductive and dielectric barrier layers, and the like.
- grain boundaries provide preferred diffusion paths for stress- and current-induced material transport events. Consequently, as line size reduction tends to generate smaller grains, disproportionately increased electro and stress migration may occur.
- grain boundaries may not necessarily form preferred diffusion paths in copper-based metal lines, the increased number of grain boundaries may nevertheless significantly increase the overall resistivity of the copper-based line owing to increased electron scattering at the grain boundaries. Consequently, the highly complex manufacturing process of metallization layers, including the deposition of the metal, the subsequent annealing thereof and the like, needs to be controlled in an attempt to increase performance of the metal interconnect structures with respect to electro and stress migration and/or conductivity.
- the present invention is directed to a technique for forming metal lines in metallization layers of semiconductor devices, wherein the characteristics of the metal lines with respect to electro and stress migration and/or conductivity may be improved by applying a heat treatment during and/or after the formation of the metal lines so as to enhance the electrical performance of the metal lines.
- the heat treatment may at least include a heating process performed in a sub-atmospheric and/or vacuum and/or reducing and/or inert ambient so as to promote out-gassing of contaminants that have been introduced into the metal during preceding manufacturing processes.
- the heat treatment comprises at least a heating process that is designed to vary a temperature created in the metal line along a predefined direction so as to locally generate heating zones moving along the predefined direction.
- a method comprises forming a metal line in a dielectric layer of a metallization layer of a semiconductor device, wherein the metal line extends along a length direction. Moreover, the method comprises performing a heat treatment to vary a temperature along the length direction in a timely sequential manner.
- a method comprises forming a metal line in a dielectric layer formed above a substrate comprising a semiconductor device and performing a heat treatment t» ⁇ lacJ ⁇ lfy" a 1 crystalline structure of the metal line. Additionally, the method comprises exposing the metal line to a vacuum ambient to promote out-gassing of contaminants in the metal line.
- the metal line is exposed to a reducing ambient after exposure to the vacuum ambient.
- a vacuum ambient is to be understood as an atmosphere with a reduced pressure on the order of magnitude of several Torr and significantly beyond, whereas a sub- atmospheric ambient may include pressure conditions that range from values below but close to the environmental pressure of the manufacturing facility to vacuum pressure conditions.
- Figure I schematically illustrates a semiconductor device including a metallization layer containing a plurality of metal lines, the characteristics of which with respect to electro and stress migration and/or conductivity are to be enhanced in accordance with illustrative embodiments of the present invention
- Figure Ib schematically shows a plan view of a substrate including a plurality of die areas, which in turn include a semiconductor device as shown in Figure Ia;
- FIGS. Ic and Id schematically illustrate a heat treatment, in which a temperature of metal lines varies along a length direction in a timely sequential manner in accordance with illustrated embodiments of the present invention
- Figure Ie schematically illustrates a heating process with a timely varying temperature along a length direction, which may be performed on a substrate basis according to illustrative embodiments
- FIG. 1 Figure If schematically shows the heat treatment of Figure Ie, wherein a heat transfer medium may be used in accordance with further illustrative embodiments;
- Figure 2a schematically illustrates a semiconductor device including a metallization layer formed in accordance with a damascene process during an intermediate manufacturing stage, in which the semiconductor device is subjected to a heat treatment according to illustrative embodiments of the present invention
- FIGS. 2b-2d schematically show the semiconductor device in further advanced manufacturing stages in accordance with various illustrative embodiments of the present invention.
- the present invention is directed to a technique that enables the formation of metal lines in metallization layers of even highly scaled semiconductor devices, wherein a crystalline structure of the metals and/or the degree of purity of the metal is modified by means of a heat treatment to enhance the characteristics of the metal lines with respect to the resistance to electro and stress migration and/or their inherent conductivity. Without intending to restrict the present invention to the following explanation, it is believed that the reduction of the number of grain boundaries within a metal line may significantly affect the electrical performance of the metal line in that electro and stress migration is reduced and/or the inherent conductivity is increased.
- the crystallinity of metals in metal lines of microstructures may significantly depend on the type of material used, the deposition technique used, the process parameters maintained throughout the deposition process, as well as any preceding and subsequent processes of the actual deposition of the metal.
- copper-based metallization layers are presently formed by using electrochemical deposition techniques, such as electroplating, wherein the grain size and the crystalline structure significantly depend on the deposition parameters and on the dimensions of the trenches and vias to be filled with the copper-based metal, since reduced dimensions of the trenches and vias may result in the formation of metal grains of reduced dimensions.
- electrochemical deposition techniques such as electroplating
- the grain size and the crystalline structure significantly depend on the deposition parameters and on the dimensions of the trenches and vias to be filled with the copper-based metal, since reduced dimensions of the trenches and vias may result in the formation of metal grains of reduced dimensions.
- the inherent conductivity of the copper-based metal may be reduced owing to increased charge carrier scattering at the increased number of grain boundaries.
- the electrochemical deposition into extremely scaled trenches and vias in a substantially void-free manner requires sophisticated electroplating techniques that involve highly complex electrolyte solution.
- a plurality of additives such as deposition suppressors, accelerators, complexing agents and the like, are contained in typical electrolyte solutions, which may remain to a certain degree in the metal as deposited, thereby also compromising the resulting inherent conductivity of the metal line.
- the presence of contaminants within the metal and/or the existence of a plurality of grain boundaries may also have an influence on the electro and stress migration behavior, since grain boundaries and/or the contaminants may affect the characteristics of any interfaces between the metal and adjacent materials, such as any diffusion barriers for copper.
- the grain boundaries may directly influence the stress-induced material transport as is, for instance, the case for aluminum. Consequently, by modifying the crystallinity of the metal and/or by reducing the amount of contaminants, the overall characteristics of the metal lines may be improved.
- the present invention is particularly advantageous in the context of copper- based metallization layers, since these structures are typically manufactured by the damascene process using electrochemical deposition techniques, thereby generating a large number of small grains and incorporating contaminants of the electrolyte.
- the present invention may also be applied to metal lines formed of any other appropriate materials, such as aluminum, and, thus, the present invention should not be considered as restricted to copper-based metallization layers, unless such restrictions are explicitly set forth in the appended claims.
- Figure Ia schematically shows a semiconductor device 100 comprising a substrate 101, which may have formed therein any features of microstructures, such as circuit elements of integrated circuits.
- the substrate 101 may represent any appropriate substrate for forming microstructures such as semiconductor devices.
- the substrate 101 may represent a silicon-based substrate in the form of a bulk silicon substrate or a silicon-on-insulator (SOI) substrate, as the vast majority of complex integrated circuits, such as microprocessors, storage chips, ASICs and the like, are presently manufactured on the basis of silicon.
- SOI silicon-on-insulator
- any other appropriate semiconductor materials such as silicon-based materials including semiconductor regions of different composition, such as silicon germanium, silicon carbon and the like, different crystallographic orientations, different inherent strain, or substrates including any compound semiconductor materials, such as II- VI semiconductors, III-V semiconductors and the like, may also be used.
- the semiconductor device 100 may have formed above the substrate 101 one or more metallization layers, wherein, in the exemplary embodiments shown, two metallization layers 110 and 120 are formed as a layer stack.
- the metallization layer 110 may comprise a dielectric layer 111 and a metal line 112, which is formed in the dielectric layer 111.
- the metallization layer 120 may comprise a plurality of metal lines 122 formed within a dielectric layer 121, wherein one or more of the metal lines 122 may be connected to the underlying metallization layer 110 by a via 123.
- the metal lines 122 and 112 may be comprised of any appropriate metal and may comprise, in one particular embodiment, copper, wherein additional components may, at least locally, be provided in the metal lines 122 and/or 112 so as to form a metal alloy.
- additional components may, at least locally, be provided in the metal lines 122 and/or 112 so as to form a metal alloy.
- a copper alloy may enhance the characteristics of a respective metal line in view of its resistance against electro and stress migration.
- appropriate barrier layers may be provided to prevent undue diffusion of copper into the adjacent dielectric materials of the layers 111 and 121.
- any such barrier layers are not shown in Figure Ia and may be described in more detail with reference to Figure 2a later on.
- the metal lines 122 in the layer 120 may define a width direction 124, which may characterize the lateral dimension of the metal lines 122.
- a length direction 125 may be defined by the metal lines 122, which is substantially perpendicular to the width direction 124 and is perpendicular to the drawing plane of Figure Ia.
- the metallization layer 110 may have the metal lines 112 extending in a substantially parallel manner along the "width" direction 124 so as to reduce the capacitive coupling between the lines 122 and 112. It should be appreciated that such an arrangement may be advantageous with respect to the overall performance and, as will be described later on with respect to the heat treatment for modifying the crystalline structure, a specific length direction is defined individually for each metallization layer 110, 120. In other embodiments, some or all of the metal lines 112 and 122 may define their own specific width direction 124 and length direction 125 so that a corresponding "directional" heat treatment may be performed on an individual basis.
- Figure Ib schematically shows a plan view of the substrate 101 including a plurality of die regions 130, each of which may include a semiconductor device, such as the semiconductor device 100 of Figure Ia.
- the die regions 130 are shown so as to expose the metallization layer 120, wherein the length direction
- the orientation of the metal line 122 in the drawings is of illustrative nature only and thus the length direction 125 defines the scan direction. It should further be appreciated that the dimensions of the die regions 130 with respect to the substrate dimension and, in particular, the dimensions of the metal line 122, are significantly magnified.
- the semiconductor device 100 may be formed in accordance with well-established processes, which may be described for embodiments referring to a damascene technique with reference to Figure 2a later on.
- the metal lines 112 and 122 may be formed by depositing aluminum on the basis of well-approved deposition techniques, such as chemical vapor deposition, sputter deposition and the like. Thereafter, the metal layer may be patterned by means of photolithography and well-established etch techniques, thereby forming the metal lines 112 and 122, as well as the via 123.
- a heat treatment may be performed to modify the crystalline structure of the metal lines 112, 122 as will be described in the following, or, according to other embodiments, the respective metal lines 112 and 122 may be embedded into the respective dielectric layers 111, 121 by depositing an appropriate dielectric material and planarizing the resulting topography. Irrespective of the process sequence for forming the metal lines 112, 122, illustrative embodiments for modifying the crystalline structure of the metal lines 122 and/or their amount of contaminants will now be described in more detail.
- Figure Ic schematically shows a system 150 configured to perform a heat treatment on the metal lines 122 to vary a temperature during the heat treatment along the length direction 125 in a timely sequential manner.
- the system 150 may comprise a heating source 151, which is configured to establish a locally restricted heating zone on or in the substrate 101.
- the heating source 151 may comprise a source for establishing a beam of radiation or a beam of particles to produce a locally restricted beam spot 153 on or in the substrate 101, wherein the beam spot 153 may represent an example of the locally restricted heating zone.
- the beam 152 may represent a laser beam of specified characteristics, such as wavelength, intensity and the like, to produce the required heat in the locally restricted heating zone 153.
- the heating source 151 may comprise any additional means (not shown) required for forming the beam 152 to exhibit the desired characteristics.
- corresponding beam optics such as mirrors, lenses and the like, may be provided to focus and direct the beam 152 onto a locally restricted area of the substrate 101.
- the system 150 is configured to establish a relative motion between the substrate 101 and the heating source 151 to enable a scanning motion of the locally restricted zone 153 at least along the length direction 125.
- the system 150 may comprise a moveable substrate holder 154, which is at least moveable along the length direction 125.
- the substrate holder 154 may also be moveable in other directions, such as in a further lateral direction perpendicularly to the length direction 125, and may also be movable vertically, that is, along the direction of the beam 152.
- the substrate 101 may appropriately be positioned on the substrate holder 154 to allow a relative motion substantially along the length direction 125 of at least one of the metal lines
- the length direction 125 may be defined commonly for all of the metal lines 122.
- Figure Id schematically shows an enlarged view of a portion of the metallization layer 120 with a plurality of metal lines 122 exposed to the heating source 151.
- the beam spot 153 defines the locally restricted heating zone created by the heating source 151.
- the intensity profile within the heating zone 153 may not necessarily be uniform.
- the intensity and thus temperature profile caused in the lines 122 may locally vary within the heating zone 153, depending on the scan speed, spot size and overall intensity of the beam, absorption characteristics and the like.
- the heating source 151 may be dimensioned such that a temperature within the beam spot 153 and, thus, within the locally restricted heating zone exceeds a specified target temperature which enables a reconfiguration of the crystalline structure within the portion of the metal line 122 that is affected by the beam spot 153.
- the energy deposited by the heating source 151 within the locally restricted heating zone 153 may be dimensioned such that the target temperature within the zone 153 is reached within a time interval that does not allow significant heat transportation within the metal line 122. Consequently, portions 'adjacefit hrthS bleating 1 zorfe" 153 t ⁇ f the metal line 122 are significantly colder and may substantially maintain their current crystalline structure.
- the heating zone 153 may be scanned along the length direction 125 and, therefore, sequentially heat portions of the line 122, thereby enabling the currently heated portion to take on a crystalline structure similarly to a crystalline structure generated in that portion that was heated before and that is now cooled down below the target temperature so as to "freeze" the crystalline structure obtained immediately before.
- the size of the grains within the metal lines 122 may be increased in the length direction 125, thereby significantly reducing the number of grain boundaries per unit length. For instance, in copper-based metal lines, a grain size in the length direction 125 of 10 ⁇ m or even more may be achieved.
- the extension of the locally restricted heating zone 153 in the length direction 125 may be selected to be a few micrometers or even less so as to enable an efficient reconfiguration as the zone size is less than the desired grain size.
- the scanning motion may be performed in a substantially continuous fashion, for instance by continuously moving the substrate holder 154 according to a specified speed, or, in other embodiments, a substantially stepwise motion may be created, wherein the dwell time after every step as well as the step size may be adjusted so as to obtain a desired degree of overlap between the "moving" heating zone 153.
- a corresponding motion in the lateral direction may be performed after one or more metal lines 122 are heat treated in the above described manner.
- the scan operation along the length direction 125 may be repeated once or several times with a moderate temperature created within the heating zone 153.
- a typical effective temperature of the heating zone may be selected to be approximately 100-400 0 C.
- the heat treatment with a scanned locally restricted heating zone as represented, for instance, by the beam spot 153 may be, at least partially, performed in a sub-atmospheric ambient or a vacuum ambient to simultaneously promote the out-gassing of any contaminants contained in the metal lines 122.
- the substrate holder 154 may be placed in a respective process chamber 160, which enables the establishment of an appropriate ambient and which especially allows a provision of a sub-atmospheric ambient and, in one illustrative embodiment, a vacuum ambient.
- the heating source 151 may be attached to the process chamber 160 or may be coupled to the process chamber 160 in such a way that the beam 152 may be introduced without undue losses.
- the heating source 151 may be placed, at least partially, within the respective process chamber 160.
- the substrate 101 may be pre-heated in the sub-atmospheric or vacuum ambient so as to further promote the out-gassing during the entire directional heating of all of the metal lines 122 and/or to maintain the metal lines 122 at an elevated temperature, thereby relaxing the constraints for the heating source 151 for raising the metal lines 122 exposed to the moving heating zone 153 above the target temperature.
- the heat treatment may comprise a further step, in which the metal lines 122 are exposed to a reducing gas ambient to thereby provide a substantially non-oxidized metal surface of the metal lines 122.
- a forming gas or other hydrogen mixture with inert gases such as argon, xenon, kryptorrand the IiKe'" may be introduced into the process chamber 160, wherein the pressure may range from sub- atmospheric conditions to atmospheric or elevated pressure conditions.
- the heat treatment on the basis of a reducing ambient may be performed simultaneously with the directional zone heating or may be performed after the zone heating process step.
- a first heat treatment step may be performed in a vacuum ambient, while, in one illustrative embodiment, the metal lines 122 are subjected to the directional zone heating, whereas, in other embodiments, a non-directional heating step may be performed prior to the zone heating and the vacuum ambient may be maintained during a subsequent zone heating. Thereafter, a second heat treatment, which may include a non-directional and/or a directional heating step, may be performed in the reducing ambient to enhance the purity of the metal of the lines 122.
- Figure Ie schematically shows the substrate 101 in a plan view, wherein the heating source 151 or at least a portion thereof is configured to enable the timely sequential or directional heat treatment on an extended "vertical" portion of the substrate 101 or which enables the creation of the locally restricted heating zone 153 across the entire substrate 101 in the non-scan direction, that is, in Figure Ie, the vertical direction indicated by arrow 161.
- the heating source 151 may comprise an appropriate beam optics (not shown) to shape the beam 152 in a longitudinal shape in the vertical direction.
- the heating source 151 may comprise a plurality of optical fibers (not shown) that are vertically arranged to provide a plurality of closely spaced laser beams on the substrate 101.
- the provision of a plurality of optical fibers also allows the employment of two or more individual laser sources, if the required energy for scanning substrates with large diameters, such as 200 mm or 300 mm substrates, may not be provided by a single laser.
- an appropriate focusing element such as a lens, may be provided at the end of each optical fiber to produce a desired highly focused laser beam.
- respective optical couplers may be used for efficiently coupling the laser beam and dividing the same into a plurality of optical fibers.
- the heating source 151 may also extend significantly in the lateral direction, i.e., the vertical direction in Figure Ie or the direction perpendicular to the drawing plane of Figure If, wherein heat is transferred to the plurality of metal lines 122 via a heat transfer medium 155.
- the heat transfer medium 155 may be provided in the form of a hot gas, such as hot nitrogen, or any other appropriate substantially inert gas.
- the heat transfer medium 155 may be provided in the form of vapor of an appropriate fluid having a condensation temperature that is at or above the target temperature for locally heating the metal lines 122.
- the heat transfer medium 155 when provided onto the metal lines 122, the heat transfer medium 155 may contact or condense on the metal lines 122, thereby locally transferring heat in a highly efficient manner due to the direct contact to the metal line 122 and the additional creation of latent heat.
- the heating source 151 may comprise a plurality of individual nozzles 156 or may comprise one or more elongated nozzle channels extending laterally with respect to the length direction 125 so as to form a nozzle bar or nozzle "gap" in the non-scan direction (in Figure Ie, the vertical direction).
- a single lateral gap may be provided as an elongated nozzle, thereby enabling the simultaneous treatment of a plurality of metal lines 122, depending on the lateral extension of the elongated nozzle.
- the one or more nozzles 156 may be configured to supply the heat transfer medium 155 in a highly localized manner along the length direction 125 in that the nozzle opening may have a size of approximately 1 ⁇ m and the distance 1 tb th'e'metal lin'e i ⁇ k ⁇ f 'within a range of approximately several ⁇ m.
- the heat transfer medium 155 may be provided in the form of a liquid, which may solidify after cooling down. For instance, a melted polymer material may be "deposited" in a directional manner to provide the locally restricted heating zone 153. After the heat treatment, the polymer material may be removed by well-established etch procedures.
- the heating source may transfer heat by radiation.
- the heating source 151 may comprise a heater element that is elongated in the non-scan direction, but restricted in size in the scan or length direction 125.
- the heater element may comprises a conductor, such as a wire that is connected to a corresponding power supply for heating the wire by initiating a current flow therein.
- the wire may be incorporated into an appropriate focusing system that may direct the heat radiation onto the metal lines 122, thereby forming a focus line extending along the non-scan direction.
- a scan operation with continuous or stepwise motion may be performed once, twice or several times, depending upon process and device requirements.
- a distance between the heating source 151 and metal lines 122 may be varied so as to adjust the effective temperature of the moving heating zone 153.
- the effective temperature may alternatively or additionally be adjusted by controlling the effective scan "speed," irrespective of whether a continuous or a stepwise motion is employed.
- FIG. 2a schematically shows, in a cross-sectional view, a semiconductor device 200 comprising a substrate 201 having formed thereon one or more metallization layers 210, 220.
- the same criteria apply as previously explained with reference to the substrate 101.
- At least one of the metallization layers 210, 220 may represent a copper-based metallization layer of a highly scaled semiconductor device.
- the metallization layer 210 may comprise a dielectric layer 211, which may be formed of any appropriate material, such as a low-k dielectric material and the like, and may comprise a metal line 212 comprising copper and/or any alloy thereof, wherein the metal line 212 may be separated from the dielectric layer 211 and the underlying substrate 201 by an appropriate barrier layer 217.
- the metallization layer 220 may comprise a dielectric layer 221, formed by any appropriate material, such as a low-k dielectric material and the like.
- the dielectric layer 221 comprises a plurality of trenches 226 having a lateral dimension in a width direction 224, which may be on the order of magnitude of several micrometers to 100 nm and even less in sophisticated devices.
- the trenches 226 define a length direction 225, which is substantially perpendicular to the lateral direction 224. Exposed surfaces of the dielectric layer 221 and the trenches 226 are covered by a barrier layer 227 on which is formed a seed layer 228.
- the seed layer 228 may be comprised of copper or any other appropriate material that promotes the deposition of metal within the trenches 226 in a subsequent electrochemical deposition process. In one illustrative embodiment, the seed layer 228 is comprised of substantially the same material as will be deposited in the subsequent electrochemical deposition.
- the device 200 as shown in Figure 2a may be formed by the following processes.
- the metallization layer 210 may be formed in accordance with proeess-strateg ⁇ es as "Will 'be expla'in'e' ⁇ with the formation of the layer 220. That is, an appropriate dielectric material is deposited, for instance, on the basis of well-established chemical vapor deposition (CVD) techniques and/or spin-on techniques followed by advanced photolithography and etch techniques to form the trenches 226 in the dielectric layer 221.
- CVD chemical vapor deposition
- the trenches 226 formed in the metallization layer 220 are substantially parallel to each other along the length direction 225, while for instance the metal lines 212 may also be parallel to each other but oriented along the direction 224.
- the barrier layer 227 may be formed by well-established sputter deposition techniques, atomic layer deposition (ALD), CVD and the like.
- the seed layer 228 may be formed by, for instance, sputter deposition or electroless plating and the like.
- a copper-based material may be deposited as the seed layer 228.
- the device 200 may be subjected to a heat treatment, indicated by 230, wherein the heat treatment 230 is performed in a similar fashion as is described with reference to Figures Ia-If.
- the heat treatment 230 may be performed to heat at least the seed layer 228 in a locally restricted manner, i.e., by creating a heating zone as is described with reference to Figures Ic-If, while scanning along the length direction
- a crystalline structure of the seed layer 228 may be modified to reduce the number of grain boundaries by providing an enhanced crystalline structure for the subsequent electrochemical deposition of the bulk metal.
- the heat treatment 230 may be performed in a substantially inert ambient or a reducing ambient so as to effectively suppress corrosion and discoloration of the seed layer 228.
- Figure 2b schematically shows the semiconductor device 200 in a further advanced manufacturing stage.
- the device 200 comprises metal 229 filled in the trenches 226, wherein excess metal forms a substantially closed layer above the metallization layer 220.
- the metal 229 may be comprised of copper and/or copper alloy, including components such as gold, nickel, palladium and the like.
- the metal 229 may be formed by electroplating, wherein, based on a complex electrolyte, a substantially void-free filling of the trenches 226 may be achieved. During the deposition process, contaminants in the form of accelerators, suppressors, complexing agents and the like may be incorporated into the metal 229 and would compromise the performance of the metal 229 during operation of the device 200.
- the device 200 as shown in Figure 2b is subjected to a heat treatment in an inert or sub-atmospheric or vacuum ambient 235 to promote out-gassing of contaminants contained in the metal layer 229.
- the heat treatment in the ambient 235 may be designed to also preheat the substrate 201 to a specified temperature to enhance the efficiency of a subsequent heat treatment for modifying the crystalline structure of the metal 229, that is, the substrate 201 may be heated to a temperature below the target temperature for a heat treatment for modifying the crystalline structure.
- the device 200 may be subjected to a heat treatment to create locally restricted heating zones along the length direction 225, as is also described with respect to Figures Ic-If.
- the directional heat treatment may be performed after a certain amount of metal is filled in the lines 122.
- the fill process may be interrupted to perform the directional heat treatment in any appropriate manner as described above. Thereafter, the fill process may be resumed.
- the crystallinity of the metal in the partially filled metal lines 122 may be improved during the fill process and also the out-gassing of contaminants may be enhanced.
- such an intermediate direeticttial heat itfeatffle ⁇ it may more than one time to enhance the overall efficiency.
- a directional heat treatment may or may not be performed immediately after completion of the seed layer 228.
- the crystalline structure of the metal layer 229 may efficiently be modified to reduce the number of grain boundaries as is also previously described.
- the heat treatment 230 and/or the treatment within the ambient 235 and/or the heat treatment scanned along the length direction 225 on the basis of the metal layer 229 may be omitted, and the substrate 200 as shown in Figure 2b may be subjected to a process for removing any excess metal of the layer 229.
- an electrochemical removal process and/or a chemical mechanical polishing (CMP) process may be performed to remove the excess metal and the barrier layer 227 on horizontal surfaces of the layer 220.
- CMP chemical mechanical polishing
- the heat treatment may be performed to sequentially heat restricted portions of the metal lines along the length direction 225 as is described previously with reference to Figures Ic-If.
- the heat treatment may be performed within the ambient 235 to simultaneously promote the out-gassing of contaminants, wherein a pre-heating may also be performed to maintain the substrate 201 at a specified elevated temperature throughout the entire directional heat treatment.
- a heat treatment may be performed, in which the device 200 is exposed to the vacuum ambient
- the heat treatment including at least one step with the vacuum ambient 235 and a further step with a reducing ambient may be combined with a directional zone heating as also described above with reference to Figures Ia-If and Figure 2a, whereas, in other embodiments, the zone heating may be omitted, when the improvement in conductivity due to an enhanced purity of the metal lines is considered sufficient.
- the dielectric layer 221 may be comprised of a low-k material, such as SiCOH, MSQ, HSQ, SiLK and the like, which inherently exhibits a reduced mechanical stability after formation compared to well-approved dielectrics, such as silicon dioxide, fluorine-doped silicon dioxide, silicon nitride and the like.
- a low-k material such as SiCOH, MSQ, HSQ, SiLK and the like, which inherently exhibits a reduced mechanical stability after formation compared to well-approved dielectrics, such as silicon dioxide, fluorine-doped silicon dioxide, silicon nitride and the like.
- the dielectric layer 221 may also be treated, at least in the vicinity of the metal lines 222.
- the mechanical characteristics, such as the hardness may be improved, as the hardness of some low-k materials may significantly increase upon treatment with, for instance, a laser beam.
- the treatment of the dielectric layer 221 may be performed on substantially all exposed surface portions of the dielectric layer 221, thereby providing the potential for improving the overall stability of a metallization layer stack including low-k dielectric materials.
- the heating source such as the source 151, for creating localized heating zones that are scanned along the length direction 225 may provide an irradiation beam, the absorption of which and thus whose efficiency of heat transfer may depend on beam characteristics such as wavelength, particle energy and the like.
- the wavelength of a laser source may result in a moderately high reflectivity on metal, thereby reducing the efficiency of energy transfer from the beam to the metal.
- a heat transfer layer may be formed prior to the directional heat treatment, wherein the characteristics of the heat transfer layer are selected so as to allow a moderately high energy deposition within the layer, thereby providing an enhanced heat transfer to the underlying metal.
- FIG. 2c schematically shows the device 200 after the above-described sequence for removing excess material of the layer 229 and after the formation of a heat transfer layer 236.
- the heat transfer layer 236 may be comprised of any appropriate dielectric material, such as a polymer material and the like, having characteristics so as to absorb a significant portion of a beam 237, which is designed to create a heating zone 238, which is locally restricted in the length direction 225, i.e., the direction perpendicular to the drawing plane of Figure 2c, while in the lateral direction 224, the heating zone 238 may span over a plurality of metal lines 222.
- the thickness and the extinction coefficient of the heat transfer layer 236 may be designed so as to absorb a high degree of radiation intensity.
- the heat transfer layer 236 may be formed in accordance with well-established deposition techniques, such as PECVD, spin-on techniques and the like. After the formation, the heat treatment on the basis of the beam 237 may be performed to modify the crystalline structure of the metal lines 222.
- the provision of the heat transfer layer 236 may also be advantageous in that a direct contact of the heat transfer medium with the metal lines 222 is prevented. Consequently, a plurality of heat transfer medium, such as super-heated water vapor, may be used without adversely affecting the metal lines 222.
- Figure 2d schematically shows the device 200 after the removal of the heat transfer layer 236, which may be accomplished by any appropriate and well-established technique, such as isotropic etching, plasma etching and the like.
- the ambient 235 representing a sub- atmospheric ambient or a vacuum ambient may be established to promote the out-gassing of any contaminants that may have been incorporated during the electrochemical deposition and/or during the formation and removal of the heat transfer layer 236.
- the ambient 235 may be modified to include a reducing atmosphere for further enhancing the purity of the metal lines 222.
- the present invention provides a technique that enables the formation of metal lines of increased electrical performance characteristics in that the metal is provided with enhanced purity and/or the crystallinity of the metal is modified.
- the modification of the crystallinity may be performed on the basis of a heat treatment including the heating of a locally restricted zone, wherein the locally heated zone is scanned along a length direction of the metal line to reduce the number of grain boundaries in this direction.
- the heat treatment with localized heating zones scanned along the length direction may effectively be combined with a heat treatment in a sub-atmospheric ambient, a vacuum ambient and a reducing ambient to promote out-gassing of any contaimnai ⁇ ts withffl'the metal 'lines 1 .
- a vacuum ambient may be established during a first phase of the heat treatment and a reducing ambient may be established in a second final phase of the heat treatment, wherein this heat treatment including at least these two ambients may be performed without a directional zone heating or may be combined with a directional zone heating.
- the zone heating may be performed, at least partially, with the vacuum ambient being established and/or, at least partially, with the reducing ambient being established.
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Abstract
Description
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GB0720857A GB2439884B (en) | 2005-03-31 | 2006-03-30 | Heat treatment for forming interconnect structures with reduced electro and stress migration and/or resistivity |
KR1020077025025A KR101273929B1 (en) | 2005-03-31 | 2006-03-30 | Heat treatment for forming interconnect structures with reduced electro and stress migration and/or resistivy |
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DE102005014751 | 2005-03-31 | ||
DE102005014751.8 | 2005-03-31 | ||
DE102005020061.3A DE102005020061B4 (en) | 2005-03-31 | 2005-04-29 | Technique for making interconnect structures with reduced electrical and stress migration and / or lower resistance |
DE10205020061.3 | 2005-04-29 | ||
US11/292,537 | 2005-12-02 | ||
US11/292,537 US7375031B2 (en) | 2005-04-29 | 2005-12-02 | Technique for forming interconnect structures with reduced electro and stress migration and/or resistivity |
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WO2006105320A1 true WO2006105320A1 (en) | 2006-10-05 |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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EP0225592A2 (en) * | 1985-12-04 | 1987-06-16 | Fujitsu Limited | Recrystallizing conductive films |
US6495453B1 (en) * | 1999-06-22 | 2002-12-17 | Interuniversitair Microelectronica Centrum | Method for improving the quality of a metal layer deposited from a plating bath |
DE10217876A1 (en) * | 2002-04-22 | 2003-11-06 | Infineon Technologies Ag | Process for the production of thin metal-containing layers with low electrical resistance |
US20040104481A1 (en) * | 2002-12-02 | 2004-06-03 | Applied Materials, Inc. | Method for recrystallizing metal in features of a semiconductor chip |
Family Cites Families (2)
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US6303476B1 (en) * | 2000-06-12 | 2001-10-16 | Ultratech Stepper, Inc. | Thermally induced reflectivity switch for laser thermal processing |
US20040010448A1 (en) * | 2002-07-12 | 2004-01-15 | Miller William E. | System and method for marketing advertising space on disposable consumer items |
-
2006
- 2006-03-30 GB GB0720857A patent/GB2439884B/en not_active Expired - Fee Related
- 2006-03-30 KR KR1020077025025A patent/KR101273929B1/en not_active IP Right Cessation
- 2006-03-30 WO PCT/US2006/011695 patent/WO2006105320A1/en active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0225592A2 (en) * | 1985-12-04 | 1987-06-16 | Fujitsu Limited | Recrystallizing conductive films |
US6495453B1 (en) * | 1999-06-22 | 2002-12-17 | Interuniversitair Microelectronica Centrum | Method for improving the quality of a metal layer deposited from a plating bath |
DE10217876A1 (en) * | 2002-04-22 | 2003-11-06 | Infineon Technologies Ag | Process for the production of thin metal-containing layers with low electrical resistance |
US20040104481A1 (en) * | 2002-12-02 | 2004-06-03 | Applied Materials, Inc. | Method for recrystallizing metal in features of a semiconductor chip |
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GB0720857D0 (en) | 2007-12-05 |
KR101273929B1 (en) | 2013-06-11 |
GB2439884A (en) | 2008-01-09 |
KR20080002899A (en) | 2008-01-04 |
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