KR100510914B1 - Method of manufacturing a semiconductor device - Google Patents
Method of manufacturing a semiconductor device Download PDFInfo
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- KR100510914B1 KR100510914B1 KR10-2003-0049470A KR20030049470A KR100510914B1 KR 100510914 B1 KR100510914 B1 KR 100510914B1 KR 20030049470 A KR20030049470 A KR 20030049470A KR 100510914 B1 KR100510914 B1 KR 100510914B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 층간 절연막에 다마신(Damascene) 공정으로 콘택홀 또는 트렌치를 형성한 후 장벽 금속층을 형성하기 전에 다마신 공정 시 발생된 식각 손상을 보상하면서 절연막에 흡착된 수분을 제거하고 절연막에 포함된 원소들의 결합력을 증가시킴으로써, 절연막의 유전율이 증가하는 것을 억제하고 공정의 신뢰성 및 소자의 전기적 특성을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a semiconductor device, wherein after forming a contact hole or a trench in an interlayer insulating film and then forming a contact hole or trench, and before forming the barrier metal layer, adsorption on the insulating film is performed while compensating for etch damage generated during the damascene process. By removing the moisture and increasing the bonding strength of the elements included in the insulating film, it is possible to suppress the increase in the dielectric constant of the insulating film and to improve the reliability of the process and the electrical characteristics of the device.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 층간 절연막의 유전율이 증가하는 것을 방지할 수 있는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing an increase in dielectric constant of an interlayer insulating film.
반도체 소자의 금속 배선으로는 알루미늄이나 구리가 많이 사용되고 있다. As metal wiring of a semiconductor element, aluminum and copper are used a lot.
이중에서도 알루미늄은 표면에 매우 안정된 산화막이 형성되기 때문에 소자 구동 시 다량의 전자 이동에 의한 원자의 이동이 주로 그레인 바운더리(Grain boundary)를 따라 진행된다. 따라서, 그레인 바운더리를 줄이면 우수한 EM(Electro Migration) 특성을 기대할 수 있었다. 그럼에도 불구하고 알루미늄(Al) 대신에 구리(Cu)를 사용하는 이유는 비저항이 낮고, RC 지연(Delay)을 감소시킬 수 있기 때문이다. Among them, aluminum has a very stable oxide film formed on its surface, so that the movement of atoms due to the large amount of electron movement during the driving of the device mainly proceeds along the grain boundary. Therefore, it was possible to expect excellent EM (Electro Migration) characteristics by reducing the grain boundary. Nevertheless, the reason why copper (Cu) is used instead of aluminum (Al) is that the specific resistance is low and the RC delay can be reduced.
배선 폭이 점차 줄어듦에 따라 배선의 신뢰성을 평가함에 있어서 EM 특성이 매우 중요한 요소로 작용을 한다. 구리는 융점이 약 1085℃로 높기 때문에, 초기에는 구리의 EM 특성이 우수할 것으로 예상되었다. 하지만, 실제 공정에서는 상반된 특성을 보이는 것으로 알려져 있다. As the wiring width gradually decreases, the EM characteristic plays an important role in evaluating the reliability of the wiring. Since copper has a high melting point of about 1085 ° C., it was initially expected that the EM properties of copper would be excellent. However, in the actual process it is known to show the opposite characteristics.
그럼에도 불구하고, 구리를 이용하여 금속 배선을 형성하는 이유 중 하나는, 구리 자체의 비저항보다는 유전율이 낮은(Low-k) 절연막을 적용할 수 있다는 것이다. 저유전율 절연막은 절연막 자체의 특성도 중요하지만, 듀얼 다마신(Dual Damascene) 공정을 적용할 수 있는지의 여부가 집적(Integration) 측면에서 더욱 중요하다고 할 수 있다.Nevertheless, one of the reasons for forming metal wiring using copper is that an insulating film having a lower dielectric constant (Low-k) than that of copper itself can be applied. Although the low dielectric constant insulating film is also important in the characteristics of the insulating film itself, whether or not to apply the dual damascene (Dual Damascene) process can be said to be more important in terms of integration (Integration).
하지만, 저유전율 절연막을 적용하는데 있어서 가장 큰 문제점 중 하나는, 식각 화학제(Etch chemical)에 의한 손상이 발생된다는 것이다. 예를 들어, OSG(Organosilicateglass) 재료를 구성하고 있는 Si-O-C-H 결합에서 식각 화학제에 의해 표면에 있는 C가 결핍(Depletion)되어 유전율 값(k)이 증가하게 된다. 또한, 식각 공정에서 혼입되는 불순물 원소들이 후속 열처리 시 구리 또는 장벽 금속(Barrier metal)과 반응하여 수율이 저하되는 문제점이 발생된다. However, one of the biggest problems in applying the low dielectric constant insulating film is that damage caused by etching chemicals occurs. For example, in the Si-O-C-H bonds constituting the OSG (Organosilicateglass) material, the C on the surface is depleted by the etching chemical to increase the dielectric constant value (k). In addition, the impurity elements to be mixed in the etching process reacts with the copper or barrier metal during the subsequent heat treatment, a problem that the yield is lowered.
이러한 문제점은 구리를 이용한 금속 배선 형성 공정에서 뿐만 아니라, 저유전율 절연막을 사용하는 모든 반도체 제조 공정에서 발생되고 있다.This problem has arisen not only in the metal wiring formation process using copper, but also in all the semiconductor manufacturing processes using the low dielectric constant insulating film.
이에 대하여, 본 발명이 제시하는 반도체 소자의 제조 방법은 층간 절연막에 다마신(Damascene) 공정으로 콘택홀 또는 트렌치를 형성한 후 장벽 금속층을 형성하기 전에 다마신 공정 시 발생된 식각 손상을 보상하면서 절연막에 흡착된 수분을 제거하고 절연막에 포함된 원소들의 결합력을 증가시킴으로써, 절연막의 유전율이 증가하는 것을 억제하고 공정의 신뢰성 및 소자의 전기적 특성을 향상시킬 수 있다. In contrast, the method of fabricating a semiconductor device according to the present invention provides an insulating film while compensating for etch damage generated during the damascene process after forming a contact hole or a trench in the interlayer insulating film by a damascene process and before forming the barrier metal layer. By removing the moisture adsorbed on and increasing the bonding strength of the elements included in the insulating film, it is possible to suppress the increase in the dielectric constant of the insulating film and to improve the reliability of the process and the electrical characteristics of the device.
본 발명의 실시예에 따른 반도체 소자의 제조 방법은 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체 기판 상에 층간 절연막을 형성하는 단계와, 층간 절연막에 콘택홀 및 트렌치를 형성하는 단계와, 탄소 함유 가스 분위기에서 열처리 또는 플라즈마 처리 공정을 실시하여 층간 절연막을 표면 처리하거나, 또는 층간 절연막을 형성하기 위하여 사용된 소오스 가스와 반응 가스를 다시 공급하여 전체 표면상에 탄소 성분이 보충된 절연막을 형성하여 층간 절연막을 표면 처리하는 단계를 포함한다.A method of manufacturing a semiconductor device according to an embodiment of the present invention comprises the steps of forming an interlayer insulating film on a semiconductor substrate formed with a number of elements for forming a semiconductor device, forming a contact hole and a trench in the interlayer insulating film, and containing carbon Heat treatment or plasma treatment process is performed in a gas atmosphere, or the interlayer insulating film is subjected to surface treatment, or the source gas and the reactive gas used to form the interlayer insulating film are supplied again to form an insulating film supplemented with carbon components on the entire surface. Surface treating the insulating film.
상기에서, 층간 절연막을 OSG로 형성할 수 있다. In the above, the interlayer insulating film can be formed of OSG.
상기에서, 탄소 함유 가스로 CO 가스 또는 CO2 가스를 사용할 수 있다.In the above, CO gas or CO 2 gas may be used as the carbon-containing gas.
상기에서, 표면 처리를 실시한 후, 반도체 기판 상에 형성된 절연막을 제거하는 단계를 더 포함한다.In the above, after the surface treatment is performed, the method further includes removing the insulating film formed on the semiconductor substrate.
한편, 표면 처리를 실시한 후, 반도체 기판 표면의 불순물이나 자연 산화막을 플라즈마 전세정 모듈로 제거하는 단계를 더 포함할 수 있다. 이때, 불순물이나 자연 산화막은 반도체 기판에 약 13.56MHz의 RF 제너레이터를 이용하여 50W 내지 1000W의 RF 파워를 인가한 상태에서 제거하는 것이 바람직하다.Meanwhile, after the surface treatment is performed, the method may further include removing impurities or a native oxide film on the surface of the semiconductor substrate with a plasma pre-cleaning module. At this time, it is preferable that the impurity or the native oxide film is removed in the state where RF power of 50 W to 1000 W is applied to the semiconductor substrate by using an RF generator of about 13.56 MHz.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 본 발명의 범위가 다음에 상술하는 실시예에 한정되는 것은 아니다. 단지 본 실시예는 본 발명의 개시가 완전하도록 하며 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이며, 본 발명의 범위는 본원의 특허 청구 범위에 의해서 이해되어야 한다. Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.
한편, 어떤 막이 다른 막 또는 반도체 기판의 '상'에 있다라고 기재되는 경우에 상기 어떤 막은 상기 다른 막 또는 반도체 기판에 직접 접촉하여 존재할 수 있고, 또는 그 사이에 제3의 막이 개재되어질 수도 있다. 또한 도면에서 각 층의 두께나 크기는 설명의 편의 및 명확성을 위하여 과장되었다. 도면 상에서 동일 부호는 동일한 요소를 지칭한다.On the other hand, when a film is described as being "on" another film or semiconductor substrate, the film may exist in direct contact with the other film or semiconductor substrate, or a third film may be interposed therebetween. In the drawings, the thickness or size of each layer is exaggerated for clarity and convenience of explanation. Like numbers refer to like elements on the drawings.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도들이다.1A through 1D are cross-sectional views of devices for describing a method for forming metal wires in a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 트랜지스터, 플래시 메모리 셀 또는 금속 배선과 같이 반도체 소자를 형성하기 위한 여러 요소(도시되지 않음)가 형성된 반도체 기판(101) 상에 층간 절연막(102)을 형성한다. 층간 절연막(102)은 유전율을 낮추기 위하여 유전 상수(k)가 1 내지 2.9인 저유전율 절연막으로 형성하며, 예를 들면 OSG(Organosilicateglass)로 층간 절연막(102)을 형성할 수 있다.Referring to FIG. 1A, an interlayer insulating film 102 is formed on a semiconductor substrate 101 on which various elements (not shown) for forming a semiconductor device, such as a transistor, a flash memory cell, or a metal wiring, are formed. In order to lower the dielectric constant, the interlayer insulating film 102 may be formed of a low dielectric constant insulating film having a dielectric constant k of 1 to 2.9. For example, the interlayer insulating film 102 may be formed of OSG (Organosilicateglass).
이어서, 다마신(Damasceme) 공정으로 층간 절연막(102)에 콘택홀(103) 또는 트렌치(도시되지 않음)를 형성한다. 이때, 층간 절연막(102)의 표면에는 다마신 공정 시 사용된 식각제에 의하여 손상층이 발생된다. Subsequently, a contact hole 103 or a trench (not shown) is formed in the interlayer insulating layer 102 by a damascene process. At this time, the damage layer is generated on the surface of the interlayer insulating film 102 by the etchant used during the damascene process.
도 1b를 참조하면, 다마신 공정 시 발생된 식각 손상을 보상하면서 층간 절연막(102)에 흡착된 수분을 제거하고 층간 절연막(102)에 포함된 원소들의 결합력을 증가시키기 위하여 표면 처리를 실시한다. Referring to FIG. 1B, a surface treatment is performed to remove moisture adsorbed on the interlayer insulating layer 102 and to increase the bonding force of elements included in the interlayer insulating layer 102 while compensating for the etching damage generated during the damascene process.
이때, 층간 절연막(102)이 OSG로 형성된 경우에는, OSG를 구성하는 Si-O-C-H 결합에서 C 성분이 다마신 공정에서 사용되는 식각제에 의해 결핍(Depletion)되어 유전율이 증가된다. At this time, when the interlayer insulating film 102 is formed of OSG, the C component in the Si-O-C-H bond constituting the OSG is depleted by the etchant used in the damascene process to increase the dielectric constant.
따라서, 표면 처리는 식각 손상을 보상하고 층간 절연막(102)에 흡착된 수분을 제거하면서, C 성분을 보충하고 결합력이 증가되도록 탄소 함유 가스 분위기에서 열처리 공정이나 플라즈마 처리 공정을 진행하는 것이 바람직하다. 이때, 탄소 함유 가스로는 CO 가스 또는 CO2 가스를 사용할 수 있다. 이렇게, 탄소 함유 가스 분위기에서 열처리 공정이나 플라즈마 처리 공정으로 표면 처리를 실시하면, 식각 손상이 보상될 뿐만 아니라, 층간 절연막(102)으로 탄소 성분이 보충되면서 내부의 결합력도 증가하여 유전율이 증가되는 것을 방지할 수 있다.Therefore, the surface treatment preferably compensates for the etching damage and removes the moisture adsorbed on the interlayer insulating film 102, while performing a heat treatment process or a plasma treatment process in a carbon-containing gas atmosphere to supplement the C component and increase the bonding force. At this time, CO gas or CO 2 gas may be used as the carbon-containing gas. In this way, when the surface treatment is performed in a heat treatment process or a plasma treatment process in a carbon-containing gas atmosphere, not only the etching damage is compensated, but also the carbon content is supplemented with the interlayer insulating film 102, thereby increasing the internal bonding force, thereby increasing the dielectric constant. You can prevent it.
표면 처리를 실시하는 또 다른 방법으로는, 도 2에 도시된 바와 같이, 층간 절연막(102)을 형성하기 위하여 사용된 소오스 가스와 반응 가스를 저압(예를 들면, 10-3Torr 내지 10Torr)에서 다시 공급하면서 표면 처리를 실시할 수도 있다. 이 경우에는, 다마신 공정에 의해 콘택홀 또는 트렌치가 형성된 상태에서 전체 표면에 절연막(104)이 다시 형성되기 때문에 식각 손상이 없고 C 성분이 충분하면서 결합력이 우수한 절연막(104)을 형성할 수 있다. 한편, 절연막(104)은 반도체 기판(101) 상에도 형성되기 때문에, 도 2b에 도시된 바와 같이, 불활성 기체(예를 들면, Ar)를 이용한 플라즈마 식각 방식으로 반도체 기판(101) 상부의 절연막(104)을 제거해야 한다.As another method of performing the surface treatment, as shown in FIG. 2, the source gas and the reactant gas used to form the interlayer insulating film 102 may be formed at low pressure (eg, 10 −3 Torr to 10 Torr). The surface treatment may be performed while supplying again. In this case, since the insulating film 104 is formed on the entire surface in the state where the contact hole or the trench is formed by the damascene process, it is possible to form the insulating film 104 without etching damage and sufficient C component and excellent bonding force. . On the other hand, since the insulating film 104 is also formed on the semiconductor substrate 101, as shown in Figure 2b, the insulating film on the semiconductor substrate 101 by a plasma etching method using an inert gas (for example, Ar) 104) must be removed.
이로써, 표면 처리로 식각 손상을 보상하고 C 성분을 보충하면서 결합력을 강화시켜 유전율이 낮고 막질이 우수한 층간 절연막(102)을 형성할 수 있다. 이러한 표면 처리는 150℃ 내지 450℃의 온도에서 30초 내지 30분 동안 실시하는 것이 바람직하다.As a result, the interlayer insulating film 102 having a low dielectric constant and excellent film quality may be formed by compensating for the etching damage through surface treatment and reinforcing the C component while supplementing the C component. Such surface treatment is preferably carried out for 30 seconds to 30 minutes at a temperature of 150 ℃ to 450 ℃.
도 1c를 참조하면, 전체 표면에 장벽 금속층(Barrier metal layer; 105)을 형성한다. 이때, 장벽 금속층(105)은 화학기상 증착법이나 단원자 증착법으로 형성할 수 있으며, Ta, TaN, TaC, WN, TiN, TiNSi, TiW, WBN 또는 WC를 20Å 내지 1000Å의 두께로 증착하여 형성할 수 있다. Referring to FIG. 1C, a barrier metal layer 105 is formed on the entire surface. In this case, the barrier metal layer 105 may be formed by chemical vapor deposition or monoatomic deposition, and may be formed by depositing Ta, TaN, TaC, WN, TiN, TiNSi, TiW, WBN, or WC in a thickness of 20 kV to 1000 kV. have.
한편, 장벽 금속층(105)을 형성하기 전에, 콘택홀(103)을 통해 노출된 반도체 기판(101)의 표면에 잔류하는 불순물이나 자연 산화막을 제거해주는 것이 바람직하다. 이때, 불순물이나 자연 산화막은 플라즈마 전세정 모듈(Plasma preclean module)을 사용한다. 좀 더 구체적으로 설명하면, 기판에 약 13.56MHz의 RF 제너레이터를 이용하여 50W 내지 1000W의 RF 파워를 인가한 상태에서 불순물이나 자연 산화막을 제거할 수 있다.Meanwhile, before the barrier metal layer 105 is formed, it is preferable to remove impurities or natural oxide films remaining on the surface of the semiconductor substrate 101 exposed through the contact hole 103. At this time, the impurity or natural oxide film uses a plasma preclean module. More specifically, it is possible to remove impurities or natural oxide film while RF power of 50W to 1000W is applied to the substrate by using the RF generator of about 13.56MHz.
도 1d를 참조하면, 콘택홀(103) 또는 트렌치를 전도성 물질로 매립하여 금속 배선(106)을 형성한다. 이때, 금속 배선(106)은 전체 상부에 시드층(도시되지 않음)을 먼저 형성하고 전기 도금법을 이용하여 콘택홀(103) 또는 트렌치를 전도성 물질로 매립하여 형성할 수도 있다.Referring to FIG. 1D, the contact hole 103 or the trench is filled with a conductive material to form the metal wiring 106. In this case, the metal wire 106 may be formed by first forming a seed layer (not shown) on the entire upper part and filling the contact hole 103 or the trench with a conductive material by using an electroplating method.
상술한 바와 같이, 본 발명은 층간 절연막에 다마신(Damascene) 공정으로 콘택홀 또는 트렌치를 형성한 후 장벽 금속층을 형성하기 전에 다마신 공정 시 발생된 층간 절연막의 식각 손상을 보상하고, 탄소 성분을 보충하면서 절연막에 흡착된 수분을 제거하고 절연막에 포함된 원소들의 결합력을 증가시킴으로써, 절연막의 유전율이 증가하는 것을 억제하고 공정의 신뢰성 및 소자의 전기적 특성을 향상시킬 수 있다.As described above, the present invention compensates for the etch damage of the interlayer insulating film generated during the damascene process after forming the contact hole or trench in the interlayer insulating film by the damascene process and before forming the barrier metal layer. By replenishing the water adsorbed on the insulating film and increasing the bonding strength of the elements contained in the insulating film, the dielectric constant of the insulating film can be suppressed from increasing and the reliability of the process and the electrical characteristics of the device can be improved.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위한 소자의 단면도들이다.1A to 1D are cross-sectional views of devices for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 2a 및 도 2b는 본 발명의 다른 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위한 소자의 단면도들이다.2A and 2B are cross-sectional views of devices for describing a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
101 : 반도체 기판 102 : 층간 절연막101 semiconductor substrate 102 interlayer insulating film
102a : 식각 손상층 103 : 콘택홀102a: etching damaged layer 103: contact hole
104 : 절연막 105 : 장벽 금속층104: insulating film 105: barrier metal layer
106 : 금속 배선106: metal wiring
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