KR100576506B1 - Method of forming a copper wiring in a semiconductor device - Google Patents

Method of forming a copper wiring in a semiconductor device Download PDF

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KR100576506B1
KR100576506B1 KR1020000036526A KR20000036526A KR100576506B1 KR 100576506 B1 KR100576506 B1 KR 100576506B1 KR 1020000036526 A KR1020000036526 A KR 1020000036526A KR 20000036526 A KR20000036526 A KR 20000036526A KR 100576506 B1 KR100576506 B1 KR 100576506B1
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film
copper
forming
copper film
layer
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KR20020002085A (en
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김헌도
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

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Abstract

본 발명은 반도체 소자의 구리 배선 형성 방법에 관한 것으로, PVD 방법으로 제 1 구리막을 형성하고 촉매로 작용하는 요오드 화합물을 도포한 후 CVD 방법으로 제 2 구리막을 형성하여 콘택의 매립 특성을 향상시키고, PVD 방법 또는 전기 화학적 방법으로 제 3 구리막을 형성한 후 CMP 공정을 실시하여 구리 배선을 형성함으로써 구리막의 층덮힘 특성을 개선할 수 있는 반도체 소자의 구리 배선 형성 방법이 제시된다.
The present invention relates to a method for forming a copper wiring of a semiconductor device, to form a first copper film by the PVD method and to apply the iodine compound acting as a catalyst, and then to form a second copper film by the CVD method to improve the buried characteristics of the contact, A method for forming a copper wiring of a semiconductor device, which can improve layer covering characteristics of a copper film by forming a copper wiring by forming a third copper film by a PVD method or an electrochemical method, and then performing a CMP process.

구리 배선, PVD 제 1 구리막, 요오드 촉매, CVD 제 2 구리막, PVD 제 3 구리막Copper wiring, PVD first copper film, iodine catalyst, CVD second copper film, PVD third copper film

Description

반도체 소자의 구리 배선 형성 방법{Method of forming a copper wiring in a semiconductor device} Method of forming a copper wiring in a semiconductor device             

도 1은 종래의 반도체 소자의 구리 배선 형성 방법을 설명하기 위한 소자의 단면도.BRIEF DESCRIPTION OF THE DRAWINGS The cross section of the element for demonstrating the copper wiring formation method of the conventional semiconductor element.

도 2(a) 내지 도 2(d)는 본 발명에 따른 반도체 소자의 구리 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.
2 (a) to 2 (d) are cross-sectional views of devices sequentially shown in order to explain a method for forming a copper wiring of a semiconductor device according to the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

11 및 21 : 반도체 기판 12 및 22 : 절연막11 and 21: semiconductor substrate 12 and 22: insulating film

13 및 23 : 확산 방지막 14 : 시드층13 and 23: diffusion barrier 14: seed layer

15 : 구리막 16 : 구리 원자15 copper film 16: copper atom

17 : 보이드 18 : 구리 산화막17: void 18: copper oxide film

24 : 제 1 구리막 25 : 제 2 구리막24: first copper film 25: second copper film

26 : 요오드층 27 : 제 3 구리막
26: iodine layer 27: third copper film

본 발명은 반도체 소자의 구리 배선 형성 방법에 관한 것으로, 특히 PVD 방법으로 제 1 구리막을 형성하고 촉매로 작용하는 요오드 화합물을 도포한 후 CVD 방법으로 제 2 구리막을 형성하여 콘택의 매립 특성을 향상시키고 PVD 방법 또는 전기 화학적 방법으로 제 3 구리막을 형성한 후 CMP 공정을 실시하여 구리 배선을 형성함으로써 구리막의 층덮힘 특성을 개선할 수 있는 반도체 소자의 구리 배선 형성 방법에 관한 것이다.
The present invention relates to a method for forming a copper wiring of a semiconductor device, and in particular, to form a first copper film by PVD method and to apply the iodine compound acting as a catalyst and then to form a second copper film by CVD method to improve the buried characteristics of the contact The present invention relates to a method for forming a copper wiring of a semiconductor device capable of improving layer covering characteristics of a copper film by forming a copper wiring by forming a third copper film by a PVD method or an electrochemical method and then performing a CMP process.

종래의 반도체 소자의 구리 배선 형성 방법을 도 1을 이용하여 설명하면 다음과 같다.The copper wiring forming method of the conventional semiconductor device will be described with reference to FIG. 1 as follows.

소정의 구조가 형성된 반도체 기판(11) 상부에 절연막(12)을 형성한다. 절연막(12)의 소정 영역을 듀얼 다마신 공정으로 패터닝하여 반도체 기판(11)의 소정 영역을 노출시키는 콘택 홀을 형성한다. 콘택 홀을 포함한 전체 구조 상부에 PVD 방법으로 확산 방지막(13)을 형성한다. 그리고, 그 상부에 PVD 방법으로 시드층 (14)을 형성한다. 트렌치가 완전히 매립되도록 전기 화학적 증착 방법으로 구리막 (15)을 형성한다. 그리고 구리막(15)에 열처리 공정을 실시한 후 CMP 공정으로 연마하여 구리 배선을 형성한다.
An insulating film 12 is formed over the semiconductor substrate 11 having a predetermined structure. A predetermined region of the insulating film 12 is patterned by a dual damascene process to form a contact hole exposing a predetermined region of the semiconductor substrate 11. The diffusion barrier 13 is formed on the entire structure including the contact hole by the PVD method. And the seed layer 14 is formed in the upper part by PVD method. The copper film 15 is formed by an electrochemical deposition method so that the trench is completely buried. The copper film 15 is subjected to a heat treatment step and then polished by a CMP process to form a copper wiring.

상기와 같은 공정에 의해 구리 배선을 형성할 경우 PVD 방법으로 형성하는 확산 방지막 및 시드층은 소자의 고집적화에 따라 확산 방지막과 시드층의 층덮힘 특성이 열화된다. 이에 따라 확산 방지막의 역할을 하지 못하거나 확산 방지막을 통해 절연막으로 구리 원자(16)가 확산해 들어가고, 전기 화학적 증착으로 구리층을 형성할 때 보이드(17)를 형성시켜 배선의 신뢰성에 악영향을 미치게 된다. 그리고, 확산 방지막과 시드층을 증착한 후 전기 화학적 증착으로 구리층을 형성할 때 진공의 파괴가 일어나 시드층에 구리 산화막이 형성되어 구리층을 전기 화학적으로 증착한 이후에도 일부 구리 산화막(18)이 배선 내부에 존재하여 신뢰성에 악영향을 준다. 또한, 전기 화학적 증착으로 형성되는 구리층은 많은 첨가제를 이용하여 형성되기 때문에 증착된 구리층에 많은 불순물들이 존재하여 이 또한 구리 금속층에 악영향을 미친다.When the copper wiring is formed by the above process, the diffusion barrier film and the seed layer formed by the PVD method deteriorate the layer covering properties of the diffusion barrier film and the seed layer according to the high integration of the device. Accordingly, the copper atoms 16 do not function as diffusion barriers or diffuse into the insulating layer through the diffusion barriers, and when the copper layer is formed by electrochemical deposition, voids 17 are formed to adversely affect the reliability of the wiring. do. In addition, when the copper layer is formed by electrochemical vapor deposition after the diffusion barrier layer and the seed layer are deposited, a vacuum breakage occurs to form a copper oxide layer on the seed layer, and even after the copper layer is electrochemically deposited, some copper oxide layers 18 are formed. It exists inside the wiring and adversely affects reliability. In addition, since the copper layer formed by electrochemical deposition is formed using many additives, many impurities are present in the deposited copper layer, which also adversely affects the copper metal layer.

결국 기존의 방법은 소자의 고집적화에 따라 사용하기가 곤란할 것으로 예상되어 좀더 층덮힘이 우수하고 불순물이 적은 구리 배선 방법이 필요하다.
As a result, the conventional method is expected to be difficult to use due to the high integration of the device, and thus, a copper wiring method with better layer covering and less impurities is needed.

본 발명은 층덮힘 특성이 우수하고 불순물이 적은 반도체 소자의 구리 배선 형성 방법을 제공하는데 있다.The present invention provides a method for forming a copper wiring of a semiconductor device having excellent layer covering characteristics and less impurities.

본 발명의 다른 목적은 구리 배선 내부에 산화막이 형성되지 않는 반도체 소자의 구리 배선 형성 방법을 제공하는데 있다.Another object of the present invention is to provide a method for forming a copper wiring of a semiconductor device in which an oxide film is not formed inside the copper wiring.

본 발명의 또다른 목적은 신뢰성을 향상시킬 수 있는 반도체 소자의 구리 배 선 형성 방법을 제공하는데 있다.
Another object of the present invention to provide a method for forming a copper wiring of a semiconductor device that can improve the reliability.

본 발명은 하부 도전층등 소정의 구조가 형성된 반도체 기판 상부에 절연막을 형성한 후 절연막의 소정 영역을 식각하여 상기 반도체 기판의 하부 도전층을 노출시키는 콘택 홀을 형성하는 단계와, 전체 구조 상부에 확산 방지막을 형성하는 단계와, 전체 구조 상부에 제 1 구리막을 형성한 후 요오드 화합물을 도포하는 단계와, 전체 구조 상부에 제 2 구리막을 형성하고, 이에 의해 요오드 화합물이 상기 제 2 구리막 상부로 확산되어 상기 제 2 구리막 표면에 요오드층이 형성되는 단계와, 상기 요오드층을 제거한 후 전체 구조 상부에 제 3 구리막을 형성하는 단계와, 상기 절연막이 노출되도록 CMP 공정을 실시하여 구리 배선을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.
According to an embodiment of the present invention, after forming an insulating film on a semiconductor substrate having a predetermined structure such as a lower conductive layer, etching a predetermined region of the insulating film to form a contact hole exposing the lower conductive layer of the semiconductor substrate; Forming a diffusion barrier film, forming a first copper film over the entire structure, and then applying an iodine compound, and forming a second copper film over the entire structure, whereby the iodine compound Forming a copper wiring by diffusing to form an iodine layer on the surface of the second copper film, removing the iodine layer, and forming a third copper film on the entire structure, and performing a CMP process to expose the insulating film. Characterized in that it comprises a step.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 2(a) 내지 도 2(d)는 본 발명에 따른 반도체 소자의 구리 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.2 (a) to 2 (d) are cross-sectional views of devices sequentially shown in order to explain a method for forming a copper wiring of a semiconductor device according to the present invention.

도 2(a)를 참조하면, 하부 도전층등 소정의 구조가 형성된 반도체 기판(21) 상부에 절연막(22)을 형성한다. 절연막(22)의 소정 영역을 이중 다마신 공정으로 패터닝하여 반도체 기판(21)의 하부 도전층을 노출시키는 콘택 홀을 형성한다. 하부 도전층 상부에 형성된 금속 산화막을 제거한 후 진공 파괴없이 CVD 방법으로 확 산 방지막(23)을 형성한다. 이러한 공정에 의해 균일한 층덮힘을 가지고 있어 구리의 확산을 방지할 수 있다. 하부 도전층의 금속 산화막을 제거하기 위해서는 H2와 Ar의 혼합 가스 또는 H2와 He의 혼합 가스등과 같은 불활성 환원 가스를 사용한다. 또한, 확산 방지막(23)은 Ta, TaN, TiAlN, WN, TiSiN, WBN, TaSiN등과 같은 물질을 사용하여 형성하며, 100Å 이하의 두께로 형성한다.Referring to FIG. 2A, an insulating film 22 is formed on the semiconductor substrate 21 on which a predetermined structure such as a lower conductive layer is formed. A predetermined region of the insulating film 22 is patterned by a double damascene process to form a contact hole exposing the lower conductive layer of the semiconductor substrate 21. After removing the metal oxide film formed on the lower conductive layer, the diffusion barrier 23 is formed by the CVD method without vacuum destruction. This process has a uniform layer covering to prevent the diffusion of copper. In order to remove the metal oxide film of the lower conductive layer, an inert reducing gas such as a mixed gas of H 2 and Ar or a mixed gas of H 2 and He is used. In addition, the diffusion barrier 23 is formed using a material such as Ta, TaN, TiAlN, WN, TiSiN, WBN, TaSiN, and the like, and has a thickness of 100 μs or less.

도 2(b)를 참조하면, 전체 구조 상부에 PVD 방법으로 100Å 미만의 두께로 제 1 구리막(24)을 형성한다. 그리고, 제 1 구리막(24) 상부에 촉매로 작용하는 요오드 화합물을 도포한 후 동일 챔버에서 아르곤이나 헬륨등과 같은 불활성 가스를 이용한 플라즈마 처리를 실시하여 전면에 도포된 요오드의 분포를 균질화한다. 전체 구조 상부에 CVD 방법으로 제 2 구리막(25)을 형성한다. 제 2 구리막(25)은 콘택 직경의 50∼70% 정도 두께로 형성하며, 이러한 공정에 의해 콘택 홀은 완전하게 매립되는 반면 콘택 홀 상부의 평판 부위에는 상대적으로 요오드 처리에 의해 증착 속도가 콘택보다 늦어 얇게 증착된다. 그리고 제 2 구리막(25)이 형성되면서 요오드는 구리막 상부로 확산되어 구리막 표면에 요오드층(26)이 존재하게 된다.Referring to FIG. 2 (b), the first copper film 24 is formed on the entire structure with a thickness of less than 100 μs by the PVD method. The iodine compound acting as a catalyst is applied to the upper portion of the first copper film 24, and then plasma treatment using an inert gas such as argon or helium is performed in the same chamber to homogenize the distribution of iodine applied to the entire surface. The second copper film 25 is formed on the entire structure by the CVD method. The second copper film 25 is formed to have a thickness of about 50 to 70% of the contact diameter. The contact hole is completely filled by this process, while the deposition rate is relatively increased by the iodine treatment on the flat portion of the contact hole. Later it is deposited thinner. As the second copper layer 25 is formed, iodine diffuses over the copper layer, and the iodine layer 26 is present on the surface of the copper layer.

도 2(c)를 참조하면, 진공 파괴없이 구리 증착 챔버에서 플라즈마를 이용하여 요오드층(26)을 제거한다. 요오드층(26)을 효과적으로 제거하기 위해서는 웨이퍼에 수십 볼트의 바이어스를 인가한다. 전체 구조 상부에 진공 파괴없이 PVD 방법으로 제 3 구리막(27)을 형성한다. 구리의 확산과 절연막의 특성을 유지하기 위해 웨이퍼 제 3 구리막(27)을 형성할 때 웨이퍼의 온도를 300∼450℃로 유지하면서 형 성한다. 또한, 제 3 구리막(27)은 후속 공정인 CMP 공정을 용이하게 실시하기 위해 5000∼15000Å 정도의 두께로 형성한다. 이와 같이 고온에서 증착된 구리 금속층은 전기 화학적 증착에 의한 경우보다 구리 금속의 순도가 높고 결정립이 조대하여 추가의 열처리를 필요로 하지 않는다. 한편, 제 3 구리막(27)은 전기 화학적 방법으로 형성하여도 된다.Referring to FIG. 2 (c), the iodine layer 26 is removed using plasma in a copper deposition chamber without vacuum destruction. In order to effectively remove the iodine layer 26, a bias of several tens of volts is applied to the wafer. The third copper film 27 is formed on the entire structure by the PVD method without vacuum breaking. In order to maintain the diffusion of copper and the characteristics of the insulating film, the wafer is formed while maintaining the temperature of the wafer at 300 to 450 占 폚 when the third copper film 27 is formed. In addition, the third copper film 27 is formed to a thickness of about 5000 to 15000 Pa in order to easily perform the CMP process, which is a subsequent step. The copper metal layer deposited at such a high temperature has higher purity of the copper metal and coarse grains than the case of electrochemical deposition, and thus does not require additional heat treatment. In addition, you may form the 3rd copper film 27 by the electrochemical method.

도 2(d)는 절연막(22)이 노출되도록 CMP 공정을 실시하여 구리 배선을 형성한 상태의 단면도이다. CPM 공정을 실시한 후 NH3와 같은 가스를 이용하여 구리막의 표면을 환원시키면서 보호하는 공정을 실시한다.
FIG. 2D is a cross-sectional view of a copper wiring formed by performing a CMP process to expose the insulating film 22. After the CPM process, a process of protecting the surface of the copper film while reducing the surface of the copper film using a gas such as NH 3 is performed.

상술한 바와 같이 본 발명에 의하면 구리 금속 배선층을 1개의 장비에서 진공의 파괴없이 이루어지기 때문에 막질이 우수한 구리 배선을 형성하여 신뢰성을 향상시킬 수 있고, 전기 화학적 방법으로 구리막을 형성하지 않고 고온에서 구리막을 형성하기 때문에 구리막의 미세 구조를 위해 추가적인 열처리 공정을 실시하지 않아도 된다.As described above, according to the present invention, since the copper metal wiring layer is formed without vacuum breakdown in one piece of equipment, the copper wiring with excellent film quality can be formed to improve reliability, and copper is formed at high temperature without forming a copper film by an electrochemical method. Since the film is formed, it is not necessary to perform an additional heat treatment process for the fine structure of the copper film.

Claims (12)

하부 도전층등 소정의 구조가 형성된 반도체 기판 상부에 절연막을 형성한 후 절연막의 소정 영역을 식각하여 상기 반도체 기판의 하부 도전층을 노출시키는 콘택 홀을 형성하는 단계와,Forming a contact hole to expose a lower conductive layer of the semiconductor substrate by forming an insulating layer on the semiconductor substrate having a predetermined structure such as a lower conductive layer and then etching a predetermined region of the insulating layer; 전체 구조 상부에 확산 방지막을 형성하는 단계와,Forming a diffusion barrier over the entire structure; 전체 구조 상부에 제 1 구리막을 형성한 후 요오드 화합물을 도포하는 단계와,Forming a first copper film on the entire structure and then applying an iodine compound; 전체 구조 상부에 제 2 구리막을 형성하고, 이에 의해 요오드 화합물이 상기 제 2 구리막 상부로 확산되어 상기 제 2 구리막 표면에 요오드층이 형성되는 단계와,Forming a second copper film over the entire structure, whereby an iodine compound is diffused over the second copper film to form an iodine layer on the surface of the second copper film, 상기 요오드층을 제거한 후 전체 구조 상부에 제 3 구리막을 형성하는 단계와,Removing the iodine layer and forming a third copper film on the entire structure; 상기 절연막이 노출되도록 CMP 공정을 실시하여 구리 배선을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.And forming a copper wiring by performing a CMP process so that the insulating film is exposed. 제 1 항에 있어서, 상기 콘택 홀에 의해 노출된 하부 도전층 상에 형성된 금속 산화막을 제거하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.The method of claim 1, further comprising removing a metal oxide film formed on the lower conductive layer exposed by the contact hole. 제 2 항에 있어서, 상기 금속 산화막은 H2와 Ar의 혼합 가스 또는 H2와 He의 혼합 가스를 이용하여 제거하는 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.The method of claim 2, wherein the metal oxide film is removed by using a mixed gas of H 2 and Ar or a mixed gas of H 2 and He. 제 1 항에 있어서, 상기 확산 방지막은 CVD 방법을 이용하여 100Å 이하의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.The method for forming a copper wiring of a semiconductor device according to claim 1, wherein the diffusion barrier is formed to a thickness of 100 GPa or less using a CVD method. 제 1 항에 있어서, 상기 확산 방지막은 Ta막, TaN막, TiAlN막, WN막, TiSiN막, WBN막, TaSiN막 중 어느 하나로 형성하는 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.The method of claim 1, wherein the diffusion barrier is formed of any one of a Ta film, a TaN film, a TiAlN film, a WN film, a TiSiN film, a WBN film, and a TaSiN film. 제 1 항에 있어서, 상기 제 1 구리막은 PVD 방법을 이용하여 100Å 미만의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.The method of forming a copper wiring of a semiconductor device according to claim 1, wherein the first copper film is formed to a thickness of less than 100 GPa using a PVD method. 제 1 항에 있어서, 상기 요오드 화합물을 도포한 후 동일 챔버에서 불활성 가스를 이용한 플라즈마 처리를 실시하여 요오드의 분포를 균질화하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.The method of claim 1, further comprising homogenizing the distribution of iodine by applying a iodine compound and performing plasma treatment using an inert gas in the same chamber. 제 1 항에 있어서, 상기 제 2 구리막은 CVD 방법을 이용하여 콘택 직경의 50 내지 70% 정도의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.The method of claim 1, wherein the second copper film is formed to a thickness of about 50 to 70% of the contact diameter by using a CVD method. 제 1 항에 있어서, 상기 요오드층은 구리 증착 챔버에서 웨이퍼의 소정 전압을 인가하고, 플라즈마를 이용하여 제거하는 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.The method of claim 1, wherein the iodine layer is removed by using a plasma by applying a predetermined voltage of the wafer in a copper deposition chamber. 제 1 항에 있어서, 상기 제 3 구리막은 PVD 방법 또는 전기 화학적 증착 방법을 이용하여 5000 내지 15000Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.The method of claim 1, wherein the third copper film is formed to a thickness of 5000 to 15000 kV using a PVD method or an electrochemical vapor deposition method. 제 1 항 또는 제 10 항에 있어서, 상기 제 3 구리막은 웨이퍼의 온도를 300 내지 450℃로 유지하면서 형성하는 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.The method for forming a copper wiring of a semiconductor device according to claim 1 or 10, wherein the third copper film is formed while maintaining the temperature of the wafer at 300 to 450 占 폚. 제 1 항에 있어서, 상기 CMP 공정을 실시한 후 NH3 가스를 이용하여 구리막의 표면을 환원시키면서 보호하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.The method of claim 1, further comprising: protecting the surface of the copper film while reducing the surface of the copper film using NH 3 gas after performing the CMP process.
KR1020000036526A 2000-06-29 2000-06-29 Method of forming a copper wiring in a semiconductor device KR100576506B1 (en)

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