KR100673178B1 - Method of forming a copper wiring in a semiconductor device - Google Patents
Method of forming a copper wiring in a semiconductor device Download PDFInfo
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- KR100673178B1 KR100673178B1 KR1020000037030A KR20000037030A KR100673178B1 KR 100673178 B1 KR100673178 B1 KR 100673178B1 KR 1020000037030 A KR1020000037030 A KR 1020000037030A KR 20000037030 A KR20000037030 A KR 20000037030A KR 100673178 B1 KR100673178 B1 KR 100673178B1
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 55
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 53
- 239000010949 copper Substances 0.000 title claims abstract description 53
- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000009792 diffusion process Methods 0.000 claims abstract description 50
- 230000004888 barrier function Effects 0.000 claims abstract description 41
- 230000008569 process Effects 0.000 claims description 19
- 239000012298 atmosphere Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 238000007772 electroless plating Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229910008482 TiSiN Inorganic materials 0.000 claims description 3
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims description 3
- 230000009977 dual effect Effects 0.000 claims description 2
- 238000009713 electroplating Methods 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 abstract description 11
- 230000002265 prevention Effects 0.000 abstract description 5
- 229910052799 carbon Inorganic materials 0.000 abstract description 4
- 229910052739 hydrogen Inorganic materials 0.000 abstract description 4
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 abstract description 3
- 229910001431 copper ion Inorganic materials 0.000 abstract description 3
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 abstract 1
- 239000005751 Copper oxide Substances 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 229910000431 copper oxide Inorganic materials 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 9
- 229910052782 aluminium Inorganic materials 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910004156 TaNx Inorganic materials 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000003405 preventing effect Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 239000002159 nanocrystal Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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Abstract
본 발명은 반도체 소자의 구리 배선 형성 방법에 관한 것으로, 반도체 기판의 소정 영역을 노출시키는 절연막 패턴에 확산 방지막을 형성하고 대기중에 노출시키거나 열처리 공정을 실시하여 확산 방지막 표면에 존재하고 있는 결함들을 O, C, H등의 원자들로 채워 매우 조밀한 확산 방지막을 형성한 후 구리 배선을 형성함으로써 구리 이온 또는 원자들의 절연막으로의 이동을 차단하여 확산 방지 특성을 현저하게 향상시킬 수 있는 반도체 소자의 구리 배선 형성 방법이 제시된다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a copper wiring of a semiconductor device. A copper oxide semiconductor can be used to form a very dense diffusion barrier by filling atoms of C, H, etc., and then copper wiring to block copper ions or atoms from moving to an insulating layer, thereby significantly improving diffusion prevention characteristics. A wiring formation method is presented.
구리 배선, 확산 방지막, 대기 노출, 열처리Copper wiring, diffusion barrier, atmospheric exposure, heat treatment
Description
도 1(a) 및 도 1(b)는 본 발명에 따른 반도체 소자의 구리 배선 형성 방법을 설명하기 위해 도시한 소자의 단면도.
1 (a) and 1 (b) are cross-sectional views of a device shown for explaining a method for forming a copper wiring of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>
11 : 반도체 기판 12 : 절연막11
13 : 확산 방지막 14 : 구리막
13: diffusion prevention film 14: copper film
본 발명은 반도체 소자의 구리 배선 형성 방법에 관한 것으로, 특히 절연막 패턴에 확산 방지막을 형성하고 확산 방지막을 대기중에 노출시키거나 열처리한 후 구리 배선을 형성함으로써 구리의 확산 방지 특성을 향상시킬 수 있는 반도체 소자 의 구리 배선 형성 방법에 관한 것이다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a copper wiring of a semiconductor device. In particular, a semiconductor capable of improving the diffusion preventing property of copper by forming a diffusion barrier in an insulating film pattern and exposing the diffusion barrier in the air or by heat treatment and then forming a copper interconnect It relates to a method for forming a copper wiring of the device.
알루미늄을 배선 재료로 사용하는 경우 알루미늄은 절연막으로 사용되는 실리콘 산화막(SiO2)로의 확산이 전혀 일어나지 않는 것으로 알려져 있으므로 측벽에 매우 얇게 증착되는 확산 방지막의 특성은 전혀 영향을 받지 않는다. 이에 반하여 구리는 알루미늄과 달리 절연막으로 사용되는 실리콘 산화막을 통해 확산이 일어난다. 또한, 절연막을 통과해 하부층으로 이동한 구리는 실리콘내에서 깊은 준위 (deep level)로 존재하게 된다. 즉, 구리는 실리콘내에서 깊은 준위의 도펀트로 작용하여 실리콘의 금지대(fobidden band)내에 여러개의 억셉터(acceptor)와 도우너 (donor) 레벨을 형성시킨다. 깊은 준위는 발생(generating)-재결합(recombination)의 소오스로 작용하여 누설 전류를 유발시켜 소자를 파괴시킨다. 따라서, 구리를 배선 공정에 도입하려면 이종 금속과 접촉하는 하부(bottom)는 물론이고 측벽의 절연막에 대한 확산 방지막이 필요하다.When aluminum is used as a wiring material, since aluminum is known to not diffuse at all into the silicon oxide film (SiO 2 ) used as an insulating film, the characteristics of the diffusion barrier film deposited very thinly on the sidewall are not affected at all. In contrast, copper, unlike aluminum, diffuses through a silicon oxide film used as an insulating film. In addition, the copper that has passed through the insulating film to the lower layer is present at a deep level in the silicon. That is, copper acts as a deep level dopant in silicon to form multiple acceptor and donor levels within the silicon's fobidden band. Deep levels act as a source of generating-recombination, causing leakage currents to destroy the device. Therefore, in order to introduce copper into the wiring process, a diffusion barrier for the insulating film on the sidewall as well as the bottom in contact with the dissimilar metal is required.
구리 배선 공정은 IC 회로의 축소에 따라 사용이 불가피해지는 공정이므로 깊은 콘택 또는 트렌치 패턴에 적용되며, 확산 방지막 증착 공정의 한계성으로 인해 스텝 커버러지가 점차 나빠지므로 하부 또는 측벽에 증착되는 확산 방지막의 두께는 점점 얇아진다. 또한 구리 배선의 유효 저항을 높이지 않기 위해서라도 확산 방지막의 두께는 제한이 따르게 된다. 예를들어 현재 실용화 단계에 있는 HCM(hollow cathod magnetron) TaNx, IMP(ion metal plasma) TaNx와 같은 advanced ionized PVD 방식의 경우 측벽의 스텝 커버러지가 10%를 넘지 않기 때문에 확산 방지막의 두께는 30Å을 넘지 않는다. 또한, PVD 방식의 한계점으로 인하여 CVD 방식으로 형성된 확산 방지막이 적용된다 하더라도 ITRS(International Technology Roadmap for Semiconductor)에 따르면 0.07㎛ 이하에서는 확산 방지막의 허용 두께는 최대 30Å 정도인 것으로 예상하고 있다. 따라서, 구리에 대한 확산 방지막의 역할을 수행하려면 확산 방지막 내부에 그레인 바운더리와 같은 결함(defect)가 전혀 없는 완벽한 비결정(amorphous) 구조가 되어야 하는데, 이와 같은 막을 제조하는 것은 거의 불가능하다.The copper wiring process is applied to deep contact or trench patterns because it is inevitable due to the shrinkage of the IC circuit, and the step coverage is gradually worsened due to the limitation of the diffusion barrier film deposition process. Becomes thinner and thinner. Further, even if the effective resistance of the copper wiring is not increased, the thickness of the diffusion barrier film is limited. For example, in advanced ionized PVD methods such as hollow cathod magnetron (HCM) TaNx and ion metal plasma (IMP) TaNx, which are currently in practical use, the diffusion barrier has a thickness of 30Å because the step coverage of the sidewalls does not exceed 10%. Do not go over. In addition, even if the diffusion barrier film formed by the CVD method is applied due to the limitation of the PVD method, according to the International Technology Roadmap for Semiconductor (ITRS), it is expected that the allowable thickness of the diffusion barrier film is about 30 mm at maximum at 0.07 μm or less. Therefore, in order to serve as a diffusion barrier for copper, it is necessary to have a perfect amorphous structure without any defects such as grain boundaries inside the diffusion barrier, which is almost impossible to manufacture.
한편, PVD 방식을 현재 실용화 단계에 있는 HCM TaNx, INP TaNx 등과 같은 재료들도 완전한 비결정 구조가 아닌 나노크리스탈(nanocrystal)의 결정질 구조를 하고 있으므로 막의 두께가 매우 얇을 경우 확산 방지 특성의 약화가 쉽게 예상된다. 단지 이를 평가하기 위한 방식이 표준화된 것이 없을 따름이다.
On the other hand, HCM TaNx, INP TaNx, etc., which are currently using PVD methods, also have a crystalline structure of nanocrystals instead of a complete amorphous structure. Therefore, when the film thickness is very thin, the diffusion prevention property is easily expected. do. There is no standard way to assess this.
본 발명의 목적은 구리의 확산 방지 특성을 향상시킬 수 있는 확산 방지막을 형성하는 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법을 제공하는데 있다.An object of the present invention is to provide a method for forming a copper wiring of a semiconductor device, characterized by forming a diffusion barrier film capable of improving the diffusion barrier property of copper.
본 발명의 다른 목적은 비결정 구조의 확산 방지막을 형성하여 구리의 확산 방지 특성을 향상시킬 수 있는 반도체 소자의 구리 배선 형성 방법을 제공하는데 있다. Another object of the present invention is to provide a method for forming a copper wiring of a semiconductor device capable of improving the diffusion preventing property of copper by forming a diffusion barrier of amorphous structure.
구리 배선 공정에 사용되는 확산 방지막은 그 내부에 그레인 바운더리와 같은 결함이 전혀 없는 완벽한 비정질 구조이어야 한다. 그러나, 구리 배선 공정에 적용되는 확산 방지막은 수십Å 정도로 매우 얇게 형성되기 때문에 막내에 결함이 존재하게 되며, 이러한 결함은 확산 방지막으로써의 역할에 제한을 가져오게 된다. 따라서, 본 발명에서는 확산 방지막을 증착한 후 대기중에 노출시키거나 기체 분위기에서 열처리 공정을 실시하여 결함이 존재하는 부분을 O, C, H등의 원자들로 매움으로써 확산 방지 능력을 향상시키고자 한다.The diffusion barrier used in the copper wiring process should be a complete amorphous structure with no defects such as grain boundaries inside. However, since the diffusion barrier film applied to the copper wiring process is formed very thin, such as several tens of micrometers, defects exist in the film, and such defects have a limitation in their role as diffusion barrier films. Therefore, in the present invention, the diffusion barrier layer is exposed to the air or subjected to a heat treatment process in a gas atmosphere to fill the portion in which defects exist with atoms such as O, C, and H to improve the diffusion barrier ability. .
기존의 알루미늄 배선 공정에서는 주상정 조직을 갖는 TiN의 표면을 공기중에 노출시켜 표면 및 결정 계면에 Ti-N-O를 형성시킴으로써 확산 방지막으로써의 역할을 향상시키는 것으로 알려져 있으며, 실용화되어 있다(oxygen stuffing 효과). 위와 같이 TiN을 구리 배선 공정에 적용할 경우에는 확산 방지막으로써의 산소 스터핑 효과가 없는 것으로 보고되어 있다. 그러나, 이는 TiN을 구리와 실리콘의 계면 사이에 수백∼수천Å 정도의 두께로 매우 두껍게 증착시켜 500∼800℃ 정도의 고온에서 실리콘과 구리의 반응성 여부를 통해 확산 방지막을 평가한 것이므로 신빙성이 없는 결과이다. 실제로 구리 배선 공정의 경우는 알루미늄과 달리 고온 공정을 수반하지 않기 때문에(최대 450℃를 넘지 않는다) 공기중에 노출될 경우 확산 방지막 표면 또는 결함 등에 흡착되어 있거나 결합되어 있는 O, H, C, N등이 구리 원자 또는 이온의 이동을 막게 된다. 즉, 구리 배선 공정의 가용 온도(450℃ 이하)에서는 원자들의 진동(vibratioon)이 크지 않기 때문에 알루미늄에서와 같은 스터핑 효과를 적용시킬 수 있게 된다. In the existing aluminum wiring process, it is known to improve the role as a diffusion barrier by exposing the surface of TiN having columnar structure to air to form Ti-NO at the surface and crystal interface, and it has been put into practical use (oxygen stuffing effect). . As described above, when TiN is applied to a copper wiring process, it is reported that there is no oxygen stuffing effect as a diffusion barrier. However, this is because TiN was deposited very thickly between the interface between copper and silicon at a thickness of several hundreds to thousands of micrometers, and the diffusion barrier was evaluated through the reactivity of silicon and copper at a high temperature of 500 to 800 ° C. to be. In fact, copper wiring processes do not involve high temperature processes (not exceeding 450 ° C), unlike aluminum, so that when exposed to air, they are adsorbed or bonded to the diffusion barrier surface or defects. This prevents the migration of copper atoms or ions. That is, at the available temperature (450 ° C. or lower) of the copper wiring process, since the vibration of atoms is not large, it is possible to apply the stuffing effect as in aluminum.
본 발명에서는 구리 확산 방지막의 경우 구리의 확산 메커니즘이 알루미늄의 경우와는 다르다는 것을 이용하여 TiN은 물론 구리 확산 방지막으로 사용되는 Ta, TaN, TaC, WN, TiW, TiSiN, WBN, WC막들에 대한 확산 방지 특성을 향상시켰다.
In the present invention, since the diffusion mechanism of copper is different from that of aluminum in the case of the copper diffusion barrier, diffusion to Ta, TaN, TaC, WN, TiW, TiSiN, WBN, and WC films used as the copper diffusion barrier is performed. Improved the prevention properties.
본 발명에 따른 반도체 소자의 구리 배선 형성 방법은 소정의 구조가 형성된 반도체 기판 상부에 절연막을 형성한 후 상기 절연막의 소정 영역을 패터닝하여 상기 반도체 기판의 소정 영역을 노출시키는 트렌치를 형성하는 단계와, 전체 구조 상부에 확산 방지막을 형성한 후 대기중에 노출시키거나 열처리 공정을 실시하는 단계와, 상기 트렌치가 매립되도록 전체 구조 상부에 구리막을 형성한 후 연마 공정을 실시하여 구리 배선을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.
The method for forming a copper wiring of a semiconductor device according to the present invention includes forming a trench over a semiconductor substrate having a predetermined structure and then patterning a predetermined region of the insulating layer to form a trench for exposing a predetermined region of the semiconductor substrate; Forming a diffusion barrier over the entire structure and exposing it to the atmosphere or performing a heat treatment process; forming a copper film over the entire structure to fill the trench, and then performing a polishing process to form a copper wiring. Characterized in that made.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1(a) 및 도 1(b)는 본 발명에 따른 반도체 소자의 구리 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.1 (a) and 1 (b) are cross-sectional views of devices sequentially shown in order to explain a method for forming a copper wiring of a semiconductor device according to the present invention.
도 1(a)를 참조하면, 소정의 구조가 형성된 반도체 기판(11) 상부에 절연막 (12)을 형성한다. 절연막(12)으로는 실리콘 산화막 또는 저유전막을 사용한다. 싱글 다마신 또는 듀얼 다마신 공정을 이용한 절연막(12) 패터닝 공정으로 반도체 기판(11)의 소정 영역을 노출시키는 트렌치를 형성한다. 트렌치를 포함한 전체 구조 상부에 확산 방지막(13)을 형성한다. 확산 방지막(13)으로는 Ta막, TaN막, TaC막, WN막, TiW막, TiSiN막, WBN막, WC막중 어느 하나를 이용한다. 확산 방지막(13)을 형성한 후 0∼100℃의 온도와 10∼80%의 습도를 유지하는 대기중에 1초∼10시간 노출시키거나 열처리 공정을 실시한다. 열처리 공정은 150∼450℃의 온도에서 5분∼5시간동안 실시하는 반응로 열처리 또는 250∼500℃의 온도에서 1초∼20분동안 실시하는 급속 열처리 공정을 사용한다. 이때, N2 분위기, Ar 분위기, N2와 H2의 혼합 분위기, Ar과 H2의 혼합 분위기, Ar과 N2의 혼합 분위기, Ar과 O2의 혼합 분위기중 어느 하나의 분위기에서 열처리 공정을 실시한다. 대부분의 확산 방지막은 완벽한 비결정 구조를 얻을 수 없을 뿐만 아니라 비록 비결정 구조가 되더라도 막이 매우 얇을 경우 그들막에 결함이 존재하게 된다. 상기한 바와 같이 확산 방지막을 형성한 후 대기중에 노출시키거나 열처리 공정을 실시하여 매우 확산 방지막내에 존재하는 미세한 결함들이 O, H, C, N등의 미세한 원자들로 채워지게 되기 때문에 구리 원자 또는 구리 이온들의 절연막으로의 확산을 방지할 수 있게 된다.Referring to FIG. 1A, an
도 1(b)를 참조하면, 트렌치를 포함한 전체 구조 상부에 구리막(14)을 형성한 후 CMP 공정을 실시하여 구리 배선을 형성한다. 구리막(14)은 무전해 도금 방법, CVD 방법, 전해 도금 방법중 어느 하나의 방법을 이용하여 형성한다. 또한, 구리막(14)을 형성하기 전 무전해 도금, PVD 방법, CVD 방법으로 구리 시드층을 50∼1500Å의 두께로 형성한 후 구리막을 형성할 수도 있다.
Referring to FIG. 1B, a
상술한 바와 같이 본 발명에 의하면 확산 방지막을 형성하고 대기중에 노출시키거나 열처리를 실시하여 확산 방지막 표면에 존재하고 있는 결함들을 O, C, H등의 원자들로 채워 매우 조밀한 확산 방지막을 형성한 후 구리 배선을 형성함으로써 구리 이온 또는 원자들의 절연막으로의 이동을 차단하여 확산 방지 특성을 현저하게 향상시킬 수 있다. 또한, 본 발명을 적용시킨다면 기존의 알루미늄 배선 공정의 확산 방지막으로 사용되고 있는 TiN을 적용할 수 있기 때문에 장비 투자 비용 또한 절감시킬 수 있다.As described above, according to the present invention, a diffusion barrier layer is formed and exposed to the atmosphere or subjected to heat treatment to fill defects existing on the surface of the diffusion barrier layer with atoms such as O, C, and H to form a very dense diffusion barrier layer. After forming the copper wiring, it is possible to block the movement of copper ions or atoms to the insulating film to significantly improve the diffusion prevention characteristics. In addition, if the present invention can be applied to TiN which is used as a diffusion barrier of the existing aluminum wiring process can also reduce the equipment investment cost.
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