TWI416662B - Technique for forming interconnect structures with reduced electro and stress migration and/or resistivity - Google Patents

Abstract

The method involves forming a metal line in a dielectric layer of a metallization layer of a semiconductor device, where the line extends along a length direction. A heat treatment including heating of a locally restricted zone is performed to modify the crystalline of metals in metal lines and to enhance the purity of the metal lines. The locally heated zone is scanned along a length direction of the metal line to reduce a number of grain boundaries in the length direction.

Description

Method of forming an interconnect structure having reduced electrical and stress migration and/or resistivity

The present invention relates generally to the formation of microstructures such as advanced integrated circuits, and more particularly to the formation of conductive structures such as metal lines in metallization layers of integrated circuits.

In the manufacture of modern microdevices such as integrated circuits, there is a sustained driving force to steadily reduce the feature size of the component elements, thereby enhancing the functionality of these structures. For example, in today's integrated circuits, the minimum feature size (e.g., the channel length of the field effect transistor) has reached the deep sub-micron range, thereby increasing the efficiency of these circuits in terms of speed and/or power consumption. Since the size of individual circuit components is reduced with each new circuit generation to thereby increase the switching speed of, for example, the transistor elements, the available floor space for interconnecting the individual circuit components is also It is reduced accordingly. Therefore, the size of these interconnect lines must be reduced to offset the reduction in usable volume and the number of circuit components added per unit wafer area. The reduced cross-sectional area of the interconnects may result in an increase in the static power consumption of the extremely reduced transistor components, which may require multiple stacked metallization layers to meet the standpoint of acceptable current density in the metal lines.

However, advanced integrated circuits, including those having a critical dimension of 0.13 microns or even smaller, may require significantly increased current density in individual interconnects, albeit because of the significant number of cells per unit area. The crystal elements provide a relatively large number of metallization layers. However, operating the interconnect at increased current density may suffer from a variety of problems associated with stress-induced line degradation, which may ultimately lead to premature failure of the integrated circuit. One notable phenomenon in this regard is the current induced material movement in the metal line, also known as "electromigration", which can result in the formation of voids therein and the formation of hillocks beside the metal lines. Therefore, the performance and reliability of the device are reduced or completely broken. For example, aluminum wires embedded with ceria and/or tantalum nitride are often used as metals for the metallization layer, where as explained above, advanced integrated circuits have critical dimensions of 0.13 microns or less and may require significantly reduced metal lines. The cross-sectional area and thus the current density, which may result in aluminum being less prone to form a metallization layer due to significant electromigration effects.

Therefore, aluminum is gradually replaced by copper, which exhibits a significantly lower resistance value relative to aluminum and a stronger resistance to electromigration at high current densities. The introduction of copper to microstructures and integrated circuit fabrication systems poses a number of serious problems due to the tendency of copper to diffuse easily in cerium oxide and various low-k dielectric materials. In order to provide the necessary adhesion and to avoid undesired diffusion of copper atoms into the sensitive device region, it is often desirable to provide a barrier layer between the dielectric material in which the copper and copper wires are embedded. Although tantalum nitride is a dielectric material that can effectively prevent the diffusion of copper atoms, the choice of tantalum nitride as the interlayer dielectric material is a less desirable choice because tantalum nitride exhibits a slightly higher permittivity, thus increasing the proximity. The parasitic capacitances of copper wires. Therefore, a thin conductive barrier layer which can provide mechanical stability required for copper is formed to separate bulk copper and surrounding dielectric material, and thin tantalum nitride or tantalum carbide or tantalum carbonitride is usually only A capping layer form is used in the copper-based metallization layer. At present, tantalum, titanium, tungsten and its compounds with nitrogen and antimony are preferred candidates for the conductive barrier layer, wherein the barrier layer may comprise two or more sublayers of different materials to achieve diffusion inhibition. (diffusion suppressing) and the nature of the adhesion.

Another characteristic that copper and aluminum can be significantly different is that copper cannot be deposited in large quantities immediately by chemical and physical vapor deposition techniques. In addition, copper cannot be efficiently patterned by an anisotropic dry etch process, thus requiring a process that is commonly referred to as damascene or inlaid techniques. In the damascene process, a dielectric layer is first formed and then patterned to include trenches and vias that are then filled with copper, wherein, as previously described, the conductive barrier layer is filled before filling the copper. Formed on the sidewalls of the trench and the via. Depositing the bulk steel material to the trenches and vias is typically achieved by a wet chemical deposition process, such as electroplating or electroless plating, whereby it is necessary to fill the aspect ratio equal to and greater than 5 and a diameter of about 0.1 microns or less. The via hole and the trench having a width ranging from about 0.1 micron to a few micrometers. Although the electrochemical deposition process of copper has been completely established in the field of electronic circuit board manufacturing, the void-free high aspect ratio via filling is a very complicated and challenging task, and the copper metal finally obtained. The characteristics of the line are significantly related to process parameters, materials, and the desired structural geometry. Since the geometry of the interconnect structure is determined by the design requirements, no significant changes can be made to a given microstructure, as it is to estimate and control the fabrication of the metallization layer and the fabrication of copper microstructure materials (eg, conductive and non-conductive). The manufacturing process of the barrier layer and its interaction, the influence of the characteristics of the interconnect structure, to ensure high yield and reliability of the required product at the same time is very important.

Therefore, as the continuous feature size reduction in advanced devices leads to stricter restrictions on electrical and stress migration and copper wire electrical conductivity characteristics, efforts have been made to investigate copper in order to find new materials and process strategies for forming copper-based metal wires. Degradation, especially focusing on electrical and stress migration and excessively reduced electrical conductivity in extremely reduced devices. Although the exact mechanism of electricity and stress migration in copper wires is not fully understood, the results show that pores located in and on the sidewalls and interfaces, large pores and residues at the bottom of the vias can significantly affect electrical and stress migration behavior. . The results of the research experience show that the degree of electrical and stress migration can be generally related to the material composition of the metal, the crystal structure of the metal, and any interface conditions of adjacent materials (such as conductive and dielectric barrier layers).

For example, in aluminum wires, grain boundaries provide a better diffusion path for stress and current induced material transport events. As a result, since the wire size reduction tends to produce smaller grains, a non-proportional increase in induced electrical and stress migration can occur. Although grain boundaries may not necessarily form a better diffusion path in the copper-based metal line, the increased number of grain boundaries may still significantly increase the overall resistivity of the copper baseline due to increased electron scattering at the grain boundaries. Therefore, there is a need for a highly complex manufacturing process (including metal deposition and subsequent tempering thereof) that controls the metallization layer to increase the performance of the metal interconnect structure in terms of electrical and stress migration and/or conductivity.

Therefore, there is a need for a lift technology that can form metal interconnect structures that exhibit reduced stress and electrically induced material diffusion and/or increased conductivity, even in extremely reduced microstructures.

A simplified summary of the invention is set forth to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. They are not intended to be used to define important or critical elements of the invention or to describe the scope of the invention. Its purpose is to present some concepts only in a simplified form, as a more detailed description of the foregoing.

In general, the present invention relates to techniques for forming metal lines in a metallization layer of a semiconductor device, wherein the improvement in electrical and stress migration and/or conductivity characteristics of the metal line can be achieved during formation of the metal line And/or afterwards a heat treatment is applied to increase the electrical performance of the wire. According to some narrative embodiments, the heat treatment may include at least a heating process performed in a sub-atmospheric and/or vacuum and/or reduced pressure and/or a blunt atmosphere to facilitate pre-production. Out-gassing of contaminants into the metal has been introduced during the process. In other embodiments, the heat treatment includes at least one heating process designed to vary the temperature generated in the wire along a predefined direction to locally create a heated region that moves in the predefined direction.

In accordance with another illustrative embodiment of the present invention, a method includes forming a metal line in a dielectric layer of a metallization layer of a semiconductor device, wherein the metal line extends along a length direction. Further, the method includes performing a heat treatment to change the temperature along the length direction in a timed sequential manner.

In accordance with still another illustrative embodiment of the present invention, a method includes forming a metal line in a dielectric layer formed on a substrate including a semiconductor device, and performing a heat treatment to modify a crystalline structure of the metal line. Additionally, the method includes exposing the metal line to a vacuum atmosphere to promote outgassing of contaminants in the metal line.

In a descriptive embodiment of the invention, the wire is exposed to a reduced pressure atmosphere after exposure to a vacuum atmosphere. In this regard, a vacuum atmosphere is understood to be a gas atmosphere having a rating of several Torr and a significantly reduced pressure, while a sub-atmospheric ambient may include a pressure condition ranging from From ambient pressures below the value but close to the manufacturing equipment to vacuum pressure conditions.

Illustrative embodiments of the invention are described below. For the sake of clarity, not all features of the actual application are recited in the specification. It is of course understood that in any such actual embodiment, a variety of implementation specific decisions must be made to achieve a developer's specific goals, such as compliance with system related and business related constraints, which may vary from application to application. Furthermore, it is important to understand that such research and development efforts can be complex and time consuming, but it is still understood that those skilled in the art routinely benefit from this disclosure.

The invention will now be described with reference to the drawings. The various structures, systems, and devices shown in the drawings are for illustrative purposes only, and the invention is not limited by the details which are well known to those skilled in the art. However, the drawings are included to describe and explain the illustrative embodiments of the invention. The words and phrases used in this article should be interpreted and understood in accordance with the words and phrases understood by those skilled in the art. There is no intention to use a specific term or phrase definition, that is, a term and phrase in this context that is different from the original and customary meanings understood by those skilled in the art. If the meaning of a term or phrase is to be extended to a particular meaning, that is to say, to a person who is familiar with the term, such special meaning will be explained in a direct and unambiguous manner by providing a specific definition of the term or phrase in a defined manner. .

The present invention relates to a technique for forming metal lines in a metallization layer of an extremely reduced semiconductor device, wherein the crystal structure of the metal and/or the purity of the metal is changed by heat treatment to impart heat and stress migration resistance and/or The intrinsic conductivity enhances the characteristics of the wire. Without wishing to be bound by the following explanation of the invention, it is believed that reducing the number of grain boundaries in the metal line can significantly affect the electrical performance of the metal line due to reduced electrical and stress migration and/or increased inherent conductivity. As is well known, the crystallization of the metal in the microstructured metal line is determined by the type of material used, the deposition technique used, the process parameters maintained throughout the deposition process, and any process before and after the metal is actually deposited.

For example, copper-based metallization layers are now formed by electrochemical deposition techniques such as electroplating, where grain size and crystal structure are significantly related to deposition parameters and trenches that need to be filled with copper-based metals, depending on the size of the vias, because the trenches are reduced The size of the slots and vias can cause the metal grains to be formed in a reduced size. Therefore, the intrinsic conductivity of the copper-based metal may be reduced because the charge carrier scattering at an increased number of grain boundaries also increases.

Moreover, as is well known, electrochemical deposition to extremely narrow trenches and vias in a substantially non-porous manner requires complex plating techniques involving highly complex electrolyte solutions. Therefore, various additives, such as deposition inhibitors, accelerators, complexing agents, etc., are contained in a typical electrolyte solution, which can be maintained in a certain amount in the deposited metal, thereby also impairing the inherent conductivity of the metal wire. degree. Furthermore, the presence of contaminants in the metal and/or the presence of most grain boundaries can also have an effect on electrical and stress migration behavior, as grain boundaries and/or contaminants can affect any interfacial properties of the metal and adjacent materials, adjacent The material is, for example, any diffusion barrier layer of copper. Furthermore, grain boundaries can directly affect the transfer of stress-inducing materials, such as aluminum. As a result, the overall properties of the wire can be improved by changing the crystallinity of the metal and/or reducing the level of contaminants.

It will be appreciated that the present invention is particularly advantageous for the use of copper-based metallization layers because these structures are typically fabricated in a damascene process using electrochemical deposition techniques, thereby producing a large number of small grains and contaminants containing electrolytes. However, the invention may also be applied to metal wires formed of any other suitable material, such as aluminum, and thus the invention should not be construed as being limited to copper-based metallization layers, unless such limitations are apparent from the scope of the appended claims.

Referring to Figures 1a through 1f and Figures 2a through 2d, a further illustrative embodiment of the present invention will now be described in more detail. Figure 1a illustrates a semiconductor device 100 comprising a substrate 101 that can form any microstructure features therein, such as circuit elements of an integrated circuit. Substrate 101 can represent any suitable material for forming microstructures such as semiconductor devices. For example, the substrate 101 may represent a silicon-based substrate in the form of a bulk silicon substrate or a silicon-on-insulatoe (SOI) substrate, as in a large number of major Complex integrated circuits, such as microprocessors, memory chips, ASICs, etc., are now manufactured on the basis of germanium. However, it should be understood that any other suitable semiconductor material may be used, such as semiconductor regions including different compositions (eg, tantalum, tantalum carbide, etc.), different crystallographic orientations, different internal strains of germanium-based materials, or A substrate comprising any compound semiconductor material (eg, II-IV semiconductor, III-V semiconductor, etc.).

The semiconductor device 100 can form one or more metallization layers on the substrate 101, wherein, in the illustrated embodiment, the two metallization layers 110 and 120 are formed in a layer stack. The metallization layer 110 may include a dielectric layer 111 and metal lines 112 formed in the dielectric layer 111. Similarly, the metallization layer 120 can include a plurality of metal lines 122 formed in the dielectric layer 121, wherein the one or more metal lines 122 can be connected to the lower metallization layer 110 via the vias 123. Metal lines 122 and 112 may comprise any suitable metal and, in a particular embodiment, copper, wherein other components may be provided at least partially into metal lines 122 and/or 112 to form a metal alloy. For example, the presence of copper alloys has been found to enhance the properties of individual metal lines in terms of electrical and stress migration resistance. Moreover, when layers 120 and 110 represent a copper-based metallization layer, a suitable barrier layer can be provided to avoid improper diffusion of copper to adjacent dielectric material layers 111 and 121. For the sake of convenience, any such barrier layers are not shown in Figure 1a and may be described in detail later in the description with reference to Figure 2a.

Metal lines 122 in layer 120 may define a width direction 124 that may depict the lateral dimension of metal lines 122. Similarly, the length direction 125 can be defined by a metal line 122 that is substantially perpendicular to the width direction 124 and perpendicular to the plane of the pattern of Figure 1a. It should be appreciated that in an advanced integrated circuit such as a highly complex microprocessor, a plurality of metallization layers, such as layers 110 and 120, are stacked one on another, wherein in each metallization layer, individual metal lines are substantially The individual metal lines in the adjacent metallization layers also extend in parallel, but are substantially perpendicular to the length of the subsequent metallization layer. In this way, any parasitic capacitance between the metal lines of adjacent metallization layers is minimized. In accordance with such configurations, the metallization layer 110 can have metal lines 112 extending in a substantially parallel manner along the "width" direction 124 to reduce capacitive coupling between the lines 122 and 112. It will be appreciated that such configurations may have advantages in overall performance, and in the following, in terms of heat treatment to modify the crystalline structure, a particular length direction is individually defined for each metallization layer 110, 120. In other embodiments, some or all of the metal lines 112 and 122 may define their particular width direction 124 and length direction 125 such that the corresponding "directional" heat treatment may be performed in an individual manner.

Figure 1b shows a plan view of a substrate 101 comprising a plurality of wafer regions 130, each of which may comprise a semiconductor device, such as semiconductor device 100 of Figure 1a. Moreover, wafer region 130 is shown as exposing metallization layer 120, with length direction 125 of metal line 122 now being horizontally directed. However, the orientation of the metal line 122 in the figure is merely descriptive, and thus the scan direction is defined in the length direction 125. It should be further appreciated that the dimensions of the wafer region 130 are significantly magnified relative to the substrate size, and particularly the size of the metal lines 122.

The semiconductor device 100 can be formed in accordance with a completely established process, which can be described with reference to the embodiment of FIG. 2a and subsequent damascene techniques. In other embodiments, when the metallization layers 110 and 120 are aluminum-based metallization layers, the metal lines 112 and 122 can be formed by depositing aluminum on the basis of widely recognized deposition techniques, such as chemical vapor deposition, sputtering. Deposition and so on. Thereafter, the metallization layer can be patterned by photolithography and a completely established etching technique, thereby forming metal lines 112 and 122 and vias 123. Thereafter, a heat treatment may be performed to change the crystalline structure of the metal lines 112 and 122, as described below, or according to other embodiments, the individual metal lines 112 and 122 may be undulated by deposition of a suitable dielectric material and planarization (topography) ) the dielectric layers 111, 121 are embedded.

A narrative embodiment that changes the crystal structure of the metal lines 112 and/or the amount of contaminants thereof irrespective of the process sequence for forming the metal lines 112, 122 will be described in detail below.

FIG. 1c depicts a system 150 that is configured to perform a heat treatment on metal line 122 to change the temperature along the length direction 125 in a time series manner during the heat treatment. For this purpose, system 150 can include a heat source 151 that is configured to establish a locally restricted heating zone on or in substrate 101 with a heated zone. In a narrative embodiment, heat source 151 can include a source for establishing a beam of radiation or a beam of particles to create a localized beam spot 153 on or in substrate 101, wherein beam spot 153 can represent a locally confined heating zone. example. In a particular embodiment, beam 152 may represent a laser beam having specific characteristics such as wavelength, intensity, etc. to produce the desired heat in locally confined heating region 153. Heat source 151 can include any device (not shown) needed to form the beam 152 to exhibit the desired characteristics. For example, associated beam optics, such as mirrors, lenses, etc., can provide beam 152 for focusing and directing onto localized regions of substrate 101. Furthermore, the system 150 is configured to establish a relative motion between the substrate 101 and the heat source 151, with the scanning of the localized confinement region 153 moving at least along the length direction 125. For example, system 150 can include a moveable substrate holder 154 that can be moved at least along length direction 125. In other cases, the substrate holder 154 can also be moved in other directions, such as transverse to the length direction 125, and can also move vertically, i.e., along the direction of the beam 152.

During operation of system 150, substrate 101 can be suitably positioned on substrate holder 154 to allow relative movement generally along the length direction 125 of at least one metal line 122. If metal lines 122 are provided in substantially parallel lines, all metal lines 122 may define a common length direction 125.

FIG. 1d is a partial enlarged view of a metallization layer 120 having a plurality of metal lines 122 exposed to a heat source 151. In the illustrated exemplary embodiment, beam 152 produces a locally confined beam spot or heating region 153 that covers a portion of one or more of metal lines 122. In this case, beam spot 153 defines a locally confined heating zone created by heat source 151. It should be noted that the intensity profile within the heating zone 153 may not need to be uniform. Therefore, the intensity of the heating zone and thus the temperature distribution in the line 122 can be locally varied within the heating zone 153 depending on the scanning speed, the beam spot size, and the overall intensity of the beam, absorption characteristics, and the like. The heat source 151 can be dimensioned such that the temperature at the beam spot 153, and thus the temperature in the locally confined region, exceeds a particular target temperature that causes the metal line 122 to be crystallized within the portion of the beam spot 153 that is affected by the beam spot 153. Reconfiguration. It will be appreciated that the energy normally released into the locally confined heating zone 153 by the heat source 151 is typically scaled such that the zone 153 reaches the target temperature during the time interval and it does not allow significant heat transfer in the wire 122. As a result, portions of the heated region 153 adjacent the heating region metal lines 122 are significantly cooler and can substantially maintain their existing crystalline structure. Thus, by establishing the relative movement of the substrate 101 and the heat source 151, the heating region 153 can be scanned along the length direction 125 and thus sequentially heat portions of the line 122, thereby allowing the crystalline structure of the current heated portion to have a similar heating The crystal structure is now cooled to a fraction below the target temperature to "freeze" the crystal structure that has just been obtained. In this manner, the grain size in the metal line 122 can be increased in the length direction 125, thereby significantly reducing the number of grain boundaries per unit length. For example, in a copper-based metal line, the grain size in the length direction 125 can reach 10 microns or even larger.

In some embodiments, the extension of the locally confined heating region 153 in the length direction 125 can be selected to be a few microns or less to enable efficient recombination because the region size is less than the desired grain size. The scanning movement can be performed in a substantially continuous manner, such as continuously moving the substrate holder 154 according to a particular speed, or in other embodiments, a substantially stepwise movement can be established, wherein the dwell time after each step can be adjusted ( Dwell time) and step size to achieve the desired degree of overlap between the "mobile" heating zones 153. According to the horizontal extension of the locally confined heating zone 153, i.e., the vertical direction in Fig. 1d, one or more of the wires 122 may be subjected to lateral movement correspondingly after heat treatment in the above manner. In some embodiments, it may be advantageous to maintain the temperature "stress" of the dielectric material surrounding the metal line 122 at a low level. In this case, the scanning operation along the length direction 125 may be repeated one or several times and an appropriate temperature is generated within the heating region 153. For example, a typical effective temperature for the heated zone can be selected to be about 100 to 400 °C.

In a narrative embodiment, the heat treatment having a locally localized heating zone, as represented by beam spot 153, can be performed at least partially in a sub-atmospheric atmosphere or vacuum atmosphere to simultaneously promote outgassing of any contaminants contained in metal line 122. . For this purpose, at least a portion of the substrate holder 154 can be placed in an individual process chamber 160 that allows for the establishment of a suitable atmosphere and, in particular, the establishment of a sub-atmospheric atmosphere, and in other instances, the establishment of a vacuum atmosphere. In these embodiments, heat source 151 may be attached to process chamber 160 or may be coupled to process chamber 160 in a manner that beam 152 may be directed and without undesirable wear and tear. In other cases, heat source 151 can be placed (at least partially) in an individual process chamber. In some embodiments, the substrate 101 can be preheated in a sub-atmospheric or vacuum atmosphere to further promote outgassing throughout the directional heating of the wire 122 and/or maintain the wire 122 at elevated temperatures, thereby mitigating The heat source 151 limits the exposure of the metal line 122 of the moving heating zone 153 above the target temperature.

In yet another embodiment, the heat treatment can include a further step in which the metal line 122 is exposed to a reduced pressure gas atmosphere to thereby provide a substantially non-oxidized metal surface of the metal line 122. For this purpose, a forming gas or other mixture of hydrogen and blunt gas, such as argon, helium, neon, etc., may be introduced into the process chamber 160, wherein the pressure range may range from sub-atmospheric conditions to atmospheric or elevated Pressure conditions. The heat treatment under the reduced pressure atmosphere may be performed simultaneously with the directional zone heating, or may be performed after the zone heating process step. For example, in a descriptive embodiment, the first heat treatment step can be performed in a vacuum atmosphere when the wire 122 is heated by the directional region, and in another embodiment, the non-directional heating can be performed before the region is heated. The step and vacuum atmosphere can be maintained during subsequent zone heating. Thereafter, a second heat treatment, which may include a non-directional and/or directional heating step, may be performed in a reduced pressure atmosphere to enhance the metal purity of the line 122.

1e is a plan view of the substrate 101, wherein the heat source 151 or at least a portion thereof is configured to enable time series or directional heat treatment in the extended "vertical" portion of the substrate 101, or to heat the non-scanning direction across the entire substrate 101. The localized limited heating region 153 can be generated, that is, the vertical direction indicated by the arrow 161 in Fig. 1e. To this end, the heat source 151 can include a suitable beam optic (not shown) to shape the beam 152 in a vertical direction into a longitudinal shape. For example, heat source 151 can include a plurality of optical fibers (not shown) that are vertically aligned to provide a plurality of closely spaced laser beams on substrate 101. Furthermore, the provision of a plurality of optical fibers also allows the use of two or more laser sources, and the energy required to scan large diameter substrates such as 200 mm or 300 mm substrates may not be provided by a single laser. Again, a suitable focusing element, such as a lens, can be provided at the end of the fiber to produce the desired high-focus laser beam. On the other hand, individual optical couplers can be used to efficiently couple the laser beam and separate it into a plurality of fibers.

Figure 1f is a cross-sectional view of the heat source 151 of Figure 1e, according to a further illustrative embodiment. In this embodiment, the heat source 151 may also extend significantly in the lateral direction, that is, in the vertical direction of the 1st diagram or in the direction perpendicular to the plane of the pattern of the 1fth diagram, wherein the heat is conducted to the plural through the heat transfer medium 155. Strip metal line 122. The heat transfer medium 155 can be provided in the form of a hot gas, such as hot nitrogen or any other suitable substantial blunt gas. In another embodiment, the heat transfer medium 155 can be provided in the form of a vapor of a suitable fluid having a condensation temperature equal to or higher than a target temperature for locally heating the metal line 122. Thus, in this embodiment, when provided on the metal line 122, the heat transfer medium 155 can contact or condense on the metal line 122, thereby locally conducting heat in a highly efficient manner because of direct contact with the metal line 122 and additional generation The latent heat. To provide a thermally conductive medium 155 to the wire 122, the heat source 151 can include a plurality of individual nozzles 156, or can include one or more elongated nozzle channels that extend laterally relative to the length direction 125 so that A nozzle bar or a nozzle "gap" is formed in the non-scanning direction (the vertical direction in Fig. 1e). For example, a single lateral spacing can be provided as an elongated nozzle whereby a plurality of metal wires 122 can be synchronized in accordance with the lateral extension of the elongated nozzle. The one or more nozzles 156 can be configured to supply the thermally conductive medium 155 in a highly localized manner along the length direction 125, wherein the nozzle opening size can be approximately 1 micron and the distance from the metal wire can be maintained within a few microns. In other embodiments, the heat transfer medium 155 can be provided in a liquid form that can be cured after cooling. For example, the molten polymeric material can be "deposited" in a directional manner to provide a locally confined heating zone 153. After the heat treatment, the polymeric material can be removed by a fully established etching process.

In yet another embodiment, the heat source can transfer heat via radiation. In this case, the heat source 151 may include a heating element that extends in the non-scanning direction, but is limited in size in the scanning or length direction 125. For example, the heating element can include a conductor, such as a wire connected to a corresponding power source that heats the wire by flowing a current through the wire. Furthermore, the wires can be bonded to a suitable focusing system that directs thermal radiation onto the metal lines 122, thereby forming a focus line that extends along the non-scanning direction.

When operating the heat source 151 as shown in Figures 1e and 1f, the scanning operation in a continuous or stepwise movement may be performed once, twice or several times, depending on the process and device requirements. Thereby, the distance between the heat source 151 and the wire 122 can be changed to adjust the effective temperature of the moving heating zone 153. Furthermore, the effective temperature can be changed or additionally adjusted by controlling the effective scanning "speed", whether using continuous or stepwise movement.

Further illustrative embodiments of the present invention are now described in more detail with reference to Figures 2a through 2d. 2a is a cross-sectional view of a semiconductor device 200 including a substrate 201 having one or more metallization layers 210, 220 formed thereon. Depending on the nature of the substrate 201, the same criteria as previously explained and referenced to the substrate 101 are employed. At least one of the metallization layers 210, 220 can represent a copper-based metallization layer of an extremely thinned semiconductor device. Thus, metallization layer 210 can include dielectric layer 211, which can be formed of any suitable material, such as a low-k dielectric material, and metallization layer 210 can include metal lines 212 containing copper and/or any alloy thereof. The metal line 212 may be separated from the dielectric layer 211 and the underlying substrate 201 by a suitable barrier layer 217. Similarly, metallization layer 220 can include a dielectric layer 221 composed of any suitable material, such as a low-k dielectric material. The dielectric layer 221 includes a plurality of trenches 226 having a lateral dimension in the width direction 224. In a fine device, the lateral dimension can be on the order of a few micrometers to 100 nanometers and even less. . Again, the groove 226 defines a longitudinal direction 225 and the longitudinal direction 225 is substantially perpendicular to the lateral direction 224. The exposed surface of the dielectric layer 221 and the trench 226 is covered with a barrier layer 227, and a seed layer 228 is formed on the barrier layer 227. The seed layer 228 may be comprised of copper or any other suitable material that facilitates deposition of metal within the trenches 226 in a subsequent electrochemical deposition process. In a narrative embodiment, seed layer 228 is comprised of a material that is substantially the same as the material to be deposited by subsequent electrochemical deposition.

Apparatus 200 as shown in Figure 2a can be formed by the following process. After any circuit elements are formed in or on the substrate 201, the metallization layer 210 can be formed according to a process strategy, as will be explained by the formation of layer 220. That is, a suitable dielectric material is deposited, for example, by a fully established chemical vapor deposition (CVD) technique and/or spin coating technique, followed by formation of trenches 226 in dielectric layer 221 using advanced photolithography and etching techniques. As explained above, in advanced integrated circuits requiring extremely high operating speeds, the trenches 226 formed in the metallization layer 220 are substantially parallel to each other along the length direction 225, and for example, the metal lines 212 may be parallel to each other but oriented For the direction 224. After patterning the dielectric layer 221, the barrier layer 227 can be formed by a fully established sputtering deposition technique, atomic layer deposition (ALD), CVD, or the like. Thereafter, the seed layer 228 may be formed of, for example, sputter deposition or electroless plating or the like. In a particular embodiment, a copper-based material can be deposited as seed layer 228.

Thereafter, device 200 can accept a heat treatment indicated at 230, wherein heat treatment 230 is performed in a manner similar to that described with reference to Figures 1a through 1f. In other words, when scanning along the length direction 225, the heat treatment 230 can be applied in a locally confined manner to heat at least the seed layer 228, i.e., by creating the heated regions as described in Figures 1c through 1f. Thus, by the method of heat treatment 230, the crystalline structure of the seed layer 228 can be altered to reduce the number of grain boundaries by providing an enhanced crystalline structure for electrochemical deposition of subsequent host metals. The heat treatment 230 can be performed in a substantially passive atmosphere or a reduced pressure atmosphere to effectively suppress corrosion and discoloration of the seed layer 228.

Figure 2b illustrates the semiconductor device 220 at a further manufacturing stage. Device 200 includes a metal 229 that is filled in trench 226, wherein excess metal forms a substantially closed layer on metallization layer 220. The metal 229 may be composed of copper and/or a copper alloy including elements such as gold, nickel, palladium and the like. Metal 229 can be formed by electroplating, wherein depending on the complex electrolyte, a trench 226 that is substantially free of void fill can be obtained. Contaminants in the form of accelerators, inhibitors, complexing agents, and the like can be incorporated into the metal 229 during the deposition process and can compromise the properties of the metal 229 when the device 200 is operated. Thus, in a descriptive embodiment, the apparatus 200 as shown in Figure 2b is subjected to a heat treatment in a passive or sub-atmospheric or vacuum atmosphere 235 to promote outgassing of contaminants contained in the metal layer 229. Moreover, in some embodiments, the heat treatment at atmosphere 235 can be designed to simultaneously preheat substrate 200 to a particular temperature to enhance subsequent efficiency of the heat treatment to alter the crystalline structure of metal 229, ie, substrate 201 can be heated to It is lower than the temperature for changing the target temperature of the heat treatment of the crystal structure. In an embodiment, in addition to an additional or additional preheating process and in addition to providing additional or additional sub-atmosphere or vacuum atmosphere 235, device 200 may accept a heat treatment to produce a locally confined heating zone along length direction 225, such as Described in Figures 1c to 1f. In some embodiments, the directional heat treatment can be performed after some of the metal is filled in the line 122. In this case, the filling process can be interrupted to perform directional heat treatment in any suitable manner as described above. After that, the fill process can be resumed. Therefore, the crystallinity of the metal partially filled in the metal line 122 can be improved during the filling process and can also enhance the outgassing of the contaminant. In some embodiments, the intermediate directional heat treatment can be performed more than once to promote overall efficiency. Therefore, the directional heat treatment may or may not be performed immediately after completion of the seed layer 228.

As a result, the crystal structure of the metal layer 229 can be effectively improved to reduce the number of grain boundaries as previously described. When the aforementioned heat treatment 230 (Fig. 2a) is combined with an additional heat treatment scanned along the length direction 225, the overall efficiency can be significantly improved because the metal 229 according to the electrochemical deposition of the seed layer 228 after the directional heat treatment may Enhanced crystalline structures have been provided which can then be improved even more effectively.

According to other illustrative embodiments, heat treatment 230 and/or treatment at atmosphere 235 and/or heat treatment along length direction 225 based on metal layer 229 may be omitted, and substrate 201 as shown in FIG. 2b may be acceptable. The process of removing any excess metal from layer 229. For this purpose, an electrochemical removal process and/or a chemical mechanical polishing (CMP) process can be performed to remove excess metal and barrier layer 227 on the horizontal surface of layer 220. Thereafter, an atmosphere 235 can be established and the contaminants can be ejected by the corresponding metal wires. Further, at this stage of fabrication, in one embodiment, the heat treatment can be performed along the sequence of heating of the metal lines in the length direction 225, as described above and with reference to Figures 1c through 1f. Thus, heat treatment can be performed at atmosphere 235 to simultaneously promote congestion of contaminants, wherein preheating can also be performed to maintain substrate 201 at a particular elevated temperature throughout the directional heat treatment.

In yet another embodiment, a heat treatment may be performed during filling of the metal to line 222 or after forming the metal line 222, wherein the apparatus 200 is exposed to the vacuum atmosphere 235 for a specific period of time, and then exposed to have appropriate The reduced pressure atmosphere of the gas mixture further enhances the purity of the metal line 222. In some embodiments, the heat treatment including at least one step in the vacuum atmosphere 235 and a further step in the reduced pressure atmosphere may be combined with the directional region heating as described in the preceding paragraphs 1a to 1f and 2a, while in other implementations In the example, when the conductivity improvement due to the enhancement of the purity of the metal wire is considered to be sufficient, the district heating can be ignored.

In other embodiments, the dielectric layer 221 may comprise a low-k material such as SiCOH, MSQ, HSQ, SiLK, etc., which upon formation may exhibit reduced mechanical stability as compared to conventional dielectrics, such conventional The dielectric material includes cerium oxide, fluorine-doped cerium oxide, cerium nitride, and the like. By heat treating the metal lines 222, at least the dielectric layer 221 in the vicinity of the metal lines 222 can also be processed. In this manner, mechanical properties such as hardness can be improved because the hardness of some low-k materials can be significantly increased by treatment such as laser light. In some embodiments, the processing of the dielectric layer 221 can be performed substantially over substantially all exposed surface portions of the dielectric layer 221, thereby providing the potential to improve the overall stability of the metallization layer stack including the low-k dielectric material. Sex.

As explained earlier, with reference to Figures 1c to 1e, a heat source (e.g., source 151) for generating a localized heating region scanned along the length direction 225 can provide a radiation beam whose absorbance and hence heat transfer efficiency can be based on, for example, wavelength, Beam characteristics such as particle energy. For example, the wavelength of the laser source can cause an appropriate high reflectivity on the metal, thus reducing the energy transfer from the beam to the metal. Thus, in some embodiments, a heat transfer layer may be formed prior to the directional heat treatment, wherein the characteristics of the heat conductive layer are selected to allow for proper high energy accumulation within the layer, thereby providing enhanced heat transfer for the underlying metal .

Figure 2c illustrates the apparatus 200 after the excess metal step of removing layer 229 described above and after formation of heat conducting layer 236. Thermally conductive layer 236 can comprise any suitable dielectric material, such as a polymeric material, having characteristics to absorb a significant portion of beam 237, which is designed to create a heated region 238 that is locally confined to length. Direction 225, i.e., perpendicular to the plane of the drawing plane of Figure 2c, while in horizontal direction 224, heating region 238 may extend across a plurality of metal lines 222. When the beam 237 includes a laser beam of a particular wavelength, the thickness of the heat conducting layer 236 and the extinction coefficient can be designed to absorb a high proportion of the radiant intensity. The thermally conductive layer 236 can be formed according to a fully established deposition technique, such as PECVD, spin coating, and the like. After formation, heat treatment based on the light beam 237 can be performed to change the crystal structure of the metal line 222. In other embodiments, providing heat transfer layer 236 may also advantageously avoid direct contact of the thermally conductive medium with metal line 222 when heat is transferred via the thermally conductive medium, as described with reference to FIG. 1f. As a result, a variety of heat transfer media, such as super-heated water vapor, can be used without adversely affecting the wire 222.

Figure 2d illustrates device 200 after removal of thermal conduction layer 236, which may be accomplished by any suitable and complete fabrication technique, such as isotropic etching, plasma etching, and the like. During and after removal of the thermally conductive layer 236, an atmosphere 235 representing a sub-atmospheric atmosphere or vacuum atmosphere may be established to promote any outgassing of the contaminants that may have been during electrochemical deposition and/or during the formation and removal of the thermally conductive layer 236. Incorporator. Thereafter, in some embodiments, the atmosphere 235 can be altered to include a reduced pressure gas environment for further enhancing the purity of the metal lines 222.

As a result, the present invention provides techniques that can be used to form metal lines that increase electrical performance characteristics, wherein the metal is provided with enhanced purity and/or improved crystallinity of the metal. The improvement in crystallinity may be performed according to a heat treatment comprising heating of a localized confinement region, wherein the locally confined heating region is scanned along the length of the metal line to reduce the number of grain boundaries in this direction. Furthermore, the heat treatment of scanning the locally limited heating zone along the length direction can be effectively combined with the heat treatment of the sub-atmospheric atmosphere, vacuum atmosphere and reduced pressure atmosphere to promote outgassing of any contaminants in the metal line. In a particular embodiment, a vacuum atmosphere can be established during the first stage of the heat treatment and a reduced pressure atmosphere can be established during the second final stage of the heat treatment, wherein the heat treatment including at least the two atmospheres can be performed without directional area heating or Heating is performed in conjunction with the directional area. Thereby, the zone heating can be carried out at least partially with a vacuum atmosphere and/or at least partially with a reduced pressure atmosphere. As a result, resistance to electrical and stress migration in the metal lines and other stress-inducing material transfer phenomena can be improved, thereby increasing the reliability of the semiconductor including the metallization layer.

The particular embodiments disclosed above are merely illustrative, and it is obvious that the invention may be modified and practiced with different but equivalent aspects. For example, the process steps set forth above can be performed in a different order. Further, the present invention is not intended to be limited to the details of the construction or design shown herein unless otherwise defined by the scope of the claims. The particular embodiments disclosed above may be varied or modified and all such variations are within the scope and spirit of the invention.

100. . . Device

101. . . Substrate

110, 120. . . Metallization layer

111, 121. . . Dielectric layer

112, 122. . . metal wires

123. . . Through hole

124. . . Width direction

125. . . Longitudinal direction

130. . . Wafer area

150. . . system

151. . . Heat source

152. . . beam

153. . . (beam) point or region

154. . . Substrate holder

155. . . Heat transfer medium

156. . . nozzle

160. . . Process chamber

200. . . Device

201. . . Substrate

210, 220. . . Metallization layer

211, 221. . . Dielectric layer

212, 222. . . metal wires

217, 227. . . Barrier layer

224. . . Width direction

225. . . Longitudinal direction

226. . . Trench

228. . . Seed layer

229. . . Metal or metal layer

230. . . Heat treatment

235. . . atmosphere

236. . . Thermal conduction layer

237. . . beam

238. . . Heating zone

The invention may be understood by reference to the following description and the drawings, wherein like reference numerals represent like elements, wherein: FIG. 1a schematically shows a semiconductor device including a metallization layer comprising a plurality of metal lines, in accordance with the present invention. In a descriptive embodiment, the electrical and stress transfer and/or conductivity characteristics of the metal lines are enhanced; Figure 1b schematically shows a plan view of a substrate comprising a plurality of wafer regions, the wafer regions including The semiconductor device shown in Fig. 1a; Figs. 1c and 1d schematically show heat treatment, wherein according to a descriptive embodiment of the invention, the wire temperature changes in a time series manner along the length direction; Fig. 1e schematically shows along a heating process in which the temperature in the length direction changes with time, according to a descriptive embodiment of the present invention, which can be carried out on the basis of a substrate; FIG. 1f schematically shows a heat treatment of FIG. 1e, wherein the heat transfer medium can be further according to the present invention Embodiments are used; Figure 2a schematically shows the formation of a metallization layer formed according to a damascene process during the intermediate manufacturing stage A semiconductor device, wherein the semiconductor device is subjected to a heat treatment according to a descriptive embodiment of the present invention; and FIGS. 2b, 2c and 2d schematically show a semiconductor device in a further advanced manufacturing stage in accordance with various illustrative embodiments of the present invention.

While the invention is susceptible to various modifications and embodiments, However, it is to be understood that the invention is not to be construed as limited to Improvements, equals and choices.

101. . . Substrate

122. . . metal wires

125. . . Longitudinal direction

151. . . Heat source

152. . . beam

153. . . (beam) point or region

154. . . Substrate holder

160. . . Process chamber

Claims (29)

A method of forming an integrated circuit comprising the steps of: forming a metal line in a dielectric layer of a metallization layer of a semiconductor device, the metal line extending along a length direction; performing a heat treatment in a time series manner to vary along the length direction a temperature, wherein the step of performing the heat treatment comprises directing a localized limited beam of at least one of the radiation and the particles onto the first portion of the metal line, and the locally confined beam and the metal line along the length direction A relative movement is generated to illuminate a second portion adjacent the first portion; and a thermally conductive layer is formed on the metal line prior to directing the locally confined beam onto the metal line. The method of claim 1, wherein the step of forming the metal line comprises forming a trench in the dielectric layer and filling the trench with the metal. The method of claim 2, wherein at least a portion of the metal is filled by electrochemical deposition techniques such that excess metal is formed on the metal line, and wherein the heat treatment is performed prior to removing the excess metal. The method of claim 2, wherein the step of filling the metal comprises depositing at least a portion of the metal by an electrochemical deposition process and removing excess metal deposited during the electrochemical deposition process, and wherein This heat treatment is performed after removing the excess metal. The method of claim 1, wherein the relative movement is A substantially continuous movement. The method of claim 1, wherein the locally confined beam comprises a laser beam. The method of claim 1, further comprising removing the heat conducting layer after the heat treatment. The method of claim 7, wherein the metal wire is exposed to one of a sub-atmosphere atmosphere and a vacuum atmosphere before or after the heat-conducting layer is removed to promote outgassing of the contaminant in the metal wire. . The method of claim 1, further comprising exposing the wire to one of a sub-atmospheric atmosphere and a vacuum atmosphere to promote outgassing of contaminants in the wire. The method of claim 9, wherein the heat treatment is performed when the metal wire is exposed to one of a sub-atmospheric atmosphere and a vacuum atmosphere. The method of claim 9, wherein the method comprises exposing the metal wire to a reduced pressure atmosphere after exposing to one of the sub-atmospheric atmosphere and the vacuum atmosphere. The method of claim 1, wherein the heat treatment is performed by guiding the heat transfer medium to a portion of the metal wire in a locally confined manner. The method of claim 12, wherein the heat transfer medium comprises heated blunt gas. The method of claim 12, wherein the heat transfer medium comprises a condensation temperature that is approximately the same as a target temperature of the heat treatment. Vapor. The method of claim 1, wherein the heat treatment comprises preheating the metal wire and locally heating the metal wire to a specific target temperature, and heating the metal wire to the target temperature along the length direction in a time series manner. Above. The method of claim 2, wherein the step of forming the metal line comprises forming a seed layer on a surface of the trench and electrochemically depositing one or more metals on the seed layer. The method of claim 16, wherein the heat treatment comprises at least one first heating process to change a temperature along the length direction of the metal wire, the first heating process after forming the seed layer and completing the one Or a variety of metal deposition before implementation. The method of claim 17, wherein the heat treatment comprises a second heating process to vary the temperature along the length of the metal line, the second heating process being performed after the one or more metal deposits are completed. The method of claim 17, wherein the heat treatment comprises a second heating process after completion of the depositing of the one or more metals, the second heating process being performed at a substantially uniform temperature along the length direction. The method of claim 17, wherein the first heating process comprises scanning a localized beam spot of the beam of at least one of the radiation and the particles along the length direction. The method of claim 20, wherein the light beam comprises a thunder Shoot the beam. A method of forming an integrated circuit, comprising the steps of: forming a metal line in a dielectric layer formed on a substrate including a semiconductor device; performing a heat treatment to change a crystalline structure of the metal line; exposing the metal line In a vacuum atmosphere to promote outgassing of contaminants in the wire; and exposing the wire to a reduced pressure atmosphere after exposure to the vacuum atmosphere. The method of claim 22, wherein the heat treatment comprises designing a heating process for changing the temperature along the length of the metal line in a time series manner. The method of claim 22, wherein the metal line is formed by forming a trench in the dielectric layer and filling the trench with one or more metals. The method of claim 22, wherein the heat treatment is performed at least partially when the metal wire is exposed to at least one of the vacuum atmosphere and the reduced pressure atmosphere. The method of claim 25, wherein the heat treatment comprises designing a heating process for changing the temperature along the length of the metal line in a time series manner. The method of claim 26, wherein the heating process is performed when the metal wire is exposed to at least one of the vacuum atmosphere and the reduced pressure atmosphere. The method of claim 26, further comprising forming a heat conducting layer prior to performing the heating process. The method of claim 28, further comprising removing the heat conductive layer after the heating process after exposing the metal wire to the vacuum atmosphere.