DE102005020061B4 - Technique for making interconnect structures with reduced electrical and stress migration and / or lower resistance - Google Patents

Abstract

A method comprising: forming a metal line (222) in a dielectric layer (221) formed over a substrate (201) comprising a semiconductor device (200); wherein the metal line (222) is formed by forming a trench (226) in the dielectric layer (211), forming a seed layer (228) on surfaces of the trench, filling one or more metals (229) into the trench (226) by an electrochemical Deposition process and removal of excess material deposited during the electrochemical deposition process; Performing a heat treatment (230) to modify a crystalline structure of a portion of the one or more metals (229); Introducing the portion of the one or more metals (229) into a vacuum environment (235) to promote the outgassing of contaminants in the portion of the one or more metals (229), wherein the heat treatment (230) is at least partially performed; while the portion of the one or more metals (229) is exposed to the action of the vacuum environment (235); Introducing the portion of the one or more metals (229) into a reducing environment after introduction to the vacuum environment (235); wherein the heat treatment (230) and introducing the portion of the one or more metals (229) into a reducing environment after depositing the portion of the one or more metals (229) in the trench (226) and before complete deposition of the one or more metals (229) are performed.

Description

FIELD OF THE PRESENT INVENTION

In general, the present invention relates to the fabrication of microstructures, such as advanced integrated circuits, and more particularly relates to fabricating conductive structures, such as metal lines, in integrated circuit metallization layers.

DESCRIPTION OF THE PRIOR ART

In the fabrication of advanced microstructures, such as integrated circuits, there is a constant drive to reduce the feature sizes of microstructure features to improve the performance of these features. For example, in modern integrated circuits, the minimum feature sizes, such as the channel length of field effect transistors, have now reached the range well below 1 μm, thereby improving the performance of these circuits in terms of speed and / or power consumption. As the size of the individual circuit elements is reduced with each new circuit generation, for example, increasing the switching speed of the transistor elements, the available space for interconnecting lines electrically connecting the individual circuit elements also decreases. As a result, the dimensions of these interconnections must be reduced to accommodate the small amount of available space and increased number of circuit elements per unit die area. The reduced cross-sectional area of the interconnect lines, possibly in conjunction with an increase in static power consumption of highly scaled transistor elements, may require the provision of multiple stacked metallization layers to meet the requirements for acceptable current density in the metal lines.

However, modern integrated circuits with transistor elements that have a critical dimension of 0.13 μm and even less may require significantly increased current densities in the individual interconnect lines, despite the provision of a relatively large number of metallization layers, due to the large number of circuit elements per unit area. However, operating the interconnections at increased current densities may entail a number of problems associated with stress induced line impairment, which may ultimately lead to premature failure of the integrated circuit. An important phenomenon in this regard is current-induced material transport in metal lines, also referred to as "electromigration", which can also lead to the formation of voids in and accumulations of material adjacent to the metal lines, resulting in reduced performance and reliability or complete failure of the device may result. For example, aluminum lines embedded in silicon dioxide and / or silicon nitride are often used as metal for metallization layers, and as discussed previously, modern integrated circuits having critical dimensions of 0.13 μm or less may have significantly reduced cross-sectional areas of the metal lines and thus high current densities, whereby aluminum is not very attractive for the production of metallization layers due to the significant electromigration effects.

Therefore, aluminum is increasingly being replaced by copper, which has significantly lower resistance and increased resistance to electromigration effects at higher current densities compared to aluminum. The introduction of copper in the fabrication of microstructures and integrated circuits creates a number of difficult problems due to the property of copper to easily diffuse into silicon dioxide and a variety of low-k dielectric materials. It is therefore typically necessary to provide a barrier layer between the copper and the dielectric material in which the copper lines are embedded in order to ensure the required adhesion and to avoid undesired diffusion of copper atoms into sensitive device areas. Although silicon nitride is a dielectric material that effectively prevents diffusion of copper atoms, the use of silicon nitride as the material of an interlayer dielectric is less desirable because silicon nitride has extremely high permittivity, thereby increasing the parasitic capacitances between adjacent copper lines. Thus, a thin conductive barrier layer which also provides the required mechanical stability to the copper is provided to separate most of the copper from the surrounding dielectric material, and only a thin silicon nitride or silicon carbide or silicon oxide carbide layer in the form of a capping layer is often used At present, tantalum, titanium, tungsten and their compounds with nitrogen and silicon and the like are preferred candidates for a conductive barrier layer, which barrier layer may have two or more sub-layers of different composition to meet the diffusion and adhesion suppression requirements to fulfill.

Another property of copper that makes it significantly different from aluminum is the fact that copper can not be efficiently applied in larger quantities by chemical and physical vapor deposition techniques. Furthermore, copper can not be efficiently patterned by anisotropic dry etch processes, thus requiring a process strategy commonly referred to as damascene or insert technique. In the damascene process, a dielectric layer is first formed, which is then patterned to include trenches and vias which are subsequently filled with copper, where, as stated previously, prior to filling the copper, a conductive barrier layer is provided on sidewalls of the trenches and contact bushings is formed. The deposition of the majority of the copper material into the trenches and vias is typically performed by wet chemical processes, such as electroplating and electroless plating, with the reliable filling of vias having an aspect ratio of five or greater with a diameter of about 0.1 μm or even less is required along with trenches having a width in the range of about 0.1 μm or less to several micrometers. Although electrochemical deposition processes for copper are well known in the electronics board manufacturing art, a substantially void-free filling of high aspect ratio vias is a highly complex and challenging task, the properties of the final copper lines being highly dependent on process parameters, materials, and geometry of the structure of interest , Since the geometry of interconnect structures is dictated by design requirements and therefore can not be changed appreciably with a given microstructure, it is of great importance to consider the influence of manufacturing processes involved in the fabrication of metallization layers and materials, such as conductive and nonconductive barrier layers to estimate and control the copper microstructure and their mutual interaction on the properties of the interconnect structure to ensure both high yield and required product reliability.

Consequently, great efforts have been made to investigate the degradation of copper lines, particularly with regard to electrical and stress migration, and undesired conductivity reduction in extremely reduced size devices to thereby provide new materials and process strategies for producing copper-based metal lines As increasingly stringent requirements are imposed on electrical and stress migration and on the conductivity properties of copper lines for constantly reduced feature sizes in modern devices. Although the exact mechanism of electrical and stress migration in copper pipes is not yet fully understood, it can be seen that cavities located in and on sidewalls and interfaces significantly affect the conductor volume and the underside of the feedthrough Exercise electrical and stress migration behavior. Empirical research has shown that the levels of electrical and stress migration can often depend on the material composition of the metal, the crystalline structure of the metal, the state of interfaces to adjacent materials, such as conductive and dielectric barrier layers, and the like.

For example, in aluminum tubing, crystal grain boundaries provide preferential diffusion paths for stress- and flow-induced material handling events. Since a reduction in the line size tends to cause smaller crystal grains, therefore, a disproportionately high electro- and stress migration can occur. Although grain boundaries are not necessarily preferred diffusion paths in copper-based metal lines, the increased number of grain boundaries can still significantly increase the overall resistance of the copper-based line due to the increased electron scattering at the grain boundaries. Consequently, the highly complex manufacturing process for metallization layers, which includes depositing the metal, subsequently annealing it, and the like, must be controlled to attempt to improve the behavior of the metal interconnect structures in terms of electrical and stress migration and / or conductivity improve.

Therefore, there is a need for an improved technique that enables the fabrication of metal interconnect structures that exhibit less stress and current induced material diffusion and / or increased conductivity even in extremely sized microstructures.

The DE 102 17 876 A1 discloses heating a semiconductor structure with a copper line by means of a laser beam, a hot gas, a plurality of heating lamps and / or a heating wire. This heat treatment is carried out in an atmosphere of nitrogen, argon or helium, or in a vacuum. The heat treatment may be performed after completion of forming the metal lines or after depositing a metal layer from which the metal lines are formed and before a chemical mechanical polishing process.

The US 4,758,533 A discloses, directly prior to forming a capping layer over a metal line, a laser heat treatment in ammonia or Nitrogen only after completion of the deposition of one or more metals, which form the metal line to perform.

OVERVIEW OF THE INVENTION

In general, the present invention is directed to a technique for making metal lines in metallization layers of semiconductor devices, wherein the properties of the metal lines can be improved with respect to electrical and stress migration and / or conductivity by performing heat treatment during and / or after the formation of the metal lines is exerted to thereby improve the electrical behavior of the metal lines. According to the invention, a method of forming a metal line in a dielectric layer comprises the features of claim 1.

In this regard, a vacuum environment is to be understood as an atmosphere with a reduced pressure of the order of a few 1.33 hectopascals (= 1 Torr) and well below, whereas a subatmospheric environment may include pressure conditions that fall within a range of values below but near ambient the production site are up to vacuum pressure conditions.

BRIEF DESCRIPTION OF THE DRAWINGS

Further advantages, objects and embodiments of the present invention are defined in the appended claims and will be more clearly apparent from the following detailed description when studied with reference to the accompanying drawings; show it:

1a 1 schematically illustrates a semiconductor device having a metallization layer that includes a plurality of metal lines and that is to be improved in electrical and stress migration and / or conductivity characteristics, according to illustrative embodiments of the present invention;

1b schematically a plan view of a substrate having a plurality of chip areas, which in turn comprise a semiconductor device, as shown in FIG 1a is shown;

1c and 1d schematically a heat treatment in which a temperature of metal lines along a longitudinal direction varies in a temporally sequential manner according to illustrative embodiments of the present invention;

1e a heating process having a time-varying temperature along a longitudinal direction, wherein the process is performed involving an entire substrate according to illustrative embodiments;

1f schematically the heat treatment 1e wherein a heat transfer medium is used, according to further illustrative embodiments;

2a 12 schematically illustrates a semiconductor device having a metallization layer fabricated in accordance with a damascene process during an intermediate stage of fabrication wherein the semiconductor device is subjected to a heat treatment in accordance with illustrative embodiments of the present invention;

2 B to 2d 12 schematically illustrates the semiconductor device in more advanced stages of manufacture in accordance with illustrative embodiments of the present invention.

DETAILED DESCRIPTION

The present invention is directed to a technique which enables metal lines to be fabricated in metallization layers of even extremely small size semiconductor devices by modifying a crystalline structure of the metals and / or the degree of purity of the metals by means of a heat treatment to thereby improve the properties of the metal lines with regard to resistance to electrical and stress migration and / or with regard to their inherent conductivity. Without limiting the present invention to the following discussion, it is believed that reducing the number of grain boundaries within a metal line can significantly affect the electrical performance of the metal line by reducing electrical and stress migration and / or increasing inherent conductivity. As is known, the crystal structure of metals in metal lines of microstructures may depend significantly on the type of material used, the deposition technique used, the process parameters set during the deposition process, and on previous and subsequent processes of actually depositing the metal.

For example, copper-based metallization layers are currently manufactured using electrochemical deposition techniques, such as electroplating, the grain size and crystalline structure being significantly dependent on the deposition parameters and dimensions of the trenches and vias to be filled with the copper-based metal, since the reduced dimensions of the trenches and bushings can lead to the formation of metal grains with smaller dimensions. Therefore, the inherent conductivity of the copper-based metal due to the increasing charge carrier scattering at the larger number of grain boundaries can be reduced.

As is well known, electrochemical deposition in extremely reduced size trenches and vias in a substantially void-free manner requires the introduction of sophisticated electroplating techniques which require a highly complex electrolytic solution. Thus, a number of additives, such as precipitation suppressors, accelerators, complexing agents, and the like are used in typical electrolyte solutions, which to some extent also remain in the metal after deposition, thus also affecting the resulting inherent conductivity of the metal line. Furthermore, the presence of contaminants in the metal and / or the existence of a plurality of grain boundaries may also exert an influence on the electrical and stress migration behavior, as grain boundaries and / or the contaminants will affect the properties of interfaces between the metal and adjacent materials, such as a diffusion barrier for copper, can influence. Furthermore, the grain boundaries can directly influence the stress-induced material transport, as is the case with aluminum, for example. Thus, by modifying the crystal structure of the metal and / or reducing the amount of contaminants, the overall performance of the metal lines can be improved.

It should be noted that the present invention is particularly advantageous in the context of copper-based metallization layers, as these structures are typically made by the damascene process using electrochemical deposition techniques, thereby producing a large number of small grains and incorporating contaminants of the electrolyte. However, the present invention may also be applied to metal lines formed of other suitable materials, such as aluminum, and thus the present invention should not be considered as limited to copper-based metallization layers, unless such limitations are explicitly set forth in the appended claims.

Related to the 1a to 1f and 2a to 2d Now, further illustrative embodiments of the present invention will be described in more detail.

1a schematically shows a semiconductor device 100 with a substrate 101 which may have formed therein structural elements of microstructures, such as circuit elements of integrated circuits. The substrate 101 may represent any suitable substrate for fabricating microstructures, such as semiconductor devices. For example, the substrate 101 represent a silicon-based substrate in the form of a bulk silicon substrate or a silicon-on-insulator (SOI) substrate, as the majority of complex integrated circuits, such as microprocessors, memory chips, ASICs, and the like, are currently manufactured based on silicon. However, it should be appreciated that other suitable semiconductor materials, such as silicon-based materials having semiconductor regions of different composition, such as silicon / germanium, silicon / carbon, and the like, with different crystallographic orientations, different inherent strain, or substrates with compound semiconductor materials, such as II-VI Semiconductors, III-V semiconductors, and the like can also be used. The semiconductor device 100 can over the substrate 101 have one or more metallization layers, wherein in the exemplary embodiments shown, two metallization layers 110 and 120 are formed as a layer stack. The metallization layer 110 can be a dielectric layer 111 and a metal pipe 112 that are in the dielectric layer 111 is formed. Similarly, the metallization layer 120 several metal pipes 122 which are in a dielectric layer 121 are formed, wherein one or more of the metal lines 122 with the underlying metallization layer 110 by means of a passage 123 can be connected. The metal pipes 122 and 112 may be constructed of any suitable metal and, in a specific embodiment, may include copper, with additional components at least locally in the metal line 122 and or 112 may be provided to form a metal alloy. For example, it has been found that the presence of a copper alloy can improve the properties of a corresponding metal line in terms of its resistance to electrical and stress migration. Further, if the layer 120 and 110 may represent copper-based metallization layers, suitable barrier layers may be provided to prevent unwanted diffusion of copper into the adjacent dielectric materials of the layers 111 and 121 to prevent. For the sake of simplicity, such barrier layers are in 1a not shown and are more detailed with respect to 2a described below.

The metal pipes 122 in the layer 120 can be a width direction 124 define the lateral dimension of the metal lines 122 can identify. Similarly, a length direction 125 through the metal lines 122 be defined, which is substantially perpendicular to the width direction 124 and perpendicular to the plane 1a stands. It should be noted that in modern integrated circuits, such as in very complex microprocessors, several metallization layers, such as the layers 110 and 120 are stacked on each other, wherein in each metallization layer the corresponding metal lines extend in substantially a parallel manner, whereas corresponding metal lines in an adjacent metallization layer also extend parallel but substantially perpendicular to the longitudinal direction of the aforementioned metallization layer. In this way, parasitic capacitances between metal lines of adjacent metallization layers can be minimized. According to such an arrangement, the metallization layer 110 the metal lines 112 so as to be substantially parallel in the "width" direction 124 extend to allow the capacitive coupling between the lines 122 and 112 to reduce. It should be noted that such an arrangement may be advantageous in terms of overall performance and, as described in more detail below with respect to the heat treatment for modifying the crystalline structure, a particular length direction is unique for each metallization layer 110 . 120 Are defined. In other embodiments, some or all of the metal lines may be 112 and 122 their own special width direction 124 and length direction 125 so that a corresponding "directional" heat treatment can be performed individually.

1b schematically shows a plan view of the substrate 101 with several chip areas 120 each of which is a semiconductor device, such as the semiconductor device 100 out 1a , contains. Furthermore, the chip areas 130 so shown that these are the metallization layer 120 expose, taking the length direction 125 the metal line 122 now oriented horizontally. The orientation of the metal line 122 in the drawings is merely illustrative nature and thus defines the length direction 125 the scanning or movement direction. It should be noted that the dimensions of the chip areas 130 with respect to the substrate dimensions and in particular the dimensions of the metal conduit 122 are significantly enlarged.

The semiconductor device 100 can be made in accordance with well-established processes described in embodiments employing a damascene technique with reference to U.S. Pat 2a described later. In other embodiments, when the metallization layers 110 and 120 Aluminum-based metallization layers, the metal lines can 112 and 122 by depositing aluminum based on well established deposition techniques such as chemical vapor deposition, sputter deposition, and the like. Thereafter, the metal layer may be patterned by photolithography and well-established etching techniques, whereby the metal lines 112 and 122 as well as the implementation 123 arise. Thereafter, a heat treatment may be carried out so as to control the crystalline structure of the metal lines 112 . 122 to modify, as described below, or according to other embodiments, the corresponding metal lines 112 and 122 into the corresponding dielectric layers 111 . 121 by depositing a suitable dielectric material and levels of the resulting topography.

Regardless of the process sequence for producing the metal lines 112 . 122 Now, illustrative embodiments will be described for modifying the crystal structure of the metal lines 122 and / or for modifying the content of contaminants described in more detail.

1c schematically shows a system 150 that is formed, a heat treatment on the metal lines 122 perform such that a temperature during the heat treatment along the length direction 125 is varied in a time sequential manner. For this purpose, the system can 150 a heat source 151 formed, which is a locally limited heating zone on or in the substrate 101 to create. In an illustrative embodiment, the heating source 151 a means for generating a collimated radiation or a particle beam, thereby having a locally confined beam spot 153 on or in the substrate 101 to generate, with the beam spot 153 an example of the localized heating zone can be represented. In a specific embodiment, the beam 152 a laser beam having specified properties, such as wavelength, intensity, and the like, to thereby provide the required heat in the localized heating zone 153 to create. The heat source 151 may include further additional means (not shown) for generating the beam 152 are required so that it has the desired properties. For example, corresponding beam optics, such as mirrors, lenses, and the like may be provided to the beam 152 to focus and on a locally limited area of the substrate 101 to judge. Furthermore, the system 150 formed, a relative movement between the substrate 101 and the heating source 151 to generate a scanning movement of the locally restricted zone 153 at least along the longitudinal direction 125 to enable. For example, the system can 150 a movable substrate holder 154 at least along the longitudinal direction 125 is movable. In other cases, the substrate holder 154 be movable in other directions, such as in a further lateral direction perpendicular to the longitudinal direction 125 and may also be vertically movable, ie along the direction of the beam 152 ,

During operation of the system 150 can the substrate 101 suitably on the substrate holder 154 be positioned to a relative movement substantially along the longitudinal direction 125 at least one of the metal lines 122 to enable. If the metal lines 122 are provided as substantially parallel lines, the longitudinal direction 125 common for all metal pipes 122 To be defined.

1d schematically shows an enlarged view of a part of the metallization layer 120 , where several metal lines 122 the action of the heat source 151 are exposed. In the exemplary embodiment shown, the beam generates 152 the localized beam spot or heating zone 153 which in turn is part of one or more metal lines 122 covers. In this case, the beam spot defines 153 the locally limited heating zone coming from the heating source 151 is created. It should be noted that the intensity profile within the heating zone 153 does not necessarily have to be uniform. Thus, the intensity and thus the temperature profile in the pipes 122 caused locally within the heating zone 153 depending on the scanning speed, the beam spot size and the total intensity of the beam, the absorption characteristics, and the like. The heat source 151 can be dimensioned such that a temperature within the beam spot 153 and within the localized heating zone exceeds a specified setpoint temperature which results in reconfiguration of the crystalline structure within the region of the metal conduit 122 made possible by the beam spot 153 being affected. It should be noted that typically from the heat source 151 in the localized heating zone 153 Deposited energy is dimensioned so that the setpoint temperature within the zone 153 within a period of time that does not cause significant heat transfer within the conduit 122 allows. Thus, areas are adjacent to the heating zone 153 the metal line 122 significantly colder and essentially retain their current crystalline structure. Thus, by creating a relative movement between the substrate 101 and the heating source 151 the heating zone 153 along the longitudinal direction 125 be moved and thus in a sequential manner areas of the line 122 whereby the currently heated region can assume a crystalline structure similar to a crystalline structure generated in the region which has been previously heated and which has now cooled below the target temperature to thereby freeze the crystalline structure obtained immediately before ". In this way, the size of the crystal grains within the metal lines 122 in the longitudinal direction 125 are increased, which significantly reduces the number of grain boundaries per unit length. For example, in copper-based metal lines, a grain size in the longitudinal direction 125 of 10 μm or more can be achieved.

In some embodiments, the extent of the localized heating zone 153 in the longitudinal direction 125 be set to a few microns or even less to allow efficient reconfiguration because the zone size is smaller than the desired grain size. The scanning movement may be carried out in a substantially continuous manner, for example by continuously moving the substrate holder 154 at a specified speed, or in other embodiments, may be performed in a substantially stepwise motion, wherein the dwell time after each step and the step size may be adjusted to provide a desired amount of overlap between the "moving" heating zones 153 is obtained. Depending on the lateral extent of the localized heating zone 153 ie in 1d the vertical dimension, a corresponding movement in the lateral direction can be performed after one or more metal lines 122 are heat treated in the manner described above. In some embodiments, it may be advantageous to measure the temperature "stress" on the dielectric material that is the metal lines 122 surrounds, to keep at a low level. In this case, the scanning operation along the longitudinal direction 125 be repeated once or several times at a moderate temperature within the heating zone 153 is produced. For example, a typical effective temperature of the heating zone may be set at about 100 ° C to 400 ° C.

In one illustrative embodiment, the heat treatment may be performed with a moving, localized heating zone such as, for example, the beam spot 153 is at least partially carried out in a subatmospheric environment or a vacuum environment to simultaneously promote the outgassing of contaminants in the metal lines 122 are included. For this purpose, at least the substrate holder 154 in a corresponding process chamber 160 arranged, which enables the generation of a suitable atmosphere and in particular the provision of a subatmospheric environment, and in one embodiment, a Vacuum environment, allows. In these embodiments, the heating source 151 at the process chamber 160 be attached or can with the process chamber 160 be coupled so that the beam 152 can be introduced without unnecessary losses. In other cases, the heat source 151 at least partially in the appropriate process chamber 160 to be ordered. In some embodiments, the substrate may be 101 be pretreated by heat in the subatmospheric environment or vacuum environment to prevent outgassing during the entire directional heating of all metal lines 122 to promote and / or to the metal lines 122 to keep at an elevated temperature, in order to meet the requirements for the heating source 151 for raising the temperature of the metal pipes 122 coming from the moving heating zone 153 be acted to reduce beyond the target temperature addition.

In still other embodiments, the heat treatment may include a further step in which the metal lines 122 exposed to a reducing gas environment, thereby forming a substantially unoxidized metal surface of the metal lines 122 to accomplish. For this purpose, a forming gas or other water mixtures with inert gases, such as argon, xenon, krypton and the like in the process chamber 160 The pressure may range from subatmospheric conditions to atmospheric or elevated pressure conditions. The heat treatment based on a reducing environment may be performed simultaneously with the directional zone heating, or may be performed after the process step with the zone related heating. For example, a first heat treatment step may be performed in a vacuum environment, while in one illustrative embodiment, the metal lines 122 the directional zone heating, whereas in other embodiments a non-directional heating step may be performed prior to zone heating, and the vacuum environment may be maintained during subsequent zone heating. Thereafter, a second heat treatment, which may include a non-directional and / or a directional heating step, may be performed in the reducing environment to increase the purity of the metal of the conduits 122 to improve.

1e schematically shows the substrate 101 in a plan view, wherein the heat source 151 or at least a portion thereof is formed such that a temporally sequential or directionally dependent heat treatment at an extended "vertical" area of the substrate 101 is possible, or that generating the localized heating zone 153 over the entire substrate 101 away in the direction not to be scanned, ie in 1e that by the arrow 161 displayed vertical direction, is possible. For this purpose, the heat source 151 include a suitable beam optic (not shown) to the beam 152 in a vertical direction to bring in an elongated shape. For example, the heat source 151 a plurality of glass fibers (not shown) arranged vertically so that a plurality of closely spaced laser beams on the substrate 101 to be provided. Furthermore, the provision of multiple optical fibers may also permit the use of two or more individual laser sources if the energy required to scan large diameter substrates, such as 200 mm or 300 mm substrates, is not practical with a single laser. Furthermore, a suitable focusing element, such as a lens, may be provided at the end of each optical fiber to produce a desired highly focused laser beam. On the other hand, corresponding optical couplers can be used to efficiently couple the laser beam and divide it into a plurality of optical fibers.

1f shows schematically the heat source 151 out 1e according to another illustrative embodiment in a cross-sectional view. In this embodiment, the heat source 151 also noticeably extend in the lateral direction, ie in 1e the vertical direction or the direction perpendicular to the plane of the drawing 1f where heat is on multiple metal lines 122 by means of a heat transfer medium 155 is transmitted. The heat transfer medium 155 may be provided in the form of a hot gas, such as hot nitrogen, or other suitable substantially inert gas. In other embodiments, the heat transfer medium 155 be provided in the form of vapor of a suitable liquid having a condensation temperature which is at or above the desired temperature for the local heating of the metal lines 122 lies. In this embodiment, thus, the heat transfer medium 155 if it's on the metal wires 122 is applied, contact or condense on this, locally heat in an extremely efficient manner due to the direct contact with the metal line 122 and due to the additional generation of latent heat. For supplying the heat transfer medium 155 on the metal lines 122 can the heat source 151 several individual nozzles 156 or may include a single or multiple elongate nozzle channels extending laterally with respect to the longitudinal direction 125 so as to form a nozzle rod or a nozzle "gap" in the non-scanning direction (see FIG 1e the vertical direction). For example, a single lateral gap may be one elongated nozzle be provided, thereby allowing the simultaneous treatment of multiple metal lines 122 depending on the lateral extent of the elongated nozzle is possible. The one or more nozzles 156 can be designed to be the heat transfer medium 155 in a highly localized manner along the longitudinal direction 125 in that the nozzle orifice has a size of about 1 μm and the distance to the metal pipe is kept within a range of about several microns. In other embodiments, the heat transfer medium 155 be provided in the form of a liquid which solidifies after deposition. For example, a molten polymeric material may be "deposited" in a directional manner to provide the localized heating zone 153 provide. After the heat treatment, the polymer material may be removed by well established etching techniques.

In still other embodiments, the heating source may transmit heat by radiation. In this case, the heat source 151 a heating element elongated in the non-scanning direction, but in the scanning or longitudinal direction 125 is limited in the great. For example, the heating element may comprise a conductor, such as a wire, which is connected to a corresponding current source for heating the wire by impressing a current flow therein. Furthermore, the wire can be integrated into a suitable focusing system that can radiate heat to the metal lines 122 which forms a focused line extending along the non-scanning direction.

During operation of the heating source 151 as they are in the 1e and 1f As shown, a continuous or stepwise scanning operation may be performed once or twice or more often depending on the process and component requirements. This can be a distance between the heat source 151 and the metal lines 122 be varied, thereby increasing the effective temperature of the moving heating zone 153 adjust. Furthermore, the effective temperature may alternatively or additionally be adjusted by controlling the effective sampling "speed" whether continuous or stepwise operation occurs.

Related to the 2a to 2d Now, further illustrative embodiments of the present invention will be described in more detail.

2a shows schematically in cross section a semiconductor device 200 with a substrate 201 formed on one or more metallization layers 210 . 220 having. Regarding the properties of the substrate 201 Apply the same criteria as before with respect to the substrate 101 are set out. At least one of the metallization layers 210 . 220 may represent a copper-based metallization layer of a very small size semiconductor device. Thus, the metallization layer 210 a dielectric layer 211 which may be made of any suitable material, such as a low-k dielectric material, and the like, and the one metal line 212 with copper and / or an alloy thereof, wherein the metal line 212 from the dielectric layer 211 and the underlying substrate 201 through a suitable barrier layer 217 can be separated. Similarly, the metallization layer 220 a dielectric layer 221 composed of any suitable material, such as a low-k dielectric material, and the like. The dielectric layer 221 includes several trenches 226 with a lateral dimension in a width direction 224 , which may be on the order of a few micrometers to 100 nm and possibly less in the most modern components. Furthermore, the trenches define 226 a longitudinal direction 225 that is substantially perpendicular to the lateral direction 224 is oriented. Exposed surfaces of the dielectric layer 221 and the trenches 226 are with a barrier layer 227 covered, on a seed layer 228 is trained. The seed layer 228 may be constructed of copper or other suitable material that facilitates the deposition of a metal within the trenches 226 favors in a subsequent electrochemical deposition process. In one illustrative embodiment, the seed layer 228 essentially the same material that is deposited in the subsequent electrochemical deposition process.

This in 2a shown component 200 can be made by the following processes. After the formation of circuit elements in and on the substrate 201 can the metallization layer 210 According to the process strategies are made, as for the production of the layer 220 be explained. That is, a suitable dielectric material is deposited, for example, based on well-established CVD (chemical vapor deposition) techniques and / or spin-on techniques, followed by advanced photolithography and etching techniques, around the trenches 226 in the dielectric layer 221 to build. As previously explained, in modern integrated circuits which require extremely high operating speeds, the trenches 226 that is in the metallization layer 220 are formed, substantially parallel to each other along the longitudinal direction 225 while, for example, the metal lines 212 are also parallel to each other, but along the direction 224 are oriented. After structuring the dielectric layer 220 can the barrier layer 227 by well-established sputter deposition methods, atomic layer deposition (ALD), CVD, and the like. After that, the seed layer 228 for example, by sputter deposition or electroless plating, and the like. In a specific embodiment, a copper-based material may be used as the seed layer 228 be deposited. Thereafter, but not claimed, the device 200 subjected to a heat treatment by 230 characterized in that the heat treatment 230 is carried out in a similar manner, as with reference to the 1a to 1f is described. In other words, the heat treatment 230 can be done so at least the seed layer 228 in a locally limited way, ie generating a heating zone, as with reference to the 1c to 1f while scanning along the longitudinal direction 225 he follows. Thus, by the heat treatment 230 a crystalline structure of the seed layer 228 be modified so that the number of grain boundaries is reduced, thereby providing an improved crystalline structure for the subsequent electrochemical deposition of the major part of the metal. The heat treatment 230 may be carried out in a substantially inert atmosphere or a reducing atmosphere to effectively prevent corrosion and discoloration of the seed layer 228 to suppress.

2 B schematically shows the semiconductor device 200 in a more advanced manufacturing stage. The component 200 includes a metal 229 that in the trenches 226 is filled with excess metal, a substantially closed layer over the metallization 220 forms. The metal 229 may include copper and / or copper alloy including components such as gold, nickel, palladium, and the like. The metal 229 may be formed by electroplating, wherein based on a complex electrolyte, a substantially void-free filling of the trenches 226 can be achieved. During the deposition process, contaminants in the form of accelerators, suppressors, complexing agents, and the like may be introduced into the metal 229 be incorporated and thus would the performance of the metal 229 during operation of the device 200 affect. Further, in one illustrative embodiment, the device as shown in FIG 2 B shown in a heat treatment in an inert or subatmospheric or vacuum environment 235 in order to promote the outgassing of contaminants in the metal layer 229 are included. Furthermore, in some embodiments, the heat treatment may be in the environment 235 be designed to include the substrate 201 preheat to a specified temperature, thereby improving the efficiency of a subsequent heat treatment to modify the crystal structure of the metal 229 to improve, ie the substrate 201 can be heated to a temperature below the target temperature for a heat treatment to modify the crystalline structure. In other embodiments, additionally or alternatively to the preheating process and additionally or alternatively to providing the sub-atmospheric or vacuum environment 235 the component 200 be subjected to a heat treatment, so as to locally limited heating zones along the longitudinal direction 225 to create, as with respect to the 1c to 1f is described.

According to the z. B. direction-dependent heat treatment carried out after a certain amount of metal in the pipes 122 is filled. In this case, the loading process is interrupted to carry out the directional heat treatment in a suitable manner as described above. Thereafter, the refilling process is continued. Thus, the crystal structure of the metal in the partially filled metal lines 122 be improved during the refilling process and also the outgassing of contaminants can be intensified. In some embodiments, such an intermediate directional heat treatment may be performed more than once to improve overall efficiency. In this case, a direction-dependent heat treatment immediately after the completion of the seed layer 238 be executed or not.

Thus, the crystalline structure of the metal layer 229 be efficiently modified so as to reduce the number of grain boundaries, as also previously described. If the previously performed heat treatment 230 (please refer 2a ) is combined with an additional heat treatment along the longitudinal direction 225 carried out, the overall efficiency can be significantly increased, since the electrochemical deposition of the metal 229 based on the directionally heat treated seed layer 228 already provide an improved crystalline structure, which can then be improved even more efficiently.

According to other illustrative embodiments, the heat treatment 230 and / or the treatment in the environment 235 and / or the heat treatment along the longitudinal direction 225 scanning takes place on the basis of the metal layer 229 be omitted, and the substrate 200 as it is in 2 B Shown is a process of removing excess metal from the layer 229 subjected. For this purpose, an electrochemical removal process and / or a chemical mechanical polishing (CMP) process to remove the excess metal and the barrier layer 227 on horizontal surfaces of the layer 220 to remove. After that, the environment can 235 created and contaminants are expelled from the corresponding metal lines. Further, in this embodiment, in one embodiment, the heat treatment may be carried out to sequentially restrict restricted portions of the metal lines along the longitudinal direction 225 to heat up as previously related to the 1c to 1f is described. This can be the heat treatment in the environment 235 be carried out simultaneously to promote the outgassing of contaminants, wherein a preheating can take place to the substrate 201 at a specified elevated temperature throughout the directional heat treatment.

In still other embodiments, while metal is being filled into the conduits 222 or after the production of the metal lines 222 a heat treatment be carried out, in which the device 200 in a vacuum environment 235 is introduced for a specified period of time and can then be introduced into a reducing environment with a suitable gas mixture, as previously specified, to ensure the purity of the metal lines 222 continue to improve. In some embodiments, the heat treatment may include at least one step with the vacuum environment 235 and a further step involving a reducing environment, combined with directional zone heating, as previously described with reference to FIGS 1a to 1f and 2a whereas, in other embodiments, zone-related heating may be omitted if the improvement in conductivity due to improved metal line cleanliness is considered sufficient.

In other embodiments, the dielectric layer 221 may be constructed of a low ε material, such as SiCOH, MSQ, HSQ, SiLK, and the like, which inherently exhibit lower post-fabrication mechanical stability compared to well-proven dielectrics, such as silicon dioxide, fluorine-doped silicon dioxide, silicon nitride, and the like. By heat treatment of the metal lines 232 can also be the dielectric layer 221 at least near the metal lines 232 be treated. In this way, the mechanical properties, such as the hardness, can be improved because the hardness of some materials with low ε increases significantly when treated with, for example, a laser beam. In some embodiments, the treatment of the dielectric layer 221 on almost all exposed surface areas of the dielectric layer 221 which offers the possibility of improving the overall stability of a metallization layer stack containing low-k dielectric materials.

As before with reference to the 1c . 1d and 1e is explained, the heat source, about the source 151 for producing localized heating zones along the longitudinal direction 225 be guided, a beam whose absorption and thus its effectiveness for the heat transfer of beam properties, such as wavelength, particle energy, and the like may depend. For example, the wavelength of a laser source can result in moderately high reflectivity to metal, thereby limiting the efficiency of energy transfer from the beam to the metal. Thus, in some illustrative embodiments, a heat transfer layer may be formed prior to the directional heat treatment, wherein the properties of the heat transfer layer are adjusted to allow moderately high energy deposition within the layer, thereby achieving improved heat transfer to the underlying metal.

2c schematically shows the device 200 after the sequence described above to remove excess material of the layer 239 and after forming a heat transfer layer 236 , The heat transfer layer 236 may be constructed of any suitable dielectric material, such as a polymeric material, and the like having properties to provide a significant portion of a beam 237 to absorb, which is designed to be a heating zone 238 to create locally in the longitudinal direction 225 is limited, ie in the direction perpendicular to the plane of the 2c while in the lateral direction 224 the heating zone 238 several metal pipes 222 can span. If the beam 237 a laser beam having a specified wavelength, the thickness and the extinction coefficient of the heat transfer layer 236 be designed to absorb a high proportion of the radiation intensity. The heat transfer layer 236 can be formed according to well established deposition techniques, such as plasma assisted CVD, spin-on techniques, and the like. After production, the heat treatment can be based on the beam 237 be executed to the crystalline structure of the metal lines 222 to modify. In other embodiments, when heat is transferred via a heat transfer medium, as described with reference to FIGS 1f described, the provision of the heat transfer layer 236 also be advantageous in that a direct contact of the heat transfer medium with the metal lines 222 is prevented. Thus, a variety of heat transfer media, such as superheated steam, can be used without adversely affecting the metal lines 222 to influence.

2d schematically shows the device 200 after removing the heat transfer layer 236 which can be accomplished by suitable and well-established methods, such as isotopic etching, plasma etching, and the like. During and after removal of the heat transfer layer 236 becomes the environment 235 , which represents a subatmospheric environment or a vacuum environment, is designed to promote the outgassing of contaminants during electrochemical deposition and / or during manufacture and removal of the heat transfer layer 236 were installed. Thereafter, in some embodiments, the environment 235 be modified so that this a reducing atmosphere for further improving the purity of the metal lines 222 having.

Thus, the present invention provides a technique that enables the formation of metal lines with improved electrical performance characteristics by providing the metal with improved purity and / or modifying the crystal structure of the metal. The modification of the crystal structure may be carried out on the basis of a heat treatment including annealing a locally restricted zone, the locally heated zone being guided along a longitudinal direction of the metal line so as to reduce the number of grain boundaries in that direction. Furthermore, the heat treatment with localized heating zones routed along the longitudinal direction can be efficiently combined with a heat treatment in a subatmospheric environment, a vacuum environment, and a reducing environment to promote the outgassing of contaminants in the metal lines. In particular embodiments, a vacuum environment may be prepared during a first phase of the heat treatment, and a reducing environment may be prepared in a second final phase of the heat treatment, wherein this heat treatment including at least two of these environments may be carried out without directional zone heating, or can be combined with a directional zone heating. In this case, the zone heating can be carried out at least partially if the vacuum environment is established and / or if the reducing environment is at least partially established. As a result, the resistance to electrical and stress migration and other load-induced material transport phenomena in metal lines can be improved, thereby also increasing the reliability of semiconductor devices with metallization layers.

Claims (6)

Method with: forming a metal line ( 222 ) in a dielectric layer ( 221 ) over a substrate ( 201 ) is formed, which is a semiconductor device ( 200 ) having; the metal line ( 222 ) by forming a trench ( 226 ) in the dielectric layer ( 211 ), Forming a seed layer ( 228 ) on surfaces of the trench, filling one or more metals ( 229 ) in the ditch ( 226 ) is formed by an electrochemical deposition process and removal of excess material deposited during the electrochemical deposition process; Performing a heat treatment ( 230 ) to form a crystalline structure of a portion of the one or more metals ( 229 ) to modify; Introducing the part of the one or more metals ( 229 ) in a vacuum environment ( 235 ) to prevent the outgassing of contaminants in the part of the one or more metals ( 229 ), whereby the heat treatment ( 230 ) is at least partially carried out while the part of the one or more metals ( 229 ) the influence of the vacuum environment ( 235 ) is exposed; Introducing the part of the one or more metals ( 229 ) in a reducing environment after introduction into the vacuum environment ( 235 ); the heat treatment ( 230 ) and the introduction of the part of the one or more metals ( 229 ) in a reducing environment after the deposition of the part of the one or more metals ( 229 ) in the trench ( 226 ) and before complete separation of the one or more metals ( 229 ). The method of claim 1, further comprising performing a second heat treatment performed in the reducing environment. Process according to claim 1 or 2, wherein the heat treatment ( 230 ) comprises a heating process that is designed to maintain a temperature along a longitudinal direction ( 225 ) of the metal line ( 222 ) in a time sequential manner. The method of claim 2, wherein the second heat treatment includes a heating process configured to have a temperature along a longitudinal direction. 225 ) of the metal line in a time sequential manner. The method of claim 3, further comprising forming a heat transfer layer (16). 236 ) before performing the heating process. The method of claim 5, further comprising: removing the heat transfer layer (16) 236 ) after the heating process while the metal line ( 222 ) the influence of the vacuum environment ( 235 ) is exposed.

Images