WO2006085465A1 - Lc filter composite module - Google Patents

Lc filter composite module Download PDF

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Publication number
WO2006085465A1
WO2006085465A1 PCT/JP2006/301729 JP2006301729W WO2006085465A1 WO 2006085465 A1 WO2006085465 A1 WO 2006085465A1 JP 2006301729 W JP2006301729 W JP 2006301729W WO 2006085465 A1 WO2006085465 A1 WO 2006085465A1
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WO
WIPO (PCT)
Prior art keywords
built
capacitor
filter
chip
composite module
Prior art date
Application number
PCT/JP2006/301729
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French (fr)
Japanese (ja)
Inventor
Tsuyoshi Suesada
Toshihiro Hosokawa
Kazushige Sato
Toshifumi Oida
Original Assignee
Murata Manufacturing Co., Ltd.
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Publication date
Application filed by Murata Manufacturing Co., Ltd. filed Critical Murata Manufacturing Co., Ltd.
Priority to JP2007502573A priority Critical patent/JPWO2006085465A1/en
Publication of WO2006085465A1 publication Critical patent/WO2006085465A1/en

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Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0233Filters, inductors or a magnetic substance
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01Frequency selective two-port networks
    • H03H7/0115Frequency selective two-port networks comprising only inductors and capacitors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01Frequency selective two-port networks
    • H03H7/17Structural details of sub-circuits of frequency selective networks
    • H03H7/1741Comprising typical LC combinations, irrespective of presence and location of additional resistors
    • H03H7/175Series LC in series path
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01Frequency selective two-port networks
    • H03H7/17Structural details of sub-circuits of frequency selective networks
    • H03H7/1741Comprising typical LC combinations, irrespective of presence and location of additional resistors
    • H03H7/1758Series LC in shunt or branch path
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
    • H03H2001/0021Constructional details
    • H03H2001/0085Multilayer, e.g. LTCC, HTCC, green sheets
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007Types of components
    • H05K2201/1003Non-printed inductor

Definitions

  • the present invention relates to an LC filter composite module, and more particularly to an LC filter composite module used for a mobile communication device or the like.
  • the LC filter composite module described in Patent Document 1 is known.
  • the coil electrode pattern of the inductor L and the capacitor electrode pattern of the capacitor C constituting the L C filter 62 are all provided in the multilayer substrate 61.
  • a ground electrode pattern G is also provided inside the multilayer substrate 61.
  • a surface mounting component 63 such as a chip resistor and a semiconductor device (IC) 64 are mounted.
  • the substrate built-in LC filter 62 of Patent Document 1 requires a high Q value in order to obtain high attenuation in the stop band near the pass band.
  • the Q value of the inductor L deteriorates by blocking the magnetic flux generated in the ground electrode pattern G force inductor L built in the multilayer substrate 61. The For this reason, the coil electrode pattern and the ground electrode pattern G cannot be brought close to each other, and there is a problem that the thickness of the multilayer substrate 61 cannot be reduced.
  • the present inventors do not incorporate the LC filter in the multilayer substrate 71 like the LC filter composite module 70 shown in FIG. 9, but mount it on one main surface of the multilayer substrate 71 as the chip component 72. I thought about what I did.
  • the LC filter configured as the chip component 72 has a built-in ground electrode pattern to suppress the coupling between the coil electrode pattern and the capacitor electrode pattern. The coil electrode pattern and the ground electrode pattern tend to be close to each other. Then, the reason factor similar to that described above is deteriorated, and the Q value of the LC filter is deteriorated, so that the coil electrode pattern and the ground electrode pattern cannot be brought close to each other.
  • the thickness of the multilayer substrate 71 can be made thinner than the multilayer substrate 61 of FIG.
  • there is a limit to downsizing the composite module 70 because a large LC chip component 72 must be installed.
  • Patent Document 1 JP 2000-165273 A
  • an object of the present invention is to provide an LC filter composite module that can obtain high attenuation in the stop band near the pass band and can be sufficiently reduced in height.
  • the LC filter composite module according to the present invention includes:
  • a surface mount component including a chip type inductor mounted on one main surface of the multilayer substrate
  • the surface mount component includes a semiconductor device and the like. It is preferable that the first built-in capacitor and the chip inductor are electrically connected via a via-hole conductor or the like provided in the dielectric layer.
  • the via hole conductor may be provided in a notch or an opening formed in the ground electrode.
  • the LC filter preferably includes a series circuit of a first built-in capacitor and a chip inductor, and the first built-in capacitor is preferably disposed immediately below the chip inductor.
  • the LC filter includes a second built-in capacitor constituted by a capacitor electrode provided inside the multilayer substrate, and the second built-in capacitor is a first built-in capacitor. It may be arranged at a position facing the chip type inductor with a gap therebetween.
  • the LC filter may be a noise-pass filter in which a series circuit of a first built-in capacitor and a chip inductor is electrically shunt-connected to a second built-in capacitor.
  • the LC filter is composed of the first built-in capacitor provided inside the multilayer substrate and the chip inductor, the coil electrode in the chip inductor is connected to the multilayer substrate.
  • the ground electrode force can also be released.
  • the effective height of the LC filter is the sum of the thickness of the multilayer substrate and the height of the chip inductor. In other words, about half of the LC filter is equivalent to being embedded in a multilayer substrate. As a result, a low profile LC filter composite module can be obtained.
  • the first built-in capacitor is arranged in a region at least partially overlapping with the chip inductor when seen in a plan view, the distance between the first built-in capacitor and the chip inductor is reduced, and the parasitic inductance is reduced.
  • the Q value of the LC filter can be increased.
  • the ground electrode has a notch or an opening immediately below the chip inductor, it is possible to prevent the Q value from deteriorating because the ground electrode may not block the magnetic flux generated in the chip inductor.
  • FIG. 1 is a schematic front view showing an embodiment of an LC filter composite module according to the present invention.
  • FIG. 2 is a top view showing (a) the first sheet to (f) the sixth sheet constituting the multilayer substrate of the LC filter composite module of FIG.
  • FIG. 3 is a top view showing (a) the seventh sheet to (f) the twelfth sheet constituting the multilayer substrate of the LC filter composite module of FIG.
  • FIG. 4 is a (a) 13th sheet to (e) top view showing a 17th sheet and (f) a bottom view showing the 17th sheet constituting the multilayer substrate of the LC filter composite module of FIG. 1.
  • FIG. 5 is a schematic diagram showing a vertical cross section of the LC filter composite module shown in FIG. 1.
  • FIG. 6 is an electrical equivalent circuit diagram of the LC filter composite module shown in FIG.
  • FIG. 7 is a graph showing the attenuation characteristics of the LC filter composite module shown in FIG.
  • FIG. 8 is a schematic front view of a conventional LC filter composite module.
  • FIG. 9 is a schematic front view of another conventional LC filter composite module.
  • the LC filter composite module 1 is composed of chip-type inductors LI and L2, which constitute an LC filter on the upper surface of a multilayer substrate 20, surface mount components 3 such as chip resistors, and semiconductor devices ( IC) 4 is mounted.
  • FIGS. 2 to 4 are a top view of dielectric sheets 21a to 21q and a bottom view of dielectric sheet 21q constituting the multilayer substrate 20 of the LC filter composite module 1 of FIG.
  • Dielectric sheets 21a to 21q are prepared by dispersing a ceramic powder mainly composed of barium oxide, aluminum oxide, and silica in a solvent to prepare a ceramic slurry, which is then formed into a sheet by a doctor blade method. obtain.
  • electrode patterns are formed on each of the dielectric sheets 21a to 21q by a screen printing method.
  • lands 22 and 23 for mounting the chip type inductors LI and L2 mounted on the upper surface of the multilayer substrate 20 and the surface mount component 3 are mounted.
  • Land 24 and land 25 for mounting the semiconductor device 4 are formed. That is, as shown by a broken line in FIG. 2 (a), the chip type inductor L1 is connected to the land 22 via a bonding material such as solder, and the chip type inductor L2 is connected via a bonding material such as solder. Connected to Land 23.
  • Capacitor electrode patterns Cpl to Cp8 are formed on the top surfaces of the sixth, thirteenth, fourteenth and fifteenth dielectric sheets 21f, 21m, 21 ⁇ , 21 ⁇ . Further, stripline electrode patterns SL are formed on the top surfaces of the eleventh and twelfth dielectric sheets 21k and 211, respectively.
  • Ground electrode patterns G1 to G5 are formed on the top surfaces of the third, fifth, seventh, tenth, and fifteenth dielectric sheets 21c, 21e, 21g, 21j, and 21o to cover substantially the entire surface of the dielectric sheets.
  • the ground electrode patterns G1 to G5 are used to prevent electromagnetic interference between the surface mount component 4 such as a semiconductor device (IC chip) and circuit elements in the multilayer substrate 20, or to strip the multilayered substrate 20 into the This is necessary for forming a line structure.
  • the ground electrode patterns Gl and G2 disposed in the vicinity of the upper surface of the multilayer substrate 20 have notches (or openings) K directly below the chip inductors LI and L2 when viewed in plan. Yes.
  • the Q values of these chip-type inductors L1 and L2 that do not block the magnetic field generated around the chip-type inductors LI and L2 due to the notches K formed in the ground electrode patterns Gl and G2 in this way. Is not reduced.
  • An external terminal electrode 30 is formed on the bottom surface (Fig. 4 (f)) of the seventeenth dielectric sheet 21q.
  • the first to seventeenth dielectric sheets 21a to 21q have lands 22 to 25, capacitor electrode patterns Cpl to Cp8, stripline electrode patterns SL1 and SL2, ground electrode patterns G1 to G5, and external parts at predetermined positions.
  • a via hole conductor VH for connecting the terminal electrode 30 is provided.
  • the capacitor electrode patterns Cp5, Cp6 constitute first built-in capacitors C5, C6, respectively, facing the ground electrode pattern G3 with the sixth dielectric sheet 21f interposed therebetween.
  • the capacitor electrode patterns Cp2 and Cp3 constitute the second built-in capacitors C2 and C3, respectively, facing the capacitor electrode patterns Cp7 and Cp8 across the thirteenth dielectric sheet 21m.
  • the capacitor electrode patterns Cpl and Cp4 constitute the second built-in capacitors CI and C4, respectively, facing the capacitor electrode patterns Cp7 and Cp8 with the 14th dielectric sheet 21 ⁇ interposed therebetween.
  • the capacitance C for constituting the LC filter includes a built-in capacitor C 5 formed between the capacitor electrode pattern Cp5 and the ground electrode pattern G3, and the capacitor electrode pattern Cp6 and the ground electrode. It is composed of a built-in capacitor C6 formed between the pattern G3.
  • the inductance L for configuring the LC filter is composed of a chip inductor Ll and a chip inductor L2.
  • the chip inductor L1 and the capacitor electrode pattern Cp5 are connected in series via the via-hole conductor VH1, and an LC series resonance circuit of the chip inductor L1 and the built-in capacitor C5 is formed.
  • the chip inductor L2 and the capacitor electrode pattern Cp6 are connected in series via the via-hole conductor VH2, and an LC series resonance circuit of the chip inductor L2 and the built-in capacitor C6 is formed.
  • the hole conductors VH1 and VH2 are notched portions formed in the ground electrode patterns Gl and G2 provided in the layer between the upper surface of the multilayer substrate 20 and the dielectric layer provided with the capacitor electrode patterns Cp5 and Cp6, respectively. It is provided at K.
  • the dielectric sheets 21a to 21q are sequentially laminated with an upper force, and then pressed to form a laminated body block.
  • the laminate block is fired after being cut into a predetermined size.
  • the multilayer substrate 20 is obtained.
  • External electrodes 32 are formed on the end portions of the multilayer substrate 20 by applying and baking a conductive paste.
  • the external electrode 32 is electrically connected to the lead parts such as the ground electrodes G2 to G5.
  • the first built-in capacitors C5 and C6 provided inside the multilayer substrate 20 are arranged immediately below the chip inductors LI and L2.
  • the capacitor electrode patterns Cp5 and Cp6 for forming the first built-in capacitors C5 and C6 are located in a region at least partially overlapping the region where the chip inductors LI and L2 are provided.
  • the second built-in capacitors C1 to C4 are arranged at positions opposite to the chip inductors LI and L2 across the first built-in capacitors C5 and C6.
  • the second built-in capacitors C1 to C4 are placed close to the first built-in capacitors C5 and C6 to shorten the routing pattern. It is not always necessary to place them at positions facing the type inductors L 1 and L2.
  • the chip inductors LI and L2, the first built-in capacitors C5 and C6, and the second built-in capacitors C1 to C4 are electrically connected to form a hynos filter 35.
  • FIG. 6 is an electrical equivalent circuit diagram of the high pass filter 35.
  • a series resonant circuit of first built-in capacitors C5 and C6 and chip inductors LI and L2 is electrically shunt-connected to the second built-in capacitors C1 to C4. This shunt-connected series resonant circuit determines the blocking pole frequency.
  • the resonant frequency of the shunt-connected series resonant circuit can be changed, and the frequency of the stopband also changes.
  • the high-pass filter 35 is mounted on the surfaces of the built-in capacitors C1 to C6 provided inside the multilayer substrate 20 and the multilayer substrate 20.
  • the chip electrode inductors LI and L2 are separated from the ground electrode patterns Gl and G2 arranged in the vicinity of the upper surface of the multilayer substrate 20. it can.
  • the effective height of the hynos filter 35 is the total dimension of the thickness of the multilayer substrate 20 and the heights of the chip inductors LI and L2. That is, about half of the high-pass filter 35 is equivalent to being embedded in the multilayer substrate 20. As a result, a low-profile LC filter composite module 1 is obtained.
  • the first built-in capacitors C5 and C6 are arranged in a region at least partially overlapping the chip inductors LI and L2, and are connected substantially only via via-hole conductors.
  • the parasitic inductance where the distance between the first built-in capacitors C5 and C6 and the chip inductors LI and L2 is reduced can be reduced, and the Q value of the high-pass filter 35 can be increased.
  • the ground electrode patterns Gl and G2 arranged between the first built-in capacitors C5 and C6 and the chip inductors LI and L2 are notched (or notched) directly below the chip inductors LI and L2. Since the opening portion (K) is provided, it is possible to prevent the Q value from deteriorating because the ground electrode patterns Gl and G2 are not likely to block the magnetic flux generated in the chip type inductors LI and L2.
  • the first built-in capacitor C5 and the chip inductor L1 are electrically connected via via-hole conductors VH 1 provided in the first to fifth dielectric sheets 21a to 21e! .
  • the first built-in capacitor C6 and the chip inductor L2 are also electrically connected via via-hole conductors VH2 provided in the first to fifth dielectric sheets 21a to 21e. Since the via-hole conductor generally has a lower resistance value than the thick film conductor, the Q value of the high-pass filter 35 can be further increased.
  • the high-performance L is low in profile and has low unwanted radiation near the passband and low interference wave penetration.
  • Figure 7 shows that the passband is 2.402 to 2.480 GHz, and the stopband near the passband is 2.11.
  • This graph shows the attenuation characteristics of the LC filter composite module 1 equipped with the high-pass filter 35 designed to be 17 GHz. Since the high-pass filter 35 has a high Q value, a steep stopband can be obtained, which makes it difficult to understand.
  • the LC filter composite module according to the present invention is not limited to the above-described embodiment. Various modifications can be made within the scope of the gist.
  • dielectric sheets are stacked to form a laminated body !, but the laminated body is formed by a method in which dielectric slurry and conductive paste are sequentially overcoated. May be.
  • the laminate may be a ceramic multilayer structure in which ceramic green sheets are laminated, or a resin multilayer structure in which a resin layer is laminated.
  • the present invention is useful for LC filter composite modules used in mobile communication devices and the like, and in particular, high attenuation is obtained in the stopband near the passband, and sufficient. It is excellent in that a low profile can be achieved.

Abstract

An LC filter composite module wherein first built-in capacitors (C5, C6) provided inside a multilayer board (20) are arranged directly under chip type inductors (L1, L2), and the first built-in capacitors (C5, C6) are positioned in a region at least partially overlapped with the chip type inductors (L1, L2) in plane view. The chip type inductors (L1, L2), the first built-in capacitors (C5, C6) and second built-in capacitors (C1-C4) are electrically connected to configure a highpass filter (35). Ground electrode patterns (G1, G2) are provided with a notched section or an opening section (K) at a section directly below the chip type inductors (L1, L2). The first built-in capacitors (C5, C6) and the chip type inductors (L1, L2) are electrically connected through a via hole conductor (VH).

Description

明 細 書  Specification
LCフィルタ複合モジュール 技術分野  LC filter composite module technology
[0001] 本発明は、 LCフィルタ複合モジュール、特に、移動体通信装置等に使用される LC フィルタ複合モジュールに関する。  The present invention relates to an LC filter composite module, and more particularly to an LC filter composite module used for a mobile communication device or the like.
背景技術  Background art
[0002] 従来より、 LCフィルタ複合モジュールとして、特許文献 1に記載のものが知られてい る。図 8に示すように、この LCフィルタ複合モジュール 60は、多層基板 61の内部に L Cフィルタ 62を構成するインダクタ Lのコイル電極パターンやコンデンサ Cのコンデン サ電極パターンを全て設けたものである。さらに、多層基板 61の内部にはグランド電 極パターン Gも設けられている。多層基板 61の一方の主面には、チップ抵抗等の表 面実装部品 63及び半導体デバイス (IC) 64が搭載されて ヽる。  [0002] Conventionally, the LC filter composite module described in Patent Document 1 is known. As shown in FIG. 8, in this LC filter composite module 60, the coil electrode pattern of the inductor L and the capacitor electrode pattern of the capacitor C constituting the L C filter 62 are all provided in the multilayer substrate 61. Further, a ground electrode pattern G is also provided inside the multilayer substrate 61. On one main surface of the multilayer substrate 61, a surface mounting component 63 such as a chip resistor and a semiconductor device (IC) 64 are mounted.
[0003] ところで、特許文献 1の基板内蔵 LCフィルタ 62は、通過帯域近くの阻止帯域にお いて高減衰を得るために、高い Q値が必要となる。し力しながら、コイル電極パターン とグランド電極パターン Gが近接して ヽると、多層基板 61に内蔵されたグランド電極 パターン G力インダクタ Lに生じる磁束を遮ることにより、インダクタ Lの Q値が劣化す る。このため、コイル電極パターンとグランド電極パターン Gを近接させることができず 、多層基板 61の厚みを薄くできないという問題があった。  Incidentally, the substrate built-in LC filter 62 of Patent Document 1 requires a high Q value in order to obtain high attenuation in the stop band near the pass band. However, when the coil electrode pattern and the ground electrode pattern G come close to each other, the Q value of the inductor L deteriorates by blocking the magnetic flux generated in the ground electrode pattern G force inductor L built in the multilayer substrate 61. The For this reason, the coil electrode pattern and the ground electrode pattern G cannot be brought close to each other, and there is a problem that the thickness of the multilayer substrate 61 cannot be reduced.
[0004] そこで、本発明者らは、図 9に示す LCフィルタ複合モジュール 70のように、 LCフィ ルタを多層基板 71に内蔵しないで、チップ部品 72として多層基板 71の一方の主面 に搭載したものを考えた。し力しながら、チップ部品 72として構成された LCフィルタ は、コイル電極パターンとコンデンサ電極パターンとの結合を抑制するなどのために グランド電極パターンを内蔵しており、このため、チップ部品 72内部において、コイル 電極パターンとグランド電極パターンが近接した構造になりやすい。そうすると、前述 と同様の理由力 LCフィルタの Q値が劣化するため、コイル電極パターンとグランド 電極パターンを近接させることができず、結果として、チップ部品 72の厚みが厚くな る傾向にある。この結果、多層基板 71の厚みは、図 8の多層基板 61よりも薄くできる ものの、大型の LCチップ部品 72を搭載する必要があるため、複合モジュール 70とし ての小型化には限界があった。 Therefore, the present inventors do not incorporate the LC filter in the multilayer substrate 71 like the LC filter composite module 70 shown in FIG. 9, but mount it on one main surface of the multilayer substrate 71 as the chip component 72. I thought about what I did. However, the LC filter configured as the chip component 72 has a built-in ground electrode pattern to suppress the coupling between the coil electrode pattern and the capacitor electrode pattern. The coil electrode pattern and the ground electrode pattern tend to be close to each other. Then, the reason factor similar to that described above is deteriorated, and the Q value of the LC filter is deteriorated, so that the coil electrode pattern and the ground electrode pattern cannot be brought close to each other. As a result, the thickness of the multilayer substrate 71 can be made thinner than the multilayer substrate 61 of FIG. However, there is a limit to downsizing the composite module 70 because a large LC chip component 72 must be installed.
特許文献 1 :特開 2000— 165273号公報  Patent Document 1: JP 2000-165273 A
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0005] そこで、本発明の目的は、通過帯域近くの阻止帯域において高減衰が得られ、か つ、十分な低背化が可能な LCフィルタ複合モジュールを提供することにある。 [0005] Therefore, an object of the present invention is to provide an LC filter composite module that can obtain high attenuation in the stop band near the pass band and can be sufficiently reduced in height.
課題を解決するための手段  Means for solving the problem
[0006] 前記目的を達成するため、本発明に係る LCフィルタ複合モジュールは、 In order to achieve the above object, the LC filter composite module according to the present invention includes:
(a)複数の誘電体層を積み重ねて構成した多層基板と、  (a) a multilayer substrate formed by stacking a plurality of dielectric layers;
(b)多層基板の一方主面に搭載されたチップ型インダクタを含む表面実装部品と、 (b) a surface mount component including a chip type inductor mounted on one main surface of the multilayer substrate;
(c)多層基板の内部に設けられたコンデンサ電極によって構成された第 1内蔵型コ ンデンサと多層基板の一方主面に設けられたチップ型インダクタとを含んで構成され 、かつ、平面視したとき第 1内蔵型コンデンサがチップ型インダクタと少なくとも一部が 重なる領域に配置されて 、る LCフィルタと、 (c) When including a first built-in capacitor formed by a capacitor electrode provided inside the multilayer board and a chip-type inductor provided on one main surface of the multilayer board, and in plan view An LC filter in which the first built-in capacitor is arranged in a region at least partially overlapping the chip inductor;
(d)多層基板の一方主面の近傍内部に配置され、かつ、平面視したときチップ型ィ ンダクタの直下部分に切欠き部又は開口部を有した状態で誘電体層の略全面に設 けられたグランド電極と、  (d) Arranged in the vicinity of one main surface of the multilayer substrate, and provided on substantially the entire surface of the dielectric layer with a notch or opening in the portion immediately below the chip-type inductor when viewed in plan. Grounded electrodes,
を備えたことを特徴とする。  It is provided with.
[0007] ここに、表面実装部品は半導体デバイス等を含んでいる。第 1内蔵型コンデンサと チップ型インダクタは、誘電体層に設けたビアホール導体等を介して電気的に接続 されていることが好ましい。そして、このビアホール導体は、グランド電極に形成され た切欠き部又は開口部に設けられていてもよい。 Here, the surface mount component includes a semiconductor device and the like. It is preferable that the first built-in capacitor and the chip inductor are electrically connected via a via-hole conductor or the like provided in the dielectric layer. The via hole conductor may be provided in a notch or an opening formed in the ground electrode.
[0008] また、 LCフィルタは第 1内蔵型コンデンサ及びチップ型インダクタの直列回路を含 み、第 1内蔵型コンデンサはチップ型インダクタの直下に配置されていることが好まし い。 [0008] In addition, the LC filter preferably includes a series circuit of a first built-in capacitor and a chip inductor, and the first built-in capacitor is preferably disposed immediately below the chip inductor.
[0009] さらに、 LCフィルタは多層基板の内部に設けられたコンデンサ電極によって構成さ れた第 2内蔵型コンデンサを含み、該第 2内蔵型コンデンサは第 1内蔵型コンデンサ を間にしてチップ型インダクタと対向する位置に配置されていてもよい。 [0009] Further, the LC filter includes a second built-in capacitor constituted by a capacitor electrode provided inside the multilayer substrate, and the second built-in capacitor is a first built-in capacitor. It may be arranged at a position facing the chip type inductor with a gap therebetween.
[0010] また、 LCフィルタは、第 2内蔵型コンデンサに、第 1内蔵型コンデンサ及びチップ型 インダクタの直列回路が電気的にシャント接続されたノヽィパスフィルタであってもよい  [0010] The LC filter may be a noise-pass filter in which a series circuit of a first built-in capacitor and a chip inductor is electrically shunt-connected to a second built-in capacitor.
発明の効果 The invention's effect
[0011] 本発明によれば、 LCフィルタが多層基板の内部に設けられた第 1内蔵型コンデン サとチップ型インダクタとで構成されて ヽるため、チップ型インダクタ内のコイル電極 を多層基板内のグランド電極力も離すことができる。一方、 LCフィルタの実効高さは 多層基板の厚さとチップ型インダクタの高さを合計した寸法となる。つまり、 LCフィル タの約半分が多層基板に埋設されているのと同等である。この結果、低背化された L Cフィルタ複合モジュールが得られる。  [0011] According to the present invention, since the LC filter is composed of the first built-in capacitor provided inside the multilayer substrate and the chip inductor, the coil electrode in the chip inductor is connected to the multilayer substrate. The ground electrode force can also be released. On the other hand, the effective height of the LC filter is the sum of the thickness of the multilayer substrate and the height of the chip inductor. In other words, about half of the LC filter is equivalent to being embedded in a multilayer substrate. As a result, a low profile LC filter composite module can be obtained.
[0012] そして、平面視したとき第 1内蔵型コンデンサがチップ型インダクタと少なくとも一部 が重なる領域に配置されているので、第 1内蔵型コンデンサとチップ型インダクタの 距離が近ぐ寄生インダクタンスを小さくでき、 LCフィルタの Q値を高くできる。さらに 、グランド電極がチップ型インダクタの直下部分に切欠き部又は開口部を有している ので、グランド電極がチップ型インダクタに生じる磁束を遮るおそれがなぐ Q値劣化 を防止できる。  [0012] Since the first built-in capacitor is arranged in a region at least partially overlapping with the chip inductor when seen in a plan view, the distance between the first built-in capacitor and the chip inductor is reduced, and the parasitic inductance is reduced. The Q value of the LC filter can be increased. Furthermore, since the ground electrode has a notch or an opening immediately below the chip inductor, it is possible to prevent the Q value from deteriorating because the ground electrode may not block the magnetic flux generated in the chip inductor.
図面の簡単な説明  Brief Description of Drawings
[0013] [図 1]本発明に係る LCフィルタ複合モジュールの一実施例を示す正面模式図。  FIG. 1 is a schematic front view showing an embodiment of an LC filter composite module according to the present invention.
[図 2]図 1の LCフィルタ複合モジュールの多層基板を構成する(a)第 1シート〜 (f)第 6シートを示す上面図。  FIG. 2 is a top view showing (a) the first sheet to (f) the sixth sheet constituting the multilayer substrate of the LC filter composite module of FIG.
[図 3]図 1の LCフィルタ複合モジュールの多層基板を構成する(a)第 7シート〜 (f)第 12シートを示す上面図。  FIG. 3 is a top view showing (a) the seventh sheet to (f) the twelfth sheet constituting the multilayer substrate of the LC filter composite module of FIG.
[図 4]図 1の LCフィルタ複合モジュールの多層基板を構成する(a)第 13シート〜(e) 第 17シートを示す上面図及び (f)第 17シートを示す下面図。  4 is a (a) 13th sheet to (e) top view showing a 17th sheet and (f) a bottom view showing the 17th sheet constituting the multilayer substrate of the LC filter composite module of FIG. 1.
[図 5]図 1に示した LCフィルタ複合モジュールの垂直断面を示す模式図。  FIG. 5 is a schematic diagram showing a vertical cross section of the LC filter composite module shown in FIG. 1.
[図 6]図 1に示した LCフィルタ複合モジュールの電気等価回路図。  FIG. 6 is an electrical equivalent circuit diagram of the LC filter composite module shown in FIG.
[図 7]図 1に示した LCフィルタ複合モジュールの減衰特性を示すグラフ。 [図 8]従来の LCフィルタ複合モジュールの正面模式図。 FIG. 7 is a graph showing the attenuation characteristics of the LC filter composite module shown in FIG. FIG. 8 is a schematic front view of a conventional LC filter composite module.
[図 9]従来の別の LCフィルタ複合モジュールの正面模式図。  FIG. 9 is a schematic front view of another conventional LC filter composite module.
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0014] 以下に、本発明に係る LCフィルタ複合モジュールの実施例について添付図面を参 照して説明する。 Hereinafter, embodiments of the LC filter composite module according to the present invention will be described with reference to the accompanying drawings.
[0015] 図 1に示すように、 LCフィルタ複合モジュール 1は、多層基板 20の上面に LCフィル タを構成するチップ型インダクタ LI, L2、チップ抵抗等の表面実装部品 3及び半導 体デバイス (IC) 4が搭載されたものである。  [0015] As shown in FIG. 1, the LC filter composite module 1 is composed of chip-type inductors LI and L2, which constitute an LC filter on the upper surface of a multilayer substrate 20, surface mount components 3 such as chip resistors, and semiconductor devices ( IC) 4 is mounted.
[0016] 図 2〜図 4は、図 1の LCフィルタ複合モジュール 1の多層基板 20を構成する誘電体 シート 21a〜21qの上面図及び誘電体シート 21qの下面図である。誘電体シート 21a 〜21qは、酸化バリウム、酸ィ匕アルミニウム、シリカを主成分としたセラミック粉末を溶 剤に分散させてセラミックスラリーを調整し、これをドクターブレード法によりシート状 に成形することにより得る。次に、誘電体シート 21a〜21qのそれぞれにスクリーン印 刷法によって、電極パターンを形成する。  FIGS. 2 to 4 are a top view of dielectric sheets 21a to 21q and a bottom view of dielectric sheet 21q constituting the multilayer substrate 20 of the LC filter composite module 1 of FIG. Dielectric sheets 21a to 21q are prepared by dispersing a ceramic powder mainly composed of barium oxide, aluminum oxide, and silica in a solvent to prepare a ceramic slurry, which is then formed into a sheet by a doctor blade method. obtain. Next, electrode patterns are formed on each of the dielectric sheets 21a to 21q by a screen printing method.
[0017] 第 1誘電体シート 21aの上面には、多層基板 20の上面に搭載されるチップ型インダ クタ LI, L2をそれぞれ実装するためのランド 22, 23、表面実装部品 3を実装するた めのランド 24、半導体デバイス 4を実装するためのランド 25が形成されている。即ち、 図 2 (a)に破線で示すように、チップ型インダクタ L1は、はんだ等の接合材を介して、 ランド 22に接続されており、チップ型インダクタ L2は、はんだ等の接合材を介して、ラ ンド 23に接続されている。  [0017] On the upper surface of the first dielectric sheet 21a, lands 22 and 23 for mounting the chip type inductors LI and L2 mounted on the upper surface of the multilayer substrate 20 and the surface mount component 3 are mounted. Land 24 and land 25 for mounting the semiconductor device 4 are formed. That is, as shown by a broken line in FIG. 2 (a), the chip type inductor L1 is connected to the land 22 via a bonding material such as solder, and the chip type inductor L2 is connected via a bonding material such as solder. Connected to Land 23.
[0018] 第 6、第 13、第 14及び第 15誘電体シート 21f, 21m, 21η, 21οの上面には、コン デンサ電極パターン Cpl〜Cp8が形成されている。さらに、第 11及び第 12誘電体シ ート 21k, 211の上面にはそれぞれ、ストリップライン電極パターン SLが形成されてい る。  Capacitor electrode patterns Cpl to Cp8 are formed on the top surfaces of the sixth, thirteenth, fourteenth and fifteenth dielectric sheets 21f, 21m, 21η, 21ο. Further, stripline electrode patterns SL are formed on the top surfaces of the eleventh and twelfth dielectric sheets 21k and 211, respectively.
[0019] 第 3、第 5、第 7、第 10及び第 15誘電体シート 21c, 21e, 21g, 21j, 21oの上面に は、誘電体シートの略全面を覆うグランド電極パターン G1〜G5が形成されている。 グランド電極パターン G1〜G5は、半導体デバイス (ICチップ)のような表面実装部品 4と多層基板 20内の回路素子との電磁干渉を防止したり、多層基板 20内にストリップ ライン構造を形成したりするなどのために必要なものである。特に、多層基板 20の上 面の近傍内部に配置されるグランド電極パターン Gl, G2は、平面視したときチップ 型インダクタ LI, L2の直下部分に切欠き部(又は開口部) Kを有している。このように グランド電極パターン Gl, G2に切欠き部 Kが形成されていることにより、チップ型ィ ンダクタ LI, L2の周囲に生じる磁界を遮ることがなぐこれらのチップ型インダクタ L1 , L2の Q値を低下させることがない。 [0019] Ground electrode patterns G1 to G5 are formed on the top surfaces of the third, fifth, seventh, tenth, and fifteenth dielectric sheets 21c, 21e, 21g, 21j, and 21o to cover substantially the entire surface of the dielectric sheets. Has been. The ground electrode patterns G1 to G5 are used to prevent electromagnetic interference between the surface mount component 4 such as a semiconductor device (IC chip) and circuit elements in the multilayer substrate 20, or to strip the multilayered substrate 20 into the This is necessary for forming a line structure. In particular, the ground electrode patterns Gl and G2 disposed in the vicinity of the upper surface of the multilayer substrate 20 have notches (or openings) K directly below the chip inductors LI and L2 when viewed in plan. Yes. The Q values of these chip-type inductors L1 and L2 that do not block the magnetic field generated around the chip-type inductors LI and L2 due to the notches K formed in the ground electrode patterns Gl and G2 in this way. Is not reduced.
[0020] 第 17誘電体シート 21qの下面(図 4 (f) )には、外部端子電極 30が形成されている 。さらに、第 1〜第 17誘電体シート 21a〜21qには、所定の位置に、ランド 22〜25、 コンデンサ電極パターン Cpl〜Cp8、ストリップライン電極パターン SL1, SL2、グラ ンド電極パターン G1〜G5及び外部端子電極 30を接続するためのビアホール導体 VHが設けられている。 [0020] An external terminal electrode 30 is formed on the bottom surface (Fig. 4 (f)) of the seventeenth dielectric sheet 21q. In addition, the first to seventeenth dielectric sheets 21a to 21q have lands 22 to 25, capacitor electrode patterns Cpl to Cp8, stripline electrode patterns SL1 and SL2, ground electrode patterns G1 to G5, and external parts at predetermined positions. A via hole conductor VH for connecting the terminal electrode 30 is provided.
[0021] ここで、コンデンサ電極パターン Cp5, Cp6は、第 6誘電体シート 21fを挟んでグラ ンド電極パターン G3に対向してそれぞれ、第 1内蔵型コンデンサ C5, C6を構成する 。コンデンサ電極パターン Cp2, Cp3は、第 13誘電体シート 21mを挟んでコンデン サ電極パターン Cp7, Cp8に対向してそれぞれ、第 2内蔵型コンデンサ C2, C3を構 成する。コンデンサ電極パターン Cpl, Cp4は、第 14誘電体シート 21ηを挟んでコン デンサ電極パターン Cp7, Cp8に対向してそれぞれ、第 2内蔵型コンデンサ CI, C4 を構成する。  Here, the capacitor electrode patterns Cp5, Cp6 constitute first built-in capacitors C5, C6, respectively, facing the ground electrode pattern G3 with the sixth dielectric sheet 21f interposed therebetween. The capacitor electrode patterns Cp2 and Cp3 constitute the second built-in capacitors C2 and C3, respectively, facing the capacitor electrode patterns Cp7 and Cp8 across the thirteenth dielectric sheet 21m. The capacitor electrode patterns Cpl and Cp4 constitute the second built-in capacitors CI and C4, respectively, facing the capacitor electrode patterns Cp7 and Cp8 with the 14th dielectric sheet 21η interposed therebetween.
[0022] 本実施例において、 LCフィルタを構成するためのキャパシタンス Cは、コンデンサ 電極パターン Cp5とグランド電極パターン G3との間に形成される内蔵型コンデンサ C 5、並びに、コンデンサ電極パターン Cp6とグランド電極パターン G3との間に形成さ れる内蔵型コンデンサ C6によって構成されている。 LCフィルタを構成するためのィ ンダクタンス Lは、チップ型インダクタ Ll、チップ型インダクタ L2によって構成されて いる。そして、チップ型インダクタ L1とコンデンサ電極パターン Cp5はビアホール導 体 VH 1を介して直列接続されており、チップ型インダクタ L 1と内蔵型コンデンサ C5 の LC直列共振回路が形成されている。同様に、チップ型インダクタ L2とコンデンサ 電極パターン Cp6はビアホール導体 VH2を介して直列接続されており、チップ型ィ ンダクタ L2と内蔵型コンデンサ C6の LC直列共振回路が形成されている。これらのビ ァホール導体 VH1, VH2は、多層基板 20の上面とコンデンサ電極パターン Cp5, C p6が設けられた誘電体層との間の層に設けられたグランド電極パターン Gl, G2に それぞれ形成された切欠き部 Kに設けられて ヽる。 In this embodiment, the capacitance C for constituting the LC filter includes a built-in capacitor C 5 formed between the capacitor electrode pattern Cp5 and the ground electrode pattern G3, and the capacitor electrode pattern Cp6 and the ground electrode. It is composed of a built-in capacitor C6 formed between the pattern G3. The inductance L for configuring the LC filter is composed of a chip inductor Ll and a chip inductor L2. The chip inductor L1 and the capacitor electrode pattern Cp5 are connected in series via the via-hole conductor VH1, and an LC series resonance circuit of the chip inductor L1 and the built-in capacitor C5 is formed. Similarly, the chip inductor L2 and the capacitor electrode pattern Cp6 are connected in series via the via-hole conductor VH2, and an LC series resonance circuit of the chip inductor L2 and the built-in capacitor C6 is formed. These bi The hole conductors VH1 and VH2 are notched portions formed in the ground electrode patterns Gl and G2 provided in the layer between the upper surface of the multilayer substrate 20 and the dielectric layer provided with the capacitor electrode patterns Cp5 and Cp6, respectively. It is provided at K.
[0023] 各誘電体シート 21a〜21qは上力も順次積層された後、圧着して積層体ブロックと する。積層体ブロックは所定のサイズにカットされた後、焼成される。これにより、多層 基板 20とされる。多層基板 20の端部には、導電ペーストを塗布し、焼き付けることに より外部電極 32が形成される。外部電極 32はグランド電極 G2〜G5等の引出し部に 電気的に接続されている。  [0023] The dielectric sheets 21a to 21q are sequentially laminated with an upper force, and then pressed to form a laminated body block. The laminate block is fired after being cut into a predetermined size. As a result, the multilayer substrate 20 is obtained. External electrodes 32 are formed on the end portions of the multilayer substrate 20 by applying and baking a conductive paste. The external electrode 32 is electrically connected to the lead parts such as the ground electrodes G2 to G5.
[0024] こうして得られた LCフィルタ複合モジュール 1は、図 5に示すように、多層基板 20の 内部に設けられた第 1内蔵型コンデンサ C5, C6がチップ型インダクタ LI, L2の直下 に配置され、平面視したとき第 1内蔵型コンデンサ C5, C6を構成するためのコンデ ンサ電極パターン Cp5, Cp6がチップ型インダクタ LI, L2の設けられる領域と少なく とも一部が重なる領域に位置している。第 2内蔵型コンデンサ C1〜C4は第 1内蔵型 コンデンサ C5, C6を間にしてチップ型インダクタ LI, L2と反対側の対向する位置に 配置されている。なお、本実施例では、第 2内蔵型コンデンサ C1〜C4を第 1内蔵型 コンデンサ C5, C6の近くに配置することによって引き回しパターンを短くしている力 第 2内蔵型コンデンサ C 1〜C4をチップ型インダクタ L 1 , L2と対向する位置に必ずし も配置する必要はない。  In the LC filter composite module 1 obtained in this way, as shown in FIG. 5, the first built-in capacitors C5 and C6 provided inside the multilayer substrate 20 are arranged immediately below the chip inductors LI and L2. In plan view, the capacitor electrode patterns Cp5 and Cp6 for forming the first built-in capacitors C5 and C6 are located in a region at least partially overlapping the region where the chip inductors LI and L2 are provided. The second built-in capacitors C1 to C4 are arranged at positions opposite to the chip inductors LI and L2 across the first built-in capacitors C5 and C6. In this embodiment, the second built-in capacitors C1 to C4 are placed close to the first built-in capacitors C5 and C6 to shorten the routing pattern. It is not always necessary to place them at positions facing the type inductors L 1 and L2.
[0025] これらチップ型インダクタ LI, L2、第 1内蔵型コンデンサ C5, C6及び第 2内蔵型コ ンデンサ C1〜C4は、電気的に接続されてハイノスフィルタ 35を構成している。  The chip inductors LI and L2, the first built-in capacitors C5 and C6, and the second built-in capacitors C1 to C4 are electrically connected to form a hynos filter 35.
[0026] 図 6はハイパスフィルタ 35の電気等価回路図である。第 2内蔵型コンデンサ C1〜C 4に、第 1内蔵型コンデンサ C5, C6及びチップ型インダクタ LI, L2の直列共振回路 が電気的にシャント接続されている。このシャント接続された直列共振回路が阻止極 周波数を決定する。チップ型インダクタ LI, L2のインダクタンス値を変更することによ り、シャント接続された直列共振回路の共振周波数を変化させることができ、阻止帯 域の周波数も変化する。  FIG. 6 is an electrical equivalent circuit diagram of the high pass filter 35. A series resonant circuit of first built-in capacitors C5 and C6 and chip inductors LI and L2 is electrically shunt-connected to the second built-in capacitors C1 to C4. This shunt-connected series resonant circuit determines the blocking pole frequency. By changing the inductance values of chip-type inductors LI and L2, the resonant frequency of the shunt-connected series resonant circuit can be changed, and the frequency of the stopband also changes.
[0027] 以上の構成からなる LCフィルタ複合モジュール 1は、ハイパスフィルタ 35が多層基 板 20の内部に設けられた内蔵型コンデンサ C1〜C6と多層基板 20の表面に搭載さ れたチップ型インダクタ LI, L2とで構成されているため、チップ型インダクタ LI, L2 内のコイル電極パターンを多層基板 20の上面近傍内部に配置されたグランド電極パ ターン Gl, G2から離すことができる。一方、ハイノスフィルタ 35の実効高さは多層基 板 20の厚さとチップ型インダクタ LI, L2の高さを合計した寸法となる。つまり、ハイパ スフィルタ 35の約半分が多層基板 20に埋設されて 、るのと同等である。この結果、 低背化された LCフィルタ複合モジュール 1が得られる。 In the LC filter composite module 1 having the above configuration, the high-pass filter 35 is mounted on the surfaces of the built-in capacitors C1 to C6 provided inside the multilayer substrate 20 and the multilayer substrate 20. The chip electrode inductors LI and L2 are separated from the ground electrode patterns Gl and G2 arranged in the vicinity of the upper surface of the multilayer substrate 20. it can. On the other hand, the effective height of the hynos filter 35 is the total dimension of the thickness of the multilayer substrate 20 and the heights of the chip inductors LI and L2. That is, about half of the high-pass filter 35 is equivalent to being embedded in the multilayer substrate 20. As a result, a low-profile LC filter composite module 1 is obtained.
[0028] そして、平面視したとき第 1内蔵型コンデンサ C5, C6がチップ型インダクタ LI, L2 と少なくとも一部が重なる領域に配置されており、さらに、実質的にビアホール導体の みを介して接続されているので、第 1内蔵型コンデンサ C5, C6とチップ型インダクタ LI, L2の距離が近ぐ寄生インダクタンスを小さくでき、ハイパスフィルタ 35の Q値を 高くできる。 [0028] When viewed in plan, the first built-in capacitors C5 and C6 are arranged in a region at least partially overlapping the chip inductors LI and L2, and are connected substantially only via via-hole conductors. As a result, the parasitic inductance where the distance between the first built-in capacitors C5 and C6 and the chip inductors LI and L2 is reduced can be reduced, and the Q value of the high-pass filter 35 can be increased.
[0029] さらに、第 1内蔵型コンデンサ C5, C6とチップ型インダクタ LI, L2との間に配置さ れたグランド電極パターン Gl, G2がチップ型インダクタ LI, L2の直下部分に切欠き 部(又は開口部) Kを有しているので、グランド電極パターン Gl, G2がチップ型イン ダクタ LI, L2に生じる磁束を遮るおそれがなぐ Q値劣化を防止できる。  [0029] Further, the ground electrode patterns Gl and G2 arranged between the first built-in capacitors C5 and C6 and the chip inductors LI and L2 are notched (or notched) directly below the chip inductors LI and L2. Since the opening portion (K) is provided, it is possible to prevent the Q value from deteriorating because the ground electrode patterns Gl and G2 are not likely to block the magnetic flux generated in the chip type inductors LI and L2.
[0030] また、第 1内蔵型コンデンサ C5とチップ型インダクタ L1は、第 1〜第 5誘電体シート 21 a〜 21 eに設けたビアホール導体 VH 1を介して電気的に接続されて!、る。同様に 、第 1内蔵型コンデンサ C6とチップ型インダクタ L2も、第 1〜第 5誘電体シート 21a〜 21eに設けたビアホール導体 VH2を介して電気的に接続されて ヽる。ビアホール導 体は一般に厚膜導体よりも抵抗値が小さいので、ハイパスフィルタ 35の Q値をより一 層高くするができる。  [0030] Also, the first built-in capacitor C5 and the chip inductor L1 are electrically connected via via-hole conductors VH 1 provided in the first to fifth dielectric sheets 21a to 21e! . Similarly, the first built-in capacitor C6 and the chip inductor L2 are also electrically connected via via-hole conductors VH2 provided in the first to fifth dielectric sheets 21a to 21e. Since the via-hole conductor generally has a lower resistance value than the thick film conductor, the Q value of the high-pass filter 35 can be further increased.
[0031] この結果、低背でかつ通過帯域近傍の不要輻射、妨害波侵入が小さい高機能の L [0031] As a result, the high-performance L is low in profile and has low unwanted radiation near the passband and low interference wave penetration.
Cフィルタ複合モジュール 1が得られる。 C filter composite module 1 is obtained.
[0032] 図 7は、通過帯域が 2. 402〜2. 480GHz、通過帯域近傍の阻止帯域が 2. 11〜[0032] Figure 7 shows that the passband is 2.402 to 2.480 GHz, and the stopband near the passband is 2.11.
2. 17GHzになるように設計したハイパスフィルタ 35を備えた LCフィルタ複合モジュ ール 1の減衰特性を示すグラフである。ハイパスフィルタ 35の Q値が高いので、急峻 な阻止帯域が得られて 、ることがわ力る。 2. This graph shows the attenuation characteristics of the LC filter composite module 1 equipped with the high-pass filter 35 designed to be 17 GHz. Since the high-pass filter 35 has a high Q value, a steep stopband can be obtained, which makes it difficult to understand.
[0033] なお、本発明に係る LCフィルタ複合モジュールは前記実施例に限定するものでは なぐその要旨の範囲内で種々に変更することができる。 [0033] The LC filter composite module according to the present invention is not limited to the above-described embodiment. Various modifications can be made within the scope of the gist.
[0034] 特に、前記実施例では、誘電体シートを積み重ねて積層体を形成して!/ヽるが、誘 電体スラリー及び導電ペーストを順に重ね塗りする方法で積層体を形成するものであ つてもよい。また、積層体は、セラミックグリーンシートを積層してなるセラミック多層構 造のほか、榭脂層を積層してなる榭脂多層構造であってもよい。  [0034] In particular, in the above embodiment, dielectric sheets are stacked to form a laminated body !, but the laminated body is formed by a method in which dielectric slurry and conductive paste are sequentially overcoated. May be. Further, the laminate may be a ceramic multilayer structure in which ceramic green sheets are laminated, or a resin multilayer structure in which a resin layer is laminated.
産業上の利用可能性  Industrial applicability
[0035] 以上のように、本発明は、移動体通信装置等に使用される LCフィルタ複合モジュ ールに有用であり、特に、通過帯域近くの阻止帯域において高減衰が得られ、かつ 、十分な低背化が可能である点で優れている。 [0035] As described above, the present invention is useful for LC filter composite modules used in mobile communication devices and the like, and in particular, high attenuation is obtained in the stopband near the passband, and sufficient. It is excellent in that a low profile can be achieved.

Claims

請求の範囲 The scope of the claims
[1] 複数の誘電体層を積み重ねて構成した多層基板と、  [1] a multilayer substrate formed by stacking a plurality of dielectric layers;
前記多層基板の一方主面に搭載されたチップ型インダクタを含む表面実装部品と 前記多層基板の内部に設けられたコンデンサ電極によって構成された第 1内蔵型 コンデンサと前記多層基板の一方主面に設けられた前記チップ型インダクタとを含ん で構成され、かつ、平面視したとき前記第 1内蔵型コンデンサが前記チップ型インダ クタと少なくとも一部が重なる領域に配置されている LCフィルタと、  Provided on one main surface of the multilayer substrate and a first built-in capacitor composed of a surface mount component including a chip-type inductor mounted on one main surface of the multilayer substrate, and a capacitor electrode provided inside the multilayer substrate An LC filter configured to include the chip-type inductor, and the first built-in capacitor disposed in a region at least partially overlapping the chip-type inductor when viewed in plan,
前記多層基板の一方主面の近傍内部に配置され、かつ、平面視したとき前記チッ プ型インダクタの直下部分に切欠き部又は開口部を有した状態で前記誘電体層の 略全面に設けられたグランド電極と、  Arranged in the vicinity of one main surface of the multilayer substrate, and provided on substantially the entire surface of the dielectric layer with a notch or an opening in a portion immediately below the chip-type inductor when viewed in plan. Ground electrode,
を備えたことを特徴とする LCフィルタ複合モジュール。  LC filter composite module characterized by comprising
[2] 前記 LCフィルタは前記第 1内蔵型コンデンサ及び前記チップ型インダクタの直列 回路を含み、前記第 1内蔵型コンデンサは前記チップ型インダクタの直下に配置され ていることを特徴とする請求の範囲第 1項に記載の LCフィルタ複合モジュール。  [2] The LC filter includes a series circuit of the first built-in capacitor and the chip inductor, and the first built-in capacitor is arranged immediately below the chip inductor. LC filter composite module according to item 1.
[3] 前記 LCフィルタは前記多層基板の内部に設けられたコンデンサ電極によって構成 された第 2内蔵型コンデンサをさらに含み、該第 2内蔵型コンデンサは前記第 1内蔵 型コンデンサを間にして前記チップ型インダクタと対向する位置に配置されているこ とを特徴とする請求の範囲第 2項に記載の LCフィルタ複合モジュール。  [3] The LC filter further includes a second built-in capacitor configured by a capacitor electrode provided inside the multilayer substrate, and the second built-in capacitor is interposed between the first built-in capacitor and the chip. 3. The LC filter composite module according to claim 2, wherein the LC filter composite module is disposed at a position facing the type inductor.
[4] 前記 LCフィルタは、前記第 2内蔵型コンデンサに、前記第 1内蔵型コンデンサ及び 前記チップ型インダクタの直列回路が電気的にシャント接続されたノ、ィパスフィルタ であることを特徴とする請求の範囲第 3項に記載の LCフィルタ複合モジュール。 [4] The LC filter is a no-pass filter in which a series circuit of the first built-in capacitor and the chip inductor is electrically shunt-connected to the second built-in capacitor. The LC filter composite module according to claim 3.
[5] 前記第 1内蔵型コンデンサと前記チップ型インダクタは、前記誘電体層に設けたビ ァホール導体を介して電気的に接続されていることを特徴とする請求の範囲第 1項な[5] The first built-in capacitor and the chip inductor are electrically connected via a via-hole conductor provided in the dielectric layer.
Vヽし第 4項の!/、ずれかに記載の LCフィルタ複合モジュール。 The LC filter composite module described in V!
[6] 前記第 1内蔵型コンデンサと前記チップ型インダクタとを電気的に接続するための 前記ビアホール導体は、前記グランド電極の前記切欠き部又は前記開口部に設けら れていることを特徴とする請求の範囲第 5項に記載の LCフィルタ複合モジュール。 前記表面実装部品は半導体デバイスを含んでいることを特徴とする請求の範囲第 項な 、し第 6項の!/、ずれかに記載の LCフィルタ複合モジュール。 [6] The via hole conductor for electrically connecting the first built-in capacitor and the chip inductor is provided in the notch or the opening of the ground electrode. The LC filter composite module according to claim 5. 7. The LC filter composite module according to claim 6, wherein said surface mount component includes a semiconductor device.
PCT/JP2006/301729 2005-02-10 2006-02-02 Lc filter composite module WO2006085465A1 (en)

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