Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
  • H01L27/144—Devices controlled by radiation
  • H01L27/146—Imager structures
  • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
  • H01L27/14689—MOS based technologies
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
  • H01L27/144—Devices controlled by radiation
  • H01L27/146—Imager structures
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
  • H01L27/144—Devices controlled by radiation
  • H01L27/146—Imager structures
  • H01L27/148—Charge coupled imagers
  • H01L27/14806—Structural or functional details thereof

Definitions

• the present invention relates to a solid-state image pickup device using charged coupled devices (CCD), and more particularly to a method for fabricating a solid-state image pickup device using CCD capable of forming poly silicon electrodes by a Salicide process to decrease the thickness of the poly silicon electrodes and to reduce resistance of the poly silicon electrodes, thereby preventing problems generated in the subsequent processes and enhancing the electrical characteristics of the solid-state image pickup device.
• CCD charged coupled devices
• FIG. 1 is a top view illustrating a solid-state image pickup device using CCD with a general honeycomb structure.
• the solid-state image pickup device using CCD includes a photo-resist part 10 formed on one surface of a semiconductor substrate 1, an interface part 60 formed at the outside of the photo-resist part 10, an output transfer part 70 formed at the outside of the interface part 60 and an output unit 80 adjacently connected to one end of the output transfer part 70.
• the photo-resist part 10 formed on the semiconductor substrate 1 includes 8 photoelectric conversion element columns 20, 8 photoelectric conversion element rows 21, 4 vertical transfer CCD 30 and 32 readout gate regions 40.
• Each of the 8 photoelectric conversion element columns 20 includes 4 photoelectric conversion elements 22 in an n-type region within a p-type well. Also, each of the 8 photoelectric conversion element rows 21 includes 4 photoelectric conversion elements 22.
• Each of the vertical transfer CCD 30 includes a charge transfer channel (not shown) composed in an n-type region within a p-type well, which is formed on one surface of the semiconductor substrate 1, 5 first transfer electrodes 32 formed on an electrical insulation film of the surface of the semiconductor substrate 1, crossing the charge transfer channel, in a plan view, and 4 second transfer electrodes 33 formed on the electrical insulation film of the upper surface of the semiconductor substrate 1, crossing the charge transfer channel, in a plan view.
• the first and second transfer electrodes 32 and 33 are formed in first and second poly silicon layers, respectively. The first and second transfer electrodes 32 and 33 are alternatively formed along the charge transfer channel.
• Each of the readout gate regions 40 is indicated by slant lines, which are shaped as a zig-zag.
• the interface unit 60 includes 12 charge transfer stages connected to one end of the charge transfer channel composing the vertical transfer CCD 30.
• Each of the 12 charge transfer stages includes an interface unit charge transfer channel (not shown) led to the charge transfer channel, and one of 3 transfer electrodes 61, 62 and 63 formed on the semiconductor substrate 1, crossing the interface unit charge transfer channel in a plan view.
• FIG. 2 is a cross-sectional view of a pixel of the prior art solid-state image pickup device using CCD.
• a photodiode (PD) area for the prior art solid-state image pickup device using CCD 200 is formed such that a first p-type well 111, approximately 3mm thick, is formed on an n-type semiconductor substrate 110 using impurity implantation, etc., then an n-type impurity doped region (PDN) 113 is formed on the first p-type well 111, and finally a p-type impurity doped region (PDP) 114 is formed on the surface of the n-type impurity doped region 113.
• PDN n-type impurity doped region
• PDP p-type impurity doped region
• the p-type impurity doped region 114 is doped with a higher concentration of p- type impurities such that it becomes a p+-type doped region, which prevents electrons generated on the surface of the photodiode from inflowing in the photodiode region. Also, the n-type impurity doped region 113 formed under the p-type impurity doped region 114 is doped by implanting ions thereto to accumulate the electrons.
• the first p-type well 111 is formed under the n-type impurity doped region 113 to control Blooming and shutter control.
• the first p-type well 111 forms a potential barrier therein to collect electrons in the photodiode area. If there are exceeding electrons, the exceeding electrons are extracted to the n-type semiconductor substrate 110 based on dose units.
• the first p-type well 111 Since the greater the depth of the first p-type well 111 is the wider the photodiode area is in the depth direction, a relatively large amount of electrons are gathered, thereby increasing sensitivity. However, if the first p-type well 111 is exceedingly deep, since electrons are generated by infrared light as well as red visible light, it may have a negative effect upon color reproduction. Therefore, based on optimum energy and dose units, the first p-type well should be implanted by ions.
• a second p-type well 115 is formed on the first p-type well 111 on the surface of the n-type semiconductor substrate 110.
• the second p-type well layer 115 is spaced from the n-type impurity doped region 113 by a predetermined distance.
• the second p- type well 115 forms a buried CCD (BCCD) 118 around the surface thereof.
• BCCD buried CCD
• a transfer gate (TG) 119 and a channel stop region (CST) 117 are formed between the n-type impurity doped region 113 and the second p-type well 115.
• the TG transfer gate
• CST channel stop region
• a first protective film 121 is formed on the surface including the n-type impurity doped region 113 and the second p-type well 115.
• Poly silicon electrodes 141 and 143 are formed on the first protective film, which is the upper side of the second p-type well 115 using chemical vapor deposition (CVD).
• a second protective film 123 covers the upper side thereof. After that, a metal light shielding film 124 is formed on the second protective film 123 by etching, such that the n-type impurity doped region 113 is opened.
• a boron phosphorus silicate glass (BPSG) layer 125 is deposited thereon.
• a passivation film or planarizing film 126 are formed on the BPSG film 125 and then planarized by a planarizing process.
• a color filter 130 is formed on the planarized surface of the passivation film or planarizing film 126.
• the upper surface of the BPSG film should be planarized, which may damage the poly silicon electrodes.
• the lowest point (denoted by 'b') of a concave portion of the BPSG film may be lower than the highest point (denoted by 'a') of the poly silicon electrodes, as shown in Fig. 3a.
• a planarizing process is applied to the BPSG film with such a structure, the result may bring about removal of a portion of the upper portion of the poly silicon electrodes, as shown in Fig. 3b. Disclosure of Invention Technical Problem
• the present invention has been made in view of the above problems, and it is an object of the present invention to provide a method for fabricating a solid-state image pickup device using CCD capable of forming poly silicon electrodes by a Salicide process to decrease the thickness of the poly silicon electrodes and to reduce resistance of the poly silicon electrodes, thereby preventing problems generated in the subsequent processes and enhancing the electrical characteristics of the solid-state image pickup device.
• the above and other objects can be accomplished by the provision of a method for fabricating a solid-state image pickup device using charged-coupled devices (CCD) including an n-type impurity doped region and buried charged-coupled devices (BCCD) region formed on a surface of the semiconductor substrate.
• CCD charged-coupled devices
• BCCD buried charged-coupled devices
• the method comprises the steps of: forming a first protective film on the n-type impurity doped region and the BCCD region; forming a first poly silicon electrode on the first protective film of the upper part of the BCCD region by a Salicide process; forming an interlay er oxidation film on the first poly silicon electrode and forming a second poly silicon electrode on the interlayer oxidation film to overlap with a part of the first poly silicon electrode by the Salicide process; and forming a second protective film, a metal light shielding film, a BPSG film, a pssivation film or planarizing film after forming the second poly silicon electrode.
• the first and second protective films may be formed by stacking one of
• the metal light shielding film may be formed by stacking one of W,
• the forming of the first poly silicon electrode may include: forming a poly silicon layer on the first protective film; forming a metal film on the upper surface of the poly silicon layer; forming a metal Silcide fim by heating the upper surface of the poly silicon layer; and selectively etching the poly silicon layer.
• the metal film may be formed by one of Co, Ti, W, and the metal
• Suicide film may J be one of the CoSi 2 , TiTi 2 , WSi 2.
• the forming of the second poly silicon electrode may include: forming a poly silicon layer on the interlayer oxidation film; forming a metal film on the supper surface of the poly silicon layer; forming a metal Suicide film by heating the upper surface of the poly silicon layer; and selectively, etching the poly silicon layer.
• the metal film may be formed by one of Co, Ti, W, and the metal
• Suicide film may J be one of the CoSi 2 , TiTi 2 , WSi 2.
• the forming of the metal light shielding film may include: depositing W or WSi to a predetermined thickness using sputtering or CVD; and etching only the upper side of the n-type impurity doped region.
• the method further comprises: forming a color filter pattern on the
• the BPSG film on the metal light shielding film and the poly silicon electrodes.
• the BPSG film may be deposited thicker than summation of the metal light shielding film and the poly silicon electrode and planarized by chemical mechanical polishing (CMP).
• CMP chemical mechanical polishing
• the CMP is performed until cave forms of the BPSG film may be removed.
• CCD charged-coupled devices
• etching the metal light shielding film can be easily performed and thusly diffuse reflection of incident light can be reduced such that light collection can be normally preformed.
• first and second poly silicon electrodes are formed on the upper surface of the metal Suicide film, resistance thereof can be decreased and electrical characteristics thereof can be enhanced.
• Fig. 1 is a top view illustrating a solid-state image pickup device using CCD having a general honeycomb structure
• Fig. 2 is a cross-sectional view of a pixel of the prior art solid-state image pickup device using CCD
• Fig. 3 is a cross-sectional view describing problems generated in the processes for fabricating a prior art solid-state image pickup device using CCD
• Figs. 4a to 4c are cross-sectional views describing a method for manufacturing a solid-state image pickup device using CCD according to the present invention.
• FIG. 4a to 4c are cross-sectional views describing a method for manufacturing a solid-state image pickup device using CCD according to the present invention.
• the solid-state image pickup device 300 is formed such that a first p-type well layer 211, approximately 3D thick, is formed on an n-type semiconductor substrate 210 using impurity implantation, etc., then an n-type impurity doped region (PDN) 213 is formed on the first p-type well 211, and finally a p-type impurity doped region (PDP) 214 is formed on the surface of the n-type impurity doped region 213.
• PDN n-type impurity doped region
• PDP p-type impurity doped region
• the p-type impurity doped region 114 is doped with a higher concentration of p- type impurities such that it becomes a p+-type doped region, which prevents electrons generated on the surface of the photodiode from inflowing in the photodiode area.
• the n-type impurity doped region 213 formed under the p-type impurity doped region 214 is doped by implanting ions thereto to accumulate the electrons.
• a second p-type well layer 215 is formed on the first p-type well layer 211 on the surface of the n-type semiconductor substrate 210.
• the second p-type well layer 215 is spaced from the n-type impurity doped region 213 at a predetermined distance.
• the second p-type well 215 layer forms a buried CCD (BCCD) 218 around the surface thereof.
• BCCD 218 accumulates and transfers electrons according to voltages applied to the poly silicon electrodes 241 and 243.
• a transfer gate (TG) 219 and a channel stop region (CST) 217 are formed between the n-type impurity doped region 213 and the second p-type well layer 215.
• the TG 219 connects the n-type impurity doped region 213 with the second p-type well 215, and the CST 217 prevents electrons from jumping to adjacent cells.
• a first protective film 221 is formed on the surfaces of the n-type impurity doped region 213, the second p-type well layer 215, and the BCCD regions 218, prepared on the surface of the n-type impurity doped region 213 and the second p-type well layer 215.
• the first protective film 221 is formed by stacking one of SiO , SiON, SiN, or any combination thereof.
• the first and second poly silicon electrodes 241 and 243 are formed to be partially overlapped to each other on the first protective film 221 of the BCCD 218 by chemical vapor deposition (CVD) and etching.
• the first protective film 221 is between the first and second poly silicon electrodes 241 and 243.
• the first poly silicon electrode 243 is formed on the first protective film of the upper side of the BCCD region 218 by a Salicide process.
• a poly silicon layer 243a is formed on the first protective film 221 by
• a metal Suicide film 243b is formed on the poly silicon layer 243a.
• the poly silicon layer 243a is selectively etched to form a first poly silicon electrode 243 with a predetermined pattern.
• the thin metal film formed on the upper surface of the poly silicon layer 243a is preferably formed by one of Co, Ti, W.
• the metal Suicide film 243b formed by heating the metal film is preferably formed by one of CoSi , TiSi , WSi .
• a cobalt Suicide film 243b is formed on the poly silicon layer 243a. Also, if the poly silicon layer 243 a onto which Ti is applied is heated, TiSi film 243b is formed on the poly silicon layer 243a. In addition, if the poly silicon 243a onto which W is applied is heated, a WSi Suicide film 243b is formed on the poly silicon layer 243a.
• the first poly silicon electrode 243 forms an interlayer oxidation film 243c at a predetermined thickness thereon.
• the interlayer oxidation film 243c forms a second silicon electrode 241 overlapped with a part of the first poly silicon electrode 243 thereon.
• the second poly silicon electrode 241 is formed by Salicide process.
• the poly silicon layer 241a is formed on the interlayer oxidation film 243c by CVD, etc. and forms a thin metal film thereon.
• the upper surface of the poly silicon layer 241a is heated to a predetermined temperature and forms a metal Suicide film 241b thereon.
• the poly silicon layer 241a is selectively etched to form a second poly silicon electrode with a predetermined pattern.
• the thin metal film formed on the upper surface of the poly silicon layer 241a is preferably formed by Co, Ti, W.
• the metal Suicide film 241b formed by heating the metal film is preferably formed by one of CoSi , TiSi , WSi .
• a cobalt Suicide film 241b is formed on the poly silicon layer 241a. Also, if the poly silicon layer 241a onto which Ti is applied is heated, TiSi film 241b is formed on the poly silicon layer 241a. In addition, if the poly silicon layer 241a onto which W is applied is heated, WSi Suicide film 241b is formed on the poly silicon layer 241a.
• the first and second poly silicon electrodes 241 and 243 form the metal Suicide films 241b and 243b on the upper surface thereof, resistance thereof is decreased such that electrical characteristics are enhanced.
• the poly silicon layers 241a and 243a are heated with metals such as Co, etc. placed thereon, the metals such as Co, etc., sink into the poly silicon layers 241a and 243a. Therefore, the total thickness of the poly silicon layers 241a and 243a is decreased.
• a second protective film 224, a metal light shielding film 227, a BPSG film 225, a passivation or planarizing film are sequentially formed thereon.
• a color filter pattern 230 is formed on the final planarized surface.
• the second protective film 224 formed on the upper surface of the second poly silicon electrode 241 is formed by stacking one of SiO , SiON, SiN or any combination thereof.
• the metal light shielding film 227 is formed on the second protective film 224 such that the n-type impurity doped region can be opened.
• the metal light shielding film 227 is formed such that W or WSi , etc. is deposited at a predetermined thickness by CVD, and the deposited result of the upper side of the n-type impurity doped region is opened by etching.
• the metal light shielding film 227 is formed by one of W, Mo, Ti or by stacking more than at least two of W, Mo, Ti. Also, the metal light shielding film 227 may be formed by stacking one of WSi, MoSi, TiSi, or any combination thereof.
• the metal light shielding film 227 opening the n-type impurity doped region 213 forms a BPSG film 225 thereon.
• the BPSG film 225 is deposited on the upper surface of the n-type doped region 213 as well as the metal light shielding film 227. More specifically, the BPSG film 225 is formed such that it is convex at a portion in which the first and second poly silicon electrodes 241 and 243 are formed and concave at a portion in which the n-type impurity doped region 213 is formed.
• a pssivation film or planarizing fi.m 226 is formed on the BPSG film 225 and forms a color filter pattern thereon.
• the color filter pattern 230 is directly formed on the planarized surface of the BPSG film 225.
• the BPSG film 225 must be stacked such that it is thicker than the summation from the first protective film 221 to the metal light shielding film 227, because upper portions of the BPSG film 225 may be removed therefrom to planarize by a planaring technique. However, if the thickness of the BPSG 225 is smaller than summation from the first protective film 221 to the metal light shielding film 227, the metal light shielding film 227 may be removed therefrom. Therefore, the BPSG film 225 should be stacked over a predetermined thickness.
• the BPSG film 225 is formed by approximately 1200A-2000A thick.
• the ploy silicon electrodes 241 and 243 are formed 800A-1000A thick, and the second protective film 223 is formed 400A-800A thick.
• the upper surface of the BPSG film 225 is planarized by CMP. After that, a color filter pattern 230 is formed on the planarized BPSG film 225.

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Citations (4)

• 2005
  • 2005-01-25 KR KR1020050006859A patent/KR100697702B1/ko not_active IP Right Cessation
  • 2005-01-28 WO PCT/KR2005/000253 patent/WO2006080595A1/en active Application Filing
  • 2005-09-08 TW TW094130932A patent/TW200627659A/zh unknown

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