WO2006069273A2 - Memory system with in stream data encryption/decryption and error correction - Google Patents
Memory system with in stream data encryption/decryption and error correction Download PDFInfo
- Publication number
- WO2006069273A2 WO2006069273A2 PCT/US2005/046688 US2005046688W WO2006069273A2 WO 2006069273 A2 WO2006069273 A2 WO 2006069273A2 US 2005046688 W US2005046688 W US 2005046688W WO 2006069273 A2 WO2006069273 A2 WO 2006069273A2
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- WO
- WIPO (PCT)
- Prior art keywords
- data
- circuit
- cells
- error
- data stream
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1408—Protection against unauthorised use of memory or access to memory by using cryptography
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
Definitions
- This invention relates in general to memory systems, and in particular to a memory system with in stream data encryption/decryption and error correction.
- the mobile device market is developing in the direction of including content storage so as to increase the average revenue by generating more data exchanges. This means that the content has to be protected when stored on a mobile device.
- Portable storage devices are in commercial use for many years. They carry data from one computing device to another or to store back-up data. More sophisticated portable storage devices, such as portable hard disc drives, portable flash memory disks and flash memory cards, include a microprocessor for controlling the storage management.
- the data stored is typically encrypted and only authorized users are allowed to decrypt the data.
- the data stored in the memory cells may contain errors for a number of reasons. It is therefore common to perform error correction when data from the memory cells are read. Error correction may also detect the positions of the errors in the data stream.
- the cryptographic processes performed by a circuit may shift the positions of the bits in the data stream so that if the bit errors in the data stream have not been corrected when such processes are performed, information on the positions of the bit errors will no longer be accurate after the processes so that error correction may no longer be possible after the cryptographic processes have been performed.
- one aspect of the invention is based on the recognition that the bit errors in the data in the data stream passing between the cells and the cryptographic circuit are preferably corrected prior to any cryptographic process performed by the circuit.
- at least one buffer is used to store data in the data stream passing between the cells and the circuit and any error or errors in the data stored in the buffer and originating from the cells are corrected prior to cryptographic processing of the data by the circuit.
- FIG. 1 is a block diagram of a memory system in communication with a host device to illustrate the invention.
- Fig. 2 is a block diagram of some of the blocks of the memory system in Fig. 1.
- Fig. 3 is a circuit diagram illustrating in more detail a preferred configuration of the error correction buffer unit of Fig. 2.
- Fig. 4 is a flow chart illustrating the operation of the system in Fig. 2 to illustrate the preferred embodiment of one aspect of the invention.
- the memory system 10 includes a central processing unit (CPU) 12, a buffer management unit (BMU) 14, a host interface module (HIM) 16 and a flash interface module (FIM) 18, a flash memory 20 and a peripheral access module (PAM) 22.
- Memory system 10 communicates with a host device 24 through a host interface bus 26 and port 26a.
- the flash memory 20 which may be of the NAND type, provides data storage for the host device 24.
- the software code for CPU 12 may also be stored in flash memory 20.
- FIM 18 connects to the flash memory 20 through a flash interface bus 28 and port 28a.
- HIM 16 is suitable for connection to a host system like a digital camera, personal computer, personal digital assistant (PDA), digital media player, MP -3 player, and cellular telephone or other digital devices.
- the peripheral access module 22 selects the appropriate controller module such as FIM, HIM and BMU for communication with the CPU 12.
- controller module such as FIM, HIM and BMU for communication with the CPU 12.
- all of the components of system 10 within the dotted line box may be enclosed in a single unit such as in memory card or stick 10' and preferably encapsulated in the card or stick.
- the buffer management unit 14 includes a host direct memory access (HDMA) 32, a flash direct memory access (FDMA) controller 34, an arbiter 36, a buffer random access memory (BRAM) 38 and a crypto-engine 40.
- the arbiter 36 is a shared bus arbiter so that only one master or initiator (which can be HDMA 32, FDMA 34 or CPU 12) can be active at any time and the slave or target is BRAM 38.
- the arbiter is responsible for channeling the appropriate initiator request to the BRAM 38.
- the HDMA 32 and FDMA 34 are responsible for data transported between the HIM 16, FIM 18 and BRAM 38 or the CPU random access memory (CPU RAM) 12a.
- the operation of the HDMA 32 and of the FDMA 34 is conventional and need not be described in detail herein.
- the BRAM 38 is used to buffer data passed between the host device 24, flash memory 20 and the CPU RAM 12a.
- the HDMA 32 and FDMA 34 are responsible for transferring the data between HIM 16/FIM 18 and BRAM 38 or the CPU RAM 12a and for indicating sector transfer completion.
- the FIM 18 also has the capability of detecting errors in the data read from the flash memory 20 and notifying the CPU 12 when errors are discovered.
- the data from memory 20 may be decrypted and encrypted again by crypto engine 40 before it is sent to BRAM 38.
- the encrypted data in BRAM 38 is then sent to host device 24 as before. This illustrates the data stream during a reading process.
- the memory system 10 in Fig. 1 contains a flash memory
- the system may alternatively contain another type of non-volatile memory instead, such as magnetic disks, optical CDs, as well as all other types of rewrite-able non volatile memory systems, and the various advantages described above will equally apply to such alternative embodiment.
- the memory is also preferably encapsulated within the same physical body (such as a memory card or stick) along with the remaining components of the memory system.
- FIM 18 may contain an error correction (ECC) circuit 102 that detects which bit or bits of the data stream from memory 20 contain errors, including the locations of the errors in the bit stream.
- ECC error correction
- Fig. 2 is a block diagram of a memory system 100 to illustrate another aspect of the invention.
- FIM 18 sends an interrupt signal to CPU 12 when error(s) is detected in the bit stream, and circuit 102 sends information concerning the locations of the bits in error to CPU 12.
- the errors are corrected by the CPU in BRAM 38.
- the cryptographic process(es) may cause the locations and/or value(s) of the data bits in the processed data stream to change, so that the location(s) and/or value(s) of the bit errors after the cryptographic processing may be different from those sent to the CPU 12 by circuit 102. This may render it impossible to correct the errors when the cryptographically processed data reach the BRAM 38.
- An aspect of the invention stems from the recognition that the error(s) detected is corrected before the data is cryptographically processed, so that this problem is avoided.
- An error buffer unit (EBU) 104 is used to store data from the data stream passing between the BMU 14 and FIM 18, so that when the CPU 12 receives an interrupt from FIM 18 indicating the presence of error(s) in the data stream, the CPU corrects the error(s) in EBU 104, instead of at the BRAM 38.
- the bits in error are simply "flipped" (i.e. turning “1" to "0” and “0” to "1") at the locations of error(s) detected by circuit 102.
- two or more buffers may be employed in the EBU 104, such as shown in Fig. 3.
- two buffers 104a and 104b are used, where one of the two buffers is receiving data from the memory 20 through FIM 18 and the other is sending data to the Crypto-Engine 40 through FDMA 34 in BMU 14.
- two switches 106a and 106b are used. When the two switches are in the solid line positions as shown in Fig. 3, buffer 104a is supplying data to the BMU 14 and buffer 104b is receiving data from FIM 18.
- the two switches are in the dotted line positions as shown in Fig.
- buffer 104b is supplying data to the BMU 14 and buffer 104a is receiving data from FIM 18.
- Each of the buffers can first be filled with data before data stored in it is sent to the BMU.
- the CPU corrects the error(s) in the buffer(s) 104a and 104b when data is sent from or received by them. In this manner, the only latency is the time required to fill one of the two buffers when the data stream is started. After that, there will be no interruption in the data stream even when error(s) have been detected by circuit 102, if the time taken by the CPU to correct the error(s) is small compared to the time needed to fill each buffer.
- a buffer-empty signal (not shown) connecting between the EBU 104 and the FDMA 34 signals the latter that the data stream is interrupted and no more data is available.
- the FDMA 34 as well as the crypto engine 40 will then pause and wait for the data stream to resume.
- switch 108 When data is written by the host device 24 to memory 20, there may be no need for error correction, so that it would be desirable to bypass the EBU. This may be accomplished by switch 108.
- switch 108 When switch 108 is closed, the data from HIM 16 (not completely shown in Fig. 2) simply bypasses the two buffers 104a and 104b.
- Switch 108 may also be closed in a bypass mode where no cryptographic processing is needed when data is read from or written to memory 20. In this mode, HDMA and FDMA are connected directly to arbiter 36 as if crypto-engine 40 is eliminated from system 10, and the data stream bypasses both the EBU 104 and the Crypto-Engine 40. This may be accomplished also by using switches.
- a logic circuit (not shown) in system 100 under the control of CPU 12 causes the data stream to bypass block 40 and causes switch 108 to close.
- the error correction process is illustrated by the flow chart of Fig. 4.
- the CPU 12 starts a read operation after receiving a read command from the host device 24 (ellipse 150). It then configures the Crypto-Engine 40 using appropriate security configuration information, and configures the BMU 14 for a reading operation, and other parameters such as the allocation of memory space in BRAM 38 for the operation (blocks 152, 154). It also configures the FIM 18, such as by specifying the locations in memory 20 where data is to be read (block 156).
- the HDMA and FDMA engines 32 and 34 are then started. See Block 158. When the CPU receives an interrupt, it checks to see whether it is a FIM interrupt (diamond 160).
- the CPU checks to see whether the interrupt is one indicating that there is one or more errors in the data stream (162). If error(s) is indicated, it proceeds to correct the error(s) (block 164) in buffers 104a and/or 104b and returns to configure the FIM 18 to change the locations in memory 20 where data is to be read next (block 156).
- the FIM interrupt does not indicate error(s) in the data stream, it means the FIM has completed its operation and the CPU also returns to block 156 to re-configure and restart the FIM.
- the interrupt detected by the CPU is not a FIM interrupt, it checks to see if it is an end of data interrupt (diamond 166). If it is, then the read operation ends (ellipse 168). If not, this interrupt is irrelevant to the cryptographic processing of the data (i.e. clock interrupt) and the CPU 12 services it (not shown) and returns to diamond 160 to check for interrupts.
- Fig. 4 needs only to be modified slightly for a write operation. Since there is no handling of ECC errors in the data to be written to memory 20, the CPU 12 can skip the processes in diamond 162 and block 164 in a write operation. If a FIM interrupt is received by the CPU 12 during a write operation, this means that the FIM completed its operation and the CPU also returns to block 156 to re-configure the FIM. Aside from this difference, the write operation is substantially similar to the read operation.
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Storage Device Security (AREA)
- Detection And Correction Of Errors (AREA)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2005800484386A CN101124545B (zh) | 2004-12-21 | 2005-12-21 | 带有流中数据加密/解密和纠错的存储器系统 |
KR1020077016699A KR101254136B1 (ko) | 2004-12-21 | 2005-12-21 | 스트림 내 데이터 암호화/복호화 및 오류 정정 기능을 가진 메모리 시스템 |
EP05855273A EP1828898A2 (en) | 2004-12-21 | 2005-12-21 | Memory system with in stream data encryption/decryption and error correction |
JP2007548490A JP2008524754A (ja) | 2004-12-21 | 2005-12-21 | イン−ストリームデータの暗号化/復号およびエラー訂正の機能を有するメモリシステム |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US63848504P | 2004-12-21 | 2004-12-21 | |
US60/638,485 | 2004-12-21 | ||
US11/313,428 US8396208B2 (en) | 2004-12-21 | 2005-12-20 | Memory system with in stream data encryption/decryption and error correction |
US11/313,428 | 2005-12-20 | ||
US11/313,447 US20060239450A1 (en) | 2004-12-21 | 2005-12-20 | In stream data encryption / decryption and error correction method |
US11/313,447 | 2005-12-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2006069273A2 true WO2006069273A2 (en) | 2006-06-29 |
WO2006069273A3 WO2006069273A3 (en) | 2006-11-16 |
Family
ID=36602336
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2005/046688 WO2006069273A2 (en) | 2004-12-21 | 2005-12-21 | Memory system with in stream data encryption/decryption and error correction |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP1828898A2 (enrdf_load_stackoverflow) |
JP (1) | JP2008524754A (enrdf_load_stackoverflow) |
KR (1) | KR101254136B1 (enrdf_load_stackoverflow) |
CN (1) | CN101124545B (enrdf_load_stackoverflow) |
TW (1) | TWI391945B (enrdf_load_stackoverflow) |
WO (1) | WO2006069273A2 (enrdf_load_stackoverflow) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8108691B2 (en) | 2005-02-07 | 2012-01-31 | Sandisk Technologies Inc. | Methods used in a secure memory card with life cycle phases |
US8220039B2 (en) | 2005-07-08 | 2012-07-10 | Sandisk Technologies Inc. | Mass storage device with automated credentials loading |
US8321686B2 (en) | 2005-02-07 | 2012-11-27 | Sandisk Technologies Inc. | Secure memory card with life cycle phases |
US8423788B2 (en) | 2005-02-07 | 2013-04-16 | Sandisk Technologies Inc. | Secure memory card with life cycle phases |
US8713328B2 (en) | 2006-09-29 | 2014-04-29 | Fujitsu Limited | Code conversion apparatus, code conversion method, and computer product |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10133883B2 (en) * | 2009-02-09 | 2018-11-20 | International Business Machines Corporation | Rapid safeguarding of NVS data during power loss event |
WO2011064883A1 (ja) | 2009-11-27 | 2011-06-03 | 株式会社東芝 | メモリチップ |
JP5017439B2 (ja) * | 2010-09-22 | 2012-09-05 | 株式会社東芝 | 暗号演算装置及びメモリシステム |
KR102392844B1 (ko) * | 2017-03-10 | 2022-05-03 | 삼성전자주식회사 | 메모리 컨트롤러 및 그것을 포함하는 저장 장치 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5438575A (en) * | 1992-11-16 | 1995-08-01 | Ampex Corporation | Data storage system with stale data detector and method of operation |
JPH113284A (ja) * | 1997-06-10 | 1999-01-06 | Mitsubishi Electric Corp | 情報記憶媒体およびそのセキュリティ方法 |
TWI223204B (en) * | 2001-11-08 | 2004-11-01 | Toshiba Corp | Memory card, content transmission system, and content transmission method |
CN1229940C (zh) * | 2002-04-30 | 2005-11-30 | 电子科技大学 | 视频/数据广播的同频道多流透明传输方法 |
JP4118639B2 (ja) * | 2002-09-17 | 2008-07-16 | 株式会社リコー | ファイル管理装置 |
-
2005
- 2005-12-21 JP JP2007548490A patent/JP2008524754A/ja active Pending
- 2005-12-21 EP EP05855273A patent/EP1828898A2/en not_active Withdrawn
- 2005-12-21 KR KR1020077016699A patent/KR101254136B1/ko active Active
- 2005-12-21 WO PCT/US2005/046688 patent/WO2006069273A2/en active Application Filing
- 2005-12-21 TW TW094145661A patent/TWI391945B/zh not_active IP Right Cessation
- 2005-12-21 CN CN2005800484386A patent/CN101124545B/zh not_active Expired - Fee Related
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8108691B2 (en) | 2005-02-07 | 2012-01-31 | Sandisk Technologies Inc. | Methods used in a secure memory card with life cycle phases |
US8321686B2 (en) | 2005-02-07 | 2012-11-27 | Sandisk Technologies Inc. | Secure memory card with life cycle phases |
US8423788B2 (en) | 2005-02-07 | 2013-04-16 | Sandisk Technologies Inc. | Secure memory card with life cycle phases |
US8220039B2 (en) | 2005-07-08 | 2012-07-10 | Sandisk Technologies Inc. | Mass storage device with automated credentials loading |
US8713328B2 (en) | 2006-09-29 | 2014-04-29 | Fujitsu Limited | Code conversion apparatus, code conversion method, and computer product |
Also Published As
Publication number | Publication date |
---|---|
TWI391945B (zh) | 2013-04-01 |
KR20070087676A (ko) | 2007-08-28 |
WO2006069273A3 (en) | 2006-11-16 |
CN101124545A (zh) | 2008-02-13 |
TW200641911A (en) | 2006-12-01 |
CN101124545B (zh) | 2012-05-16 |
EP1828898A2 (en) | 2007-09-05 |
JP2008524754A (ja) | 2008-07-10 |
KR101254136B1 (ko) | 2013-04-12 |
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