WO2006062000A1

WO2006062000A1 - Digital filter

Info

Publication number: WO2006062000A1
Application number: PCT/JP2005/021711
Authority: WO
Inventors: Hisashi Suganuma
Original assignee: Pioneer Corporation
Priority date: 2004-12-06
Filing date: 2005-11-25
Publication date: 2006-06-15

Abstract

A digital filter realizes frequency characteristic equivalent to that obtained when n basic digital filters are connected in cascade by using a small-size and low-cost circuit. The digital filter includes adders, multipliers, and delay devices as components of the basic digital filters and the delay devices are connected in n stages in cascade. The digital filter further includes: a digital filter circuit operating with the sample value input clock frequency multiplied by n; a feedback memory for storing output data of the digital filter circuit; an output memory for outputting the output data of the feedback memory outside; and selector means for selecting a sample value input or the feedback memory output data as an input of the digital filter circuit.

Description

Specification

Digital filter

Technical field

TECHNICAL FIELD [0001] The present invention relates to a digital filter, and more specifically, a frequency characteristic similar to that of a filter circuit configured by cascade-connecting basic digital filters in multiple stages is realized with a reduced circuit scale and a low-cost configuration. The present invention relates to a digital filter that can be used. Background art

Conventionally, as this type of digital filter, for example, the techniques of Patent Document 1 and Patent Document 2 are known. In order to obtain a desired frequency characteristic, a digital filter may be configured by connecting basic primary and secondary digital filters (basic digital filters) in multiple stages. FIG. 6 is a diagram showing an example of a digital filter configured by cascade-connecting two low-pass filters 100 and 200 having the same basic configuration.

[0003] The low-pass filters 100 and 200 have multiplication coefficients that determine the filter characteristics of A1 and A2, respectively, and are configured to include one delay device for delaying data in the feedback path. The low-pass filters 100 and 200 operate according to a clock ckl generated by a clock generation circuit (not shown) and change at the rising edge of the clock ckl.

As shown in FIG. 6, the low-pass filter 100 includes an adder 101 that adds the input data (sample value) and the output data of the multiplier 13, and a clock for the output data of the adder 101. Delay device 102 that delays one cycle of ckl, multiplier 103 that multiplies the output data of delay device 102 by a multiplication coefficient A1, and output data of adder 101 and output data of delay device 102 And an adder 104 for performing addition.

In addition, as shown in FIG. 6, the low-pass filter 200 includes an adder 201 that performs addition on the output data of the adder 104 of the low-pass filter 100 and the output data of the multiplier 203, and the adder A delay unit 202 that delays the output data of 201 by one cycle of the clock ckl, a multiplier 203 that multiplies the output data of the delay unit 202 by a multiplication coefficient A2, and the output data of the adder 201 and And an adder 204 that adds to the output data of the delay unit 202. FIG. 7 is a diagram illustrating an example of a timing chart of the digital filter in FIG. In the figure, in the low-pass filter 100, when the time of the clock ckl reaches “t0”, the output of the force adder 101 whose input data changes to “DaO” is slightly delayed from the time “t0”. Therefore, the delay unit 102 stores and outputs the output data “Za-1” of the adder 101 immediately before “t0” at the rising edge of “t0”. The multiplier 103 multiplies the output data “Za-l” of the delay unit 102 by the multiplication coefficient A1 and outputs “Za_l * Al”. The adder 101 calculates the input data “DaO” and the output data “Za−1 * Al” of the multiplier 103 and outputs “DaO + Za−1 * Al”. The adder 104 calculates the output data “DaO + Za— 1 * A1” of the adder 101 and the output data “Za— 1” of the delay device 102 and outputs “DaO + Za_l * Al + Za— 1”. Is output.

[0007] The output data force of the adder 104 is the output of the digital filter 100 and becomes the input data of the digital filter 200. The digital filter 200 operates in the same manner as the digital filter 100. When the output data “DaO + Za-1 * A1 + Za—l” = DbO of the adder 104 is set, the output of the digital filter 200 (adder 204) The data is “DbO + Zb−1 * A2 + Zb−1”.

Patent Document 1: Japanese Patent Laid-Open No. 2001-308684, FIG.

Patent Document 2: JP 2000-315937 A, FIG.

Disclosure of the invention

Problems to be solved by the invention

However, in order to obtain a desired frequency characteristic, the configuration in which the digital filters are connected in multiple stages as shown in FIG. 6 increases the number of elements constituting the filter circuit. There is a problem that the scale increases and the configuration becomes expensive.

The present invention has been made in view of the above, and has a frequency characteristic similar to that of a digital filter circuit configured by cascade-connecting a basic digital filter in multiple stages, with a reduced circuit scale and low cost. An object is to provide a digital filter that can be realized with a configuration.

Means for solving the problem

[0011] In order to solve the above-described problems and achieve the object, the present invention provides a digital signal of the basic type that realizes the same frequency characteristic as when n digital filters of the basic type are cascade-connected. A digital filter circuit including an adder, a multiplier, and a delay unit that are components of the Tal filter, the delay unit being n-stage cascaded and operating at a clock frequency n times the clock frequency of the sample value input; A feedback memory that stores output data that has passed through the digital filter circuit a plurality of times, an output memory element that outputs output data of the feedback memory element to the outside, and an input of the digital filter circuit, And a first selector for selecting sample value input or output data of the feedback memory.

Brief Description of Drawings

FIG. 1 is a diagram showing a configuration of a digital filter according to an embodiment of the present invention.

FIG. 2 is a diagram showing a specific configuration example of the digital filter of FIG.

FIG. 3 is a diagram showing a configuration example of a digital filter that realizes the same frequency characteristics as when two (n = 2) basic digital filters are connected in series.

FIG. 4 is a diagram illustrating an example of a timing chart of the digital filter of FIG.

FIG. 5 is a diagram showing a configuration example of a digital filter that realizes the same frequency characteristics as when a low-pass filter and a high-pass filter are cascade-connected.

FIG. 6 is a diagram illustrating an example of a digital filter configured by cascade-connecting basic digital filters.

FIG. 7 is a diagram illustrating an example of a timing chart of the digital filter of FIG. Explanation of symbols

[0013] 1 Digital filter

10 Selector means

11 Selector

12 Switching signal generation circuit

20 Digital filter

21 Adder

22Z delay

23 multiplication

24 selector 25 counter

26 Adder

27 Inverter

28 selector

30 Return memory

40 Output memory

BEST MODE FOR CARRYING OUT THE INVENTION

The best mode of a digital filter according to the present invention will be described below with reference to the drawings. It should be noted that the present invention is not limited by this embodiment, and all the combinations of features described in the embodiment are not necessarily required for the solution means of the invention. In addition, constituent elements in the following embodiments include those that can be easily assumed by those skilled in the art or that are substantially the same.

[0015] (Embodiment)

FIG. 1 is a diagram illustrating a configuration example of the digital filter 1 according to the embodiment of the present invention. In FIG. 1, ckl and ckn are clocks for operating the digital filter 1, and ckn has a frequency (speed) n times that of ck 1.

As shown in FIG. 1, the digital filter 1 includes a selector means (first selector) 10 that switches between input data (sample value) and output data of the feedback memory 30, and output data of the selector means 10. A one-dimensional digital filter circuit 20 and a digital filter circuit 20 for realizing the same frequency characteristics as when a basic digital filter is connected in n (n≥2) stages in cascade. A return memory 30 for storing the output data that has passed through the memory multiple times, and an output memory 40 for outputting the output data of the feedback memory element 30 to the outside.

FIG. 2 is a diagram illustrating a specific configuration example of the digital filter 1 of FIG. The selector means 10 includes a selector 11 and a switching signal generation circuit 12. The switching signal generator circuit 12 receives ckl and ckn, and outputs a switching signal ta that becomes “H” in the period of lZc kn and “L” in the other period from the moment ckl rises in one cycle of ckl. Output to selector 11. The selector 11 receives the input data when the switching signal ta is “H”, and the feedback memory 30 when the switching signal ta is “L”. Select output data. That is, the selector 11 selects input data during lZckn and output data from the feedback memory 30 during (1 / ckn) * (n−1). When n = 2, as will be described later (see FIG. 3), the switching signal generation circuit 12 is not required, and the selector 11 receives the input data when ckl is “H” and “L”. In this case, the output data of feedback memory 30 should be selected.

The digital filter circuit 20 includes an adder (first adder) 21 that adds the output data of the selector 11 and the output data of the multiplier 23, and a clock for the output data of the adder 21. n delay units 22Z1, ···, 22Zn, which are each delayed by one cycle of ckn, and the multiplication coefficient “A1” input from selector 24 to the output data of delay unit 22Zn ··································· Multiplier coefficient “A1”, “An” depending on the selection signal “1” input from counter 25 and “n”. ”Is output to the multiplier 24. Based on the selector (second selector) 24 and the clocks ckl and ckn, the rising edge of the clock ckn is counted and the selection signal“ 1 ”, ··· “n” is output to selector 24 The output data of counter 25 and adder 21 and And an adder (second adder) 26 for adding and outputting output data of the delay device 22Zn, Ru.

[0019] When n = 2, as will be described later (see FIG. 3), the counter circuit 25 is not necessary, and the selector 24 is configured such that “A1”, “L” when ckl is “H”. In this case, “A2” may be output.

The feedback memory 30 composed of a delay device stores the output data of the adder 26 at the rising edge of the clock ckn and delays it by one cycle of the clock ckn. The output memory 40 composed of a delay device stores the output data of the feedback memory 30 at the rising edge of the clock ckl, and delays it by one cycle of the clock ckl and outputs it to the outside.

[Example 1]

FIG. 3 is a diagram illustrating a configuration example of the digital filter 1 that realizes the same frequency characteristic as that in the case where the basic digital filter is connected in two stages (n = 2). In particular, the digital filter 1 shown in FIG. 3 realizes the frequency characteristics of the low-pass filters 100 and 200 of FIG. 6 shown in the above prior art with a small number of parts. In FIG. 3, parts having the same functions as those in FIG. 2 are given the same reference numerals. [0022] In the figure, ck2 has twice the frequency (speed) of ckl. The selector 11 selects the input data when the clock ckl is “H”, and the output data of the feedback memory 30 when the clock ckl is “L”. The selector 11 outputs two pieces of output data fed back from the feedback memory 30 while the clock ckl is “L”.

[0023] The digital filter circuit 20 includes an adder 21 that adds the output data of the selector 11 and the output data of the multiplier 23, and a delay of one cycle of the clock ck2 with respect to the output data of the adder 21. The delay coefficient 22Z1 for delaying, the delay 22Z2 for delaying the output data of the delay 22Z1 for one cycle of the clock ck2, and the multiplication coefficient input from the selector 24 for the output data of the delay 22Z2 Multiplier 23 that multiplies “A1” and “A2” and multiplication coefficient “A1” when clock c kl is “H”, and multiplication coefficient “A2” when clock kl is “L”. A selector 24 for outputting, and an adder 26 for adding and outputting the output data of the adder 21 and the output data of the delay unit 22Z2 are provided.

[0024] The feedback memory 30 composed of a delay device stores the output data of the adder 26 at the rising edge of the clock ck2, and delays it by one cycle of the clock ck2. The output memory 40 composed of a delay device stores the output data of the feedback memory 30 at the rising edge of the clock ckl, delays it by one cycle of the clock ckl, and outputs it to the outside.

FIG. 4 is a diagram illustrating an example of a timing chart of the digital filter 1 in FIG. In the figure, the selector 10 includes input data “Da-1” between times “t—lb” and “tO”, input data “DaO” between times “tO” and “tl”, and time “tl”. ”To“ t2 ”, input data“ Dal ”is input.

The selector 11 selects input data when ckl is [H], and outputs data “DaO” between “tO” and “tOb”. The selector 11 selects the output data of the feedback memory 30 when “L”. However, since the delay unit 30 stores data at the rising edge of the clock ck2, data change occurs at time “t Oc”. As a result, when the output data of the feedback memory 30 between time “tOb” and “tOc” is “DbO” and the output data between “tOc” and “tl” is “DcO”, the output data of the selector 11 Is “DbO” between times “tOb” and “tOc”, and “DcO” between times “tOc” and “tl”.

The delay unit 22Z1 stores the output data of the adder 21 at the rising edge of the clock ck2. Here, the data up to “tOc” stored at time “tOa” is “ZaO”, and the data up to “t la” stored at “tOc” is “ZbO”. Since the delay unit 22Z2 is slightly delayed from the rising edge of the clock ck2, the delay unit 22Z2 stores data one cycle before the clock ck2 of the delay unit 22Z1. As a result, the output data of the delay device 22Z2 is “21) -1” between “1; 0 &” to “1; 0 ₍ :)” and “ZaO” between “t Oc” and “tal”.

The selector 24 selects the multiplication coefficient “A1” when the clock ckl is “H”, and the multiplication coefficient “A2” when the clock ckl is “L”. The output data of the selector 24 is “eight 1” between “0” and “1; 01)” and “eight 2” between “tOb” and “1”. The multiplier 23 multiplies the output data of the selector 24 and the output data of the delay unit 22Z2, and the output data is “Za—1 * A1”, “tOa” to “t ObJ” between “tO” and “tOa”. The interval is “Zb—1 * A2”, and the interval between “tOc” and “tl” is “ZaO * A2”.

[0029] The adder 26 adds the output data of the adder 21 and the output data of the delay unit 22Z2, and the output data is “DaO + Za— 1 * A1 + between“ tO ”and“ tOa ”. Za—1, “t0a” to “t0b” is “DaO + Zb— 1 * Al + Zb— 1”, and “tOb” to “tOc” is “DbO + Zb— 1 * A2 + Zb — 1” , “DcO + ZaO * A2 + ZaOj” between “tOc” and “t 1”.

[0030] The feedback memory 30 stores the output data of the adder 26 at the rising edge of the clock ck2. The output data of the adder 26 is slightly delayed from the rising edge of the clock ck2, so the output immediately before the rising edge at time “t 0a” Data "DaO + Za-1 * A1 + Za-1" is stored, and "01) 0 + 21) -1 * A2 + Zb-1" is stored at time "0". These data are the output data “DbO” between “t0b” and “t0c” of the selector 10 and the output data “0 0” between “tOc” and “tl”, respectively.

[0031] The output memory 40 stores the output data of the feedback memory 30 at the rising edge of the clock ckl. In the output memory 40, the output data between “tl” and “t2” is “DbO + Zb−1 * A2 + Zb−1”. This output data is the same as the data between “tO” and “tl” of the digital filter 100 in FIG. 6, and the time is delayed by one cycle of the clock ckl.

[0032] (Example 2)

In the first embodiment, a case where two stages of low-pass filters are cascade-connected has been described. In the second embodiment, the same frequency characteristics as when a low-pass filter and a high-pass filter are cascade-connected (bandpass filter) are realized. A digital filter will be described. FIG. 5 is a diagram illustrating a configuration example of the digital filter 1 that realizes the same frequency characteristics as when the low-pass filter and the high-pass filter are cascade-connected. In FIG. 5, parts having the same functions as those in FIG. 3 are given the same reference numerals.

[0034] Digital filter 1 shown in FIG. 5 differs from FIG. 3 in that an inverter 27 that inverts the output data of delay device 22Z2 and a clock ckl are “H” between delay device 22Z2 and adder 26. In this case, a selector (third selector) 28 is provided which selects the output data of the delay unit 22Z2 in the case of “1”, selects the output data of the inverter 27 in the case of “L”, and outputs the selected data to the adder 26. In this way, the functions of the single pass filter and the high pass filter, that is, the function of the bandpass filter can be realized with a simple configuration.

[0035] As described above, according to the present embodiment, as shown in Fig. 1 above, a basic digital signal that realizes the same frequency characteristics as when n basic digital filters are cascade-connected is used. A digital filter circuit including an adder, a multiplier, and a delay unit that are components of the filter. The delay unit is connected in n stages, and operates at a clock frequency n times the clock frequency of the sample value input. A feedback memory 30 for storing the output data of the digital filter circuit 20, an output memory 40 for outputting the output data of the feedback memory 30 to the outside, and a sample value input or input as an input to the digital filter circuit 20. Since the digital filter is composed of the selector means 10 for selecting the output data of the feedback memory 30, the basic digital filter is connected in multiple stages. Digital filter circuit similar frequency characteristics configured Te, and it becomes possible to realize at low cost configuration to reduce the circuit scale. Specifically, n basic digital filters can be added without adding the number of adders and multipliers in the basic digital filter by simply adding a selector, feedback memory, output memory, and delay unit. It is possible to achieve the same frequency characteristics as in the case of cascade connection.

In addition, according to the present embodiment, as shown in FIG. 2, the digital filter circuit 20 includes an adder 21 that adds the output data of the selector 11 and the output data of the multiplier 23, and , _N delay units 22Z1,..., 22Zn, which are connected in cascade, which respectively delay the output data of the adder 21 at a clock frequency n times the clock frequency of the sample value input. Multiplier input from selector 24 to output data of stage delay device 22Zn A multiplier 23 that multiplies the coefficients “A1”,..., “An”, and a selector 24 that selectively selects the multiplication coefficients “A1”,. The output data of the adder 26 and the output data of the final stage delay circuit 22Zn are added and output to the feedback memory 30. Therefore, the low pass filter is cascade connected in multiple stages. It is possible to achieve the same frequency characteristics as the configured digital filter circuit with a low-cost configuration by reducing the circuit scale.

Further, according to the present embodiment, as shown in FIG. 5 above, the output data of the final stage delay unit 22Zn is inverted between the final stage delay unit 22Zn and the calorimeter 26. Since the inverter 27 and the selector 28 that selectively selects the output data of the delay device 22Zn in the final stage and the output data of the inverter 27 and outputs the data to the adder 26 are provided, a low-pass filter and a high-pass filter are provided. Frequency characteristics similar to those of a digital filter circuit configured by cascade-connecting filters can be realized with a low cost configuration by reducing the circuit scale.

Industrial applicability

The digital filter according to the present invention can be used in various circuits of electronic equipment, and is particularly useful when it is necessary to reduce the circuit scale.

Claims

The scope of the claims

[1] Realize the same frequency characteristics as when n basic digital filters are connected in cascade.

A digital filter including an adder, a multiplier, and a delay unit, which are components of the digital filter of the basic form, and the delay unit being n-stage cascaded and operating at a clock frequency n times the clock frequency of the sample value input Circuit,

A feedback memory that stores output data that has passed through the digital filter circuit a plurality of times; an output memory that outputs the output data of the feedback memory to the outside; and an input of the digital filter circuit as a sample value input or the A first selector for selecting the output data of the feedback memory;

A digital filter comprising:

[2] The digital filter circuit includes:

A first adder for adding to the output data of the first selector and the output data of the multiplier;

N subordinately connected delay devices each delaying the output data of the first adder by one cycle of a clock having a frequency n times the clock frequency of the sample value input;

The multiplier that multiplies the output data of the delay device at the final stage by a multiplication coefficient; the second selector that alternatively selects n multiplication coefficients and outputs the multiplication coefficient to the multiplier; A second adder that adds the output data of the adder of 1 and the output data of the delay device at the final stage and outputs the result to the feedback memory;

The digital filter according to claim 1, comprising:

[3] Furthermore, an inverter that inverts output data of the final stage delay unit between the final stage delay unit and the second adder, output data of the final stage delay unit, and the second adder 3. The digital filter according to claim 2, further comprising a third selector that selectively selects output data of the inverter and outputs the data to the second adder.

[4] The basic digital filter is a low-pass filter and Z or high-pass filter. The digital filter according to claim 1, wherein the digital filter is a filter.