WO2006051816A1 - Semiconductor device and method for manufacturing same - Google Patents

Abstract

Disclosed is a semiconductor device comprising a memory array and a peripheral circuit formed in the same substrate as the memory array. The memory array includes an MTJ, and a word line and bit line through which a write current for writing data into the MTJ is passed. The word line and the bit line respectively have a conductor portion and a yoke layer covering the conductor portion. Meanwhile, ferromagnetic layers are eliminated from wiring of the peripheral circuit. Since ferromagnetic layers are readily eliminated from the wiring of the peripheral circuit in a semiconductor device having such a constitution, malfunction of the peripheral circuit caused by increase in the inductance of the wiring can be prevented.

Description

 Specification

 Semiconductor device and manufacturing method thereof

 Technical field

 The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a magnetic memory using a magnetic resistance element as a memory cell and a semiconductor device on which the magnetic memory is mounted.

 Background art

 [0002] Magnetic random access memories that store data using spontaneous magnetization of a ferromagnetic material are one of the non-volatile memories that have attracted the most attention in recent years. As a memory cell of a magnetic random access memory, a magnetoresistive element composed of two ferromagnetic layers separated by an insulating or conductive nonmagnetic layer is used. One of the two ferromagnetic layers is configured such that the direction of magnetization is easily changed by an external magnetic field, and the other is configured so that the direction of magnetization is not easily changed. The former is often called a magnetization free layer, and the latter is called a magnetization fixed layer. Digital data is stored in the memory cell as the relative angle of the magnetization direction of the two ferromagnetic layers. Stored data is retained for an extremely long period unless it is intentionally rewritten.

 [0003] Data writing in the magnetic random access memory is performed by wiring located in the vicinity of the memory cell.

 (These are often referred to as word lines, bit lines, digit lines, etc.) by applying a write current to generate a magnetic field, and the magnetic field changes the magnetization direction of the free ferromagnetic layer to a desired direction. Is called.

 [0004] For reading data from a magnetic random access memory, a phenomenon is used in which the resistance of the magnetoresistive element depends on the relative angle of the magnetization directions of the two ferromagnetic layers. Specifically, when an insulator is used as the nonmagnetic layer, the tunneling magnetoresistance effect (TMR: tunneling thigh gnetoresistance) effect is used. When a conductor is used as the nonmagnetic layer, the giant magnetoresistance effect is used. (GMR: giant magnetoresistance) is used for lj.

One problem with magnetic random access memories is a reduction in power consumption. In the magnetic random access memory, a large write current for rewriting the state of the memory cell is a main factor of power consumption. U.S. Pat.No. 3,940,319 In order to reduce this, a technique is disclosed in which the surface of the write wiring other than the surface facing the memory cell is covered with a high magnetic permeability layer formed of a high magnetic permeability material. The high permeability layer concentrates the magnetic field generated by the write current on the memory cell, thereby enabling data to be written with a small write current. Similar techniques are disclosed in JP-A-2 001-273760, JP-A-2002-246566, JP-A-2003-60172, JP-A-2003-198001, JP-A-2003-318365, JP-A-2004-. No. 31640, JP-A 2004-128011, JP-A 2004-140091, JP-A 2004-165661.

However, the above document, however, is used to access wirings coated with a high permeability layer and circuits integrated on the same substrate as the memory array, eg, memory cells. It does not discuss the consistency of the operation of peripheral circuits and logic circuits. From the viewpoint of reducing the wiring process, it may be the most appropriate force to use wiring covered with a high permeability layer as wiring for peripheral circuits and logic circuits. However, according to the inventor's study, wiring covered with a high permeability layer is not suitable for use in peripheral circuits or logic circuits because of its high inductance; it is covered with a high permeability layer. Use of wiring tends to cause malfunction of peripheral circuits and logic circuits. When using wiring covered with a high-permeability layer, an architecture is required in which the wiring does not adversely affect the operation of peripheral and logic circuits.

On the other hand, Japanese Unexamined Patent Application Publication Nos. 2002-359356 and 2004-158841 refer to the integration of MRAM memory arrays and peripheral circuits. However, these publications refer to wiring covered with a high magnetic permeability layer, and nothing else.

 Disclosure of the invention

 [0008] Therefore, the object of the present invention is not to adversely affect the operation of the circuit integrated on the same substrate as the memory array by using the wiring covered with the high permeability layer. It is to provide a magnetic memory architecture.

In one aspect of the present invention, a semiconductor device includes a memory array and a circuit formed on the same substrate as the memory array. The memory array includes a magnetoresistive element and a write wiring through which a write current for writing data to the magnetoresistive element flows. writing The wiring includes a conductor portion and a yoke layer that covers the conductor portion. The yoke layer includes a ferromagnetic layer. On the other hand, the ferromagnetic layer is substantially excluded from the circuit wiring. Here, not only when the ferromagnetic layer is completely eliminated, but also when the ferromagnetic layer residue is present when the step of removing the ferromagnetic layer is performed, It must be interpreted as falling under the “excluded” category. In the semiconductor device having such a configuration, since the ferromagnetic layer is positively excluded from the circuit wiring, it is possible to prevent the circuit from malfunctioning due to an increase in wiring inductance.

 [0010] The above circuit is typically a peripheral circuit used for accessing the magnetoresistive element.

 In one embodiment, the circuit wiring is formed in the base circuit layer, and the magnetic resistance elements and the write wiring of the memory array are formed in the memory layer formed on the base circuit layer. There is power. In this case, the circuit preferably has no wiring in the memory layer.

 [0012] In other embodiments, the circuit may include a wiring that is located in the same wiring layer as the write wiring and substantially free of the ferromagnetic layer. This configuration makes it possible to configure a circuit with a small number of wiring layers by effectively using a wiring layer in which a write wiring is formed.

 [0013] The write wiring includes a word line and a bit line that intersects with the word line, and is provided at a position where the magnetoresistive element force word line and the bit line intersect. Including the first wiring located in the same wiring layer and the second wiring located in the same wiring layer as the bit line. In this case, it is desirable that the distance between the word line and the bit line be smaller than the distance between the first wiring and the second wiring.

 [0014] In a preferred embodiment, the wiring of the circuit has a force S that is carried in a groove formed in the interlayer insulating film. In this case, in order to facilitate the loading of the wiring into the groove, it is preferable that the residue of the ferromagnetic material is left at the corner of the groove.

 In another aspect of the present invention, a method for manufacturing a semiconductor device including a memory array including a magnetoresistive element and a circuit formed on the same substrate as the memory array includes:

 (A) forming an interlayer insulating film;

(B) A first groove corresponding to a write wiring through which a write current for writing data to the magnetoresistive element flows and a second groove corresponding to a circuit wiring are formed in the interlayer insulating film. About

 (C) forming a ferromagnetic film covering the first groove and the second groove;

 (D) removing at least a part of the portion of the ferromagnetic film located inside the second groove;

 (E) After the step (D), forming a write wiring and a circuit wiring by placing a conductor in the first groove and the second groove. Such a manufacturing method makes it possible to form the write wiring covered with the ferromagnetic layer and the wiring of the circuit from which the ferromagnetic layer is excluded in the same wiring layer.

 [0016] In this manufacturing method, it is preferable that a part of the portion of the ferromagnetic film located in the second groove remains positively to facilitate embedding the conductor in the second groove. is there

In still another aspect of the present invention, a method for manufacturing a semiconductor device includes:

 (F) forming an interlayer insulating film;

 (G) forming a first groove in the interlayer insulating film corresponding to a write wiring through which a write current for writing data to the magnetoresistive element flows;

 (H) forming a ferromagnetic film on the interlayer insulating film so as to cover the first groove;

(I) forming a second groove corresponding to the circuit wiring in the interlayer insulating film by etching the ferromagnetic film and the interlayer insulating film;

 CJ) After the step (I), a step of forming a write wiring and a circuit wiring from which the ferromagnetic layer is eliminated by simultaneously embedding a conductor in the first groove and the second groove.

 It comprises. Such a manufacturing method makes it possible to form the write wiring covered with the ferromagnetic layer and the wiring of the circuit from which the ferromagnetic layer is excluded in the same wiring layer. In other words, the manufacturing method can eliminate the process of etching the ferromagnetic material located inside the second groove, and therefore, the problem of difficulty in etching the ferromagnetic material can be avoided.

In yet another aspect, a method for manufacturing a semiconductor device according to the present invention includes:

 (Ii) forming an interlayer insulating film covering the magnetoresistive element;

(L) forming a first groove corresponding to a write wiring through which a write current for writing data to the magnetoresistive element flows and a second groove corresponding to a circuit wiring in the interlayer insulating film; (M) forming a ferromagnetic film covering the first groove and the second groove;

 (N) removing a portion of the ferromagnetic film other than the first sidewall portion covering the sidewall of the first groove and the second sidewall portion covering the sidewall of the second groove;

 (O) removing the second sidewall portion of the ferromagnetic film;

 (P) Step of simultaneously embedding the first conductor in the first groove and the second conductor in the second groove after the step (O)

 It comprises. Such a manufacturing method makes it possible to form the write wiring covered with the ferromagnetic layer and the wiring of the circuit from which the ferromagnetic layer is excluded in the same wiring layer.

In yet another aspect, a method for manufacturing a semiconductor device according to the present invention includes:

 (Q) forming an interlayer insulating film covering the magnetoresistive element;

 (R) forming a first groove corresponding to a write wiring through which a write current for writing data to the magnetoresistive element flows in the interlayer insulating film;

 (S) forming a ferromagnetic layer covering the sidewall of the first groove;

 (T) After the step (S), forming a second groove corresponding to the wiring of the circuit; (U) After the step (T), the first conductor is formed in the first groove and the second groove is formed. Process to embed second conductor at the same time

 It comprises. Such a manufacturing method makes it possible to form the write wiring covered with the ferromagnetic layer and the wiring of the circuit from which the ferromagnetic layer is excluded in the same wiring layer. In addition, the manufacturing method can eliminate the step of etching the ferromagnetic material located inside the second groove, and therefore can avoid the problem of difficulty in etching the ferromagnetic material.

 [0020] The depth of the first groove is preferably deeper than the depth of the second groove.

 [0021] The manufacturing method includes:

 (V) It is preferable that the method further includes a step of forming a ferromagnetic layer covering the upper surface of the first conductor.

 [0022] According to the present invention, an architecture of a magnetic memory that does not adversely affect the operation of a circuit integrated on the same substrate as the memory array by using wiring covered with a high permeability layer. Can be provided.

Brief Description of Drawings FIG. 1 is a plan view showing a structure of a magnetic memory that is a semiconductor device according to a first embodiment of the present invention.

 FIG. 2 is a cross-sectional view showing the structure of the magnetic memory according to the first embodiment.

 FIG. 3A is a cross-sectional view showing the structure of the memory layer of the magnetic memory according to the first embodiment.

 FIG. 3B is a cross-sectional view showing the structure of the memory layer in the magnetic memory according to the first embodiment.

 FIG. 4 is a cross-sectional view showing the structure of a magnetic memory according to a second embodiment.

 FIG. 5A is a cross-sectional view showing a manufacturing process for forming a write word line and a wiring in a peripheral circuit section of a magnetic memory according to a second embodiment.

 FIG. 5B is a cross-sectional view showing the manufacturing process for forming the write word line and the peripheral circuit wiring of the magnetic memory according to the second embodiment.

 FIG. 5C is a cross-sectional view showing the manufacturing process for forming the write word line and the peripheral circuit portion wiring in the magnetic memory according to the second embodiment.

 FIG. 5D is a cross-sectional view showing the manufacturing process for forming the write word line and the peripheral circuit portion wiring in the magnetic memory according to the second embodiment.

 FIG. 5E is a cross-sectional view showing the manufacturing process for forming the write word line and the peripheral circuit line in the magnetic memory according to the second embodiment.

 FIG. 5F is a cross-sectional view showing the manufacturing process for forming the write word line and the peripheral circuit line in the magnetic memory according to the second embodiment.

 [FIG. 6A] FIG. 6A is a cross-sectional view showing the structure of the magnetic memory when residue remains in the groove in the manufacturing process of forming the write word line and the peripheral circuit wiring of the magnetic memory according to the second embodiment. FIG.

 [FIG. 6B] FIG. 6B is a cross-sectional view showing the structure of the magnetic memory when residues remain in the grooves in the manufacturing process of forming the write word line and the peripheral circuit wiring of the magnetic memory according to the second embodiment. FIG.

FIG. 7A is a cross-sectional view showing another preferred manufacturing process for forming the write word line and the peripheral circuit wiring of the magnetic memory according to the second embodiment. FIG. 7B is a cross-sectional view showing another preferable manufacturing process for forming the write word line and the peripheral circuit wiring of the magnetic memory according to the second embodiment.

7C] FIG. 7C is a cross-sectional view showing another preferred manufacturing process for forming the write word line and the peripheral circuit wiring of the magnetic memory according to the second embodiment.

7D] FIG. 7D is a cross-sectional view showing another preferable manufacturing process for forming the write word line and the peripheral circuit wiring of the magnetic memory according to the second embodiment.

8A] FIG. 8A is a cross-sectional view showing a manufacturing process for forming the bit line of the magnetic memory according to the second embodiment and the wiring of the peripheral circuit portion.

 FIG. 8B is a cross-sectional view showing the manufacturing process for forming the bit line and the peripheral circuit portion of the magnetic memory according to the second embodiment.

8C] FIG. 8C is a cross-sectional view showing the manufacturing process for forming the bit line of the magnetic memory according to the second embodiment and the wiring of the peripheral circuit portion.

FIG. 8D is a cross-sectional view showing the manufacturing process for forming the bit line and the peripheral circuit wiring of the magnetic memory according to the second embodiment.

 FIG. 8E is a cross-sectional view showing the manufacturing process for forming the bit line and the wiring of the peripheral circuit portion in the magnetic memory according to the second embodiment.

 FIG. 8F is a cross-sectional view showing the manufacturing process for forming the bit line and the peripheral circuit portion wiring in the magnetic memory according to the second embodiment.

FIG. 9 is a cross-sectional view showing the structure of the magnetic memory according to the third embodiment.

10A] FIG. 10A is a cross-sectional view showing a manufacturing process for forming the bit line of the magnetic memory according to the third embodiment and the wiring of the peripheral circuit portion.

FIG. 10B is a cross-sectional view showing the manufacturing process for forming the bit line and the peripheral circuit wiring of the magnetic memory according to the third embodiment.

10C] FIG. 10C is a cross-sectional view showing a manufacturing process for forming the bit line of the magnetic memory according to the third embodiment and the wiring of the peripheral circuit portion.

10D] FIG. 10D is a cross-sectional view showing the manufacturing process for forming the bit line of the magnetic memory according to the third embodiment and the wiring of the peripheral circuit portion.

10E] FIG. 10E shows the bit lines of the magnetic memory according to the third embodiment and the wiring of the peripheral circuit section It is sectional drawing which shows the manufacturing process which forms.

 BEST MODE FOR CARRYING OUT THE INVENTION

 [0024] First embodiment of the first embodiment

 FIG. 1 is a plan view showing a configuration of a magnetic memory 10 which is a semiconductor device according to a first embodiment of the present invention. The magnetic memory 10 includes a memory array 1 and a peripheral circuit unit 2 integrated on the same substrate. In the memory array 1, MTJ (magnetic tunnel junction) 3 which are magnetoresistive elements functioning as memory cells are arranged in a matrix. The peripheral circuit unit 2 is an area where a peripheral circuit used for accessing the memory cell is provided. The peripheral circuit unit 2 includes, for example, a row address buffer 2a, a row decoder 2b, a row driver 2c, a column address buffer 2d, a column decoder 2e, a 歹 driver 2f, a sense amplifier 2g, an output amplifier 2h, and an output buffer 2i. Provided.

 FIG. 2 is a cross-sectional view showing the structure of the magnetic memory 10.

 The magnetic memory 10 is generally composed of a base circuit layer 4 and a memory layer 5 formed thereon. The base circuit layer 4 is a portion where a MOS transistor and wiring connected thereto are formed, and includes three wiring layers: a first wiring layer 6, a second wiring layer 7, and a third wiring layer 8. Yes. Memory layer 5 is the part where MTJ3 and the wiring used to access it are formed. Interlayer insulation in the underlying circuit layer 4 is achieved by interlayer insulation films 3:! -34, and interlayer insulation in the memory layer 5 is achieved by interlayer insulation films 35-39. The underlying circuit layer 4 can be formed by a general complementary metal oxide semiconductor (CMOS) process, and the MTJ3 of the memory layer 5 can also be formed by a general process.

 The memory array 1 includes a MOS transistor 11 located in the base circuit layer 4, lands 12a to 12c, vias 13a to 13c, a ground line 14 and vias 15, and a land 16 and vias 13d located in the memory layer 5. 13e, a lower electrode 17, a write word line 18, a bit line 19, and a via 20. The land 12a and the ground line 14 are formed in the first wiring layer 6 of the base circuit layer 4, and the lands 12b and 12c are formed in the second wiring layer 7 and the third wiring layer 8, respectively.

The MTJ 3 used as a memory cell is formed on the lower electrode 17 of the memory layer 5. As shown in Figure 3A, MTJ3 is a pinned magnetization formed on the bottom electrode 17. A layer 3a, a magnetization free layer 3c, and an insulating barrier layer 3b interposed therebetween are provided. MTJ3 is provided at a position where the write word line 18 and the bit line 19 intersect, and data is written to MTJ3 by passing a write current through the write word line 18 and the bit line 19. Further, as shown in FIG. 2, MTJ3 is connected to the drain 11a of the MOS transistor 11 via the lower electrode 17, the lands 12a to 12d and the vias 13a to 13e, and further via the via 20. Connected to bit line 19. The source l ib of the MOS transistor 1 1 is connected to the ground line 14 via the via 15. The gate 11a of the MOS transistor 11 functions as a read word line, and the MOS transistor 11 is used to select a memory cell during a read operation. During the read operation, the MOS transistor 11 is turned on, and a predetermined voltage is applied to the bit line 19. As a result, a current flows from the bit line 19 to the ground line 14 via the MTJ3, and the data written in the MTJ3 is determined by the magnitude of the current.

[0028] In order to reduce the write current, the write word line 18 and the bit line 19 through which the write current flows are composed of a conductive layer covered with a yoke layer; the yoke layer is ferromagnetic A structure including a layer formed of a body. More specifically, as shown in FIG. 3A, the write word line 18 includes a conductor layer 18a and a yoke layer 18b covering the bottom and side surfaces thereof. Similarly, as shown in FIG. 3B, the bit line 19 includes a conductor layer 19a and a yoke layer 19b covering the upper surface and side surfaces thereof. The yoke layers 18b and 19b concentrate the magnetic field generated by the write current on the MTJ3, effectively reducing the write current.

 As shown in FIG. 3A, the land 16 belonging to the same wiring layer as the write word line 18 composed of the conductor layer 18 a covered with the yoke layer 18 b is the same as the write word line 18. It has the structure of. More specifically, the land 16 includes a conductor layer 16a and a yoke layer 16b covering the bottom surface and the side surface thereof.

Referring back to FIG. 2, the peripheral circuit section 2 includes the MOS transistor 21, wirings 22a to 22c, and vias 23a to 23c located in the base circuit layer 4. The wiring 22 a is formed in the first wiring layer 6 of the base circuit layer 4, the wiring 22 b is formed in the second wiring layer 7, and the wiring 22 c is formed in the third wiring layer 8. MOS transistor 21 and wiring 22a are connected via via 23a. The self-line 22a and the wiring 22b are connected via the via 23b, and the wiring 22b and the wiring 22c are connected via the via 23c.

 [0031] In the magnetic memory 10 of the first embodiment having such a configuration, the peripheral circuit unit 2 does not use wiring located in the memory layer 5. That is, the peripheral circuit section 2 does not use a wiring covered with a yoke layer (that is, a ferromagnetic layer) belonging to the same wiring layer as the write word line 18 and the bit line 19, but uses only a normal wiring. Shinare. Such a configuration effectively prevents the peripheral circuit portion 2 from malfunctioning by using the wiring covered with the yoke layer.

 [0032] Second embodiment of the second embodiment

 One problem with the magnetic memory 10 according to the first embodiment is that many wiring layers are required. The magnetic memory 10 according to the first embodiment includes at least five wiring layers (i.e., first to third wiring layers 6 to 8) to form the peripheral circuit section 2 having three wiring layers. 2 wiring layers in which the write word line 18 and the bit line 19 are formed are required. The use of many wiring layers is undesirable because it increases the manufacturing cost of the magnetic memory 10.

 [0033] In order to solve the problem, in the magnetic memory 10A of the second embodiment, as shown in FIG. 4, the wiring of the same wiring layer as that of the write word line 18 and the bit line 19 is connected to the periphery. Also used for circuit part 2. Along with this, the second wiring layer 7 and the third wiring layer 8 are removed. However, when forming a wiring belonging to the same wiring layer as the write word line 18 and the bit line 19 in the peripheral circuit section 2, a process for removing the ferromagnetic layer from the wiring is performed. As described above, removing the ferromagnetic layer is important for reducing the inductance of the wiring of the peripheral circuit section 2 and preventing malfunction.

 More specifically, the peripheral circuit section 2 is provided with a self line 41 belonging to the same wiring layer as the write word line 18 and a wiring 42 belonging to the same wiring layer as the bit line 19. The wirings 41 and 42 are both normal wirings that are not covered with the yoke layer. The wiring 41 is connected to the wiring 22 a belonging to the first wiring layer 6 through a via 43 that penetrates the interlayer insulating film 35. The wiring 42 is connected to the wiring 41 through a via 44 that penetrates the interlayer insulating films 36 and 37.

In order to form the wiring 41 that is not covered by the yoke layer in the same wiring layer as the write word line 18 having the yoke layer 18b, a special manufacturing process is required. Figure 5A FIG. 5F is a cross-sectional view showing a process for forming the write word line 18 having the yoke layer 18b and the wiring 41 not covered with the yoke layer in the same wiring layer.

 Referring to FIG. 5A, in the manufacturing process of forming write word line 18 and wiring 41 in the same wiring layer, first, groove 36a for forming write word line 18 is formed in interlayer insulating film 36. And a step of forming a groove 36b for forming the wiring 41 is performed. The groove 36 a is provided in the memory array 1, and the groove 36 b is provided in the peripheral circuit unit 2.

 Subsequently, as shown in FIG. 5B, a barrier film 51, a ferromagnetic film 52, and a noria film 53 are sequentially formed. In the present embodiment, a laminated film (Ta / TaN film) of a tantalum film and a tantalum nitride film is used as the barrier films 51 and 53, and a NiFe film is used as the ferromagnetic film 52. The barrier film 51 also has a role of improving the adhesion between the ferromagnetic film 52 and the interlayer insulating film 36.

 Subsequently, as shown in FIG. 5C, after the resist mask 54 covering the grooves 36a located in the memory array 1 is formed, the barrier film 53 and the ferromagnetic film 5 are formed using the resist mask 54. 2 are sequentially etched. As a result, the ferromagnetic film 52 is removed from the peripheral circuit portion 2. The barrier film 53 is selected by reactive etching using a fluorine-based gas (for example, CF).

 Four

 Selectively etched. The ferromagnetic film 52 is etched by a wet etch using an etchant such as nitric acid. By optimizing the etching solution, it is possible to selectively etch the ferromagnetic film 52 with the rear film 51 remaining.

 Subsequently, as shown in FIG. 5D, after the resist mask 54 is removed, RF tallying is performed, and the rear film 51 is removed.

 Subsequently, as shown in FIG. 5E, after the barrier film 55 and the seed film for plating (not shown) are formed, the wiring metal film 56 is formed by plating. . The wiring metal film 56 is typically formed of aluminum, an aluminum alloy, copper, or a copper alloy. The grooves 36a and 36b are both filled with the wiring metal film 56.

Subsequently, as shown in FIG. 5F, portions of the barrier film 51, the ferromagnetic film 52, the barrier film 53, the barrier film 55, and the wiring metal film 56 that are located outside the grooves 36a and 36b. Are removed by CMP (chemical mechanical polishing). As a result, the groove 36a has a conductor layer 18a composed of a barrier layer 55a and a wiring metal layer 56a, and a barrier layer 51a and a ferromagnetic layer 52a. The yoke layer 18b is formed, and the formation of the write word line 18 to the memory array 1 is completed. On the other hand, the barrier layer 55b and the wiring metal layer 56b remain in the trench 36b, and the wiring 41 is formed.

 [0042] According to such a manufacturing process, the write word line 18 having the yoke layer 18b and the wiring 41 having no yoke layer can be formed in the same wiring layer.

 [0043] The provision of the yoke layer in the wiring 41 is also effective in reducing the wiring width rule of the wiring provided in the peripheral circuit section 2. Ferromagnetic materials have a relatively high electrical resistance, so the yoke layer hardly contributes as a conductor for transmitting signals. Therefore, the width required for the portion of the wiring where the current actually flows out of the wiring in which the yoke layer is provided on the side surface is almost the same as the width of the wiring in which the yoke layer is not provided on the side surface. This means that the force of providing the yoke layer on the side of the wiring leads to an increase in the wiring width. However, in the magnetic memory 10A of the present embodiment, the yoke layer is not formed on the wiring 41. Therefore, in the magnetic memory 10A of the present embodiment, the rule of the wiring width of the wiring provided in the peripheral circuit unit 2 can be further reduced.

 [0044] The problem in the manufacturing process shown in FIGS. 5A to 5F is that the ferromagnetic material etching technique necessary for the process of etching the ferromagnetic film 52 in FIG. 5C is sufficiently established. It is not. In particular, as shown in FIG. 6A where the etching of the ferromagnetic film 52 is difficult to proceed inside the groove 36b, the residue 57 tends to remain at the corner of the groove 36b in the process of etching the ferromagnetic film 52.

 However, it is not a problem that some residue 57 remains in the process of etching the ferromagnetic film 52. As shown in FIG. 6B, even if the above manufacturing process is performed with the residue 57 left in the corner of the groove 36b, the residue 57 of the ferromagnetic film 52 and the residue of the barrier film 51 are left in the corner of the groove 36b. Only 51b remains, and the function of peripheral circuit section 2 is not affected. Rather, leaving the residue 57 may be beneficial to load the wiring 41 into the groove 36b. By leaving the residue 57 at the corner of the groove 36b, it becomes unnecessary to bury the barrier film 55 and the wiring metal film 56 in the corner of the groove 36b. This enables the wiring 41 to be caught in the groove 36b while preventing voids from occurring in the corners.

[0046] To alleviate the problem of etching difficulty of ferromagnetic materials, FIG. As described above, it is also preferable to employ a manufacturing process in which the ferromagnetic film is not formed inside the groove where the wiring 41 is formed. In this manufacturing process, first, as shown in FIG. 7A, a groove 36 a for forming the write word line 18 is formed in the memory array 1 in the interlayer insulating film 36. In this step, no groove is formed in the peripheral circuit portion 2.

Subsequently, as shown in FIG. 7B, the barrier film 51, the ferromagnetic film 52, and the barrier film 53 are sequentially formed. The barrier film 51, the ferromagnetic film 52, and the barrier film 53 are formed along the side surface and the bottom surface of the groove 36a. In the present embodiment, as the barrier films 51 and 53, a laminated film of a tantalum film and a tantalum nitride film (TaZTaN film) is used. As the ferromagnetic film 52, a NiFe film is used.

 Subsequently, as shown in FIG. 7C, after the resist mask 58 is formed, a groove 36 c is formed in the peripheral circuit portion 2 by etching using the resist mask 58. The resist mask 58 has an opening at a position corresponding to the groove 36c, and is formed so as to completely cover the memory array 1.

 Subsequently, as shown in FIG. 7D, after the resist mask 58 is removed, the grooves 36a of the memory array 1 and the grooves 36c of the peripheral circuit portion 2 are formed by the same process as the above-described manufacturing process. It is carried. More specifically, after the resist mask 58 is removed, a barrier film 55 and a seed film for bonding (not shown) are formed. Further, using the seed film, a wiring metal film 56 is formed by plating. Subsequently, portions of the barrier film 51, the ferromagnetic film 52, the barrier film 53, the barrier film 55, and the wiring metal film 56 that are located outside the grooves 36a and 36b are removed by CMP (chemical mechanical polishing). The As a result, a conductor layer 18a composed of a barrier layer 55a and a wiring metal layer 56a and a yoke layer 18b composed of a barrier layer 51a and a ferromagnetic layer 52a are formed inside the groove 36a, and a write word to the memory array 1 is formed. The formation of line 18 is complete. On the other hand, a wiring 41 composed of a barrier layer 55b and a wiring metal layer 56b is formed in the groove 36b.

 In this manufacturing process, the ferromagnetic film 52 is not formed inside the groove 36c of the peripheral circuit portion 2.

 Therefore, the difficulty of etching the ferromagnetic film 52 can be reduced.

[0051] Similar to the write word line 18 and the wiring 41, in order to form the wiring 42 not covered with the yoke layer in the same wiring layer as the bit line 19 having the yoke layer 19b, Requires a simple manufacturing process. 8A to 8F are cross-sectional views showing steps for forming the bit line 19 having the yoke layer 19b and the wiring 42 not covered with the yoke layer in the same wiring layer.

 Referring to FIG. 8A, in the manufacturing process of forming bit line 19 and wiring 42 in the same wiring layer, first, groove 39a for forming bit line 19 in interlayer insulating film 39, and wiring A step of forming a groove 39b for forming 42 is performed. The groove 39a is provided in the memory array 1, and the groove 39b is provided in the peripheral circuit portion 2. The barrier film 61, the ferromagnetic film 62, and the barrier film 63 are sequentially formed. In the present embodiment, a laminated film (TaZTaN film) of a tantalum film and a tantalum nitride film is used as the barrier films 61 and 63, and a NiFe film is used as the ferromagnetic film 62.

 Subsequently, as shown in FIG. 8B, a portion of the barrier film 61, the ferromagnetic film 62, and the barrier film 63 that covers the upper surface of the interlayer insulating film 39, and the bottom surfaces of the grooves 39a and 39b. The portion covering the surface is removed by anisotropic etching. As a result, the barrier film 61, the ferromagnetic film 62, and the barrier film 63 are left only on the side walls of the trench 39a and the trench 39b. Hereinafter, the barrier film 61, the ferromagnetic film 62, and the barrier film 63 left in the trench 39a of the memory array 1 are referred to as the barrier layer 61a, the ferromagnetic layer 62a, and the barrier layer 63a. On the other hand, the barrier film 61, the ferromagnetic film 62, and the rear film 63 left in the groove 39b of the peripheral circuit section 2 are referred to as a barrier layer 61b, a ferromagnetic layer 62b, and a barrier layer 63b hereinafter.

 Subsequently, as shown in FIG. 8C, a resist mask covering the grooves 39a of the memory array 1

 After 69 is formed, the barrier layer 63b and the ferromagnetic layer 62b inside the groove 39b of the peripheral circuit portion 2 are removed by force etching. The barrier layer 63b is made of fluorine gas (for example, CF).

 4 Removed by reactive etching used. On the other hand, the ferromagnetic layer 62b is etched by wet etching using an etching solution such as HC1. By optimizing the etching solution, the ferromagnetic layer 62b can be selectively etched while the barrier layer 61b remains.

[0055] Subsequently, as shown in FIG. 8D, after the resist mask 69 is removed, RF tallying is performed, and the barrier layer 63a of the memory array 1 and the barrier layer 61b of the peripheral circuit unit 2 are performed. Is removed. Subsequently, as shown in FIG. 8E, after the resist mask 69 is removed, the grooves 39a of the memory array 1 and the grooves 39b of the peripheral circuit portion 2 are filled with wiring metal. More specifically, after the resist mask 69 is removed, a barrier film and a seed film for adhesion are formed. Furthermore, a wiring metal film is formed by plating using the seed film. Subsequently, the formed barrier film and wiring metal film are removed by partial force CMP (chemical mechanical polishing) located outside the grooves 39a and 39b. As a result, a conductor layer 19a composed of the barrier layer 64a and the wiring metal layer 65a is formed inside the groove 39a of the memory array 1. On the other hand, the barrier layer 64b and the wiring metal layer 65b remain inside the groove 39b of the peripheral circuit portion 2, and thereby the wiring 42 is formed.

 Subsequently, as shown in FIG. 8F, after the first barrier film, the ferromagnetic film, and the second noor film are formed in the same manner, they are patterned, so that the memory A barrier layer 66, a ferromagnetic layer 67, and a barrier layer 68 covering the grooves 39a of the array 1 are formed. The yoke layer 19b is constituted by the no layer 61a, the ferromagnetic layer 62a, the noble layer 66, the ferromagnetic layer 67, and the barrier layer 68, and the formation of the bit line 19 is completed.

 According to such a manufacturing process, the bit line 19 having the yoke layer 19b and the wiring 42 having no yoke layer can be formed in the same wiring layer.

 [0059] Third Embodiment of Third Embodiment

 Referring to FIG. 4, in the magnetic memory 10A of the second embodiment, the distance between the write side line 18 and the bit line 19 in the memory array 1 is the same as the wiring 41 and the wiring 42 in the peripheral circuit section 2. The distance between is the same.

[0060] With such a structure, there is a drawback in that a reduction in write current and a reduction in capacitance between layers of the peripheral circuit section 2 conflict. In order to reduce the write current, it is preferable to reduce the distance between the write word line 18 and MTJ3 and the distance between the bit line 19 and MTJ3. For this purpose, it is necessary to reduce the distance between the write word line 18 and the bit line 19. However, if the distance between the write word line 18 and the bit line 19 is decreased, the distance between the wiring 41 and the wiring 42 in the peripheral circuit section 2 is also reduced; because the wiring 41 in the peripheral circuit section 2 is written. This is because the self-line 42 belongs to the same wiring layer as the bit line 19 and belongs to the same wiring layer as the word line 18. When the distance between wiring 41 and wiring 42 decreases, wiring 41 and wiring Capacity between 42 is increased. An increase in capacitance between the wiring 41 and the wiring 42 is not preferable because it causes an increase in wiring delay.

 [0061] In the third embodiment, a structure of a magnetic memory is provided to eliminate a strong defect. As shown in FIG. 9, in the magnetic memory 10B of the third embodiment, the distance between the write word line 18 and the bit line 19 of the memory array 1 is the same as that of the wiring 41 of the peripheral circuit section 2. A structure that is smaller than the distance between the wiring 42 and the wiring 42 is adopted. Adopting a force and a structure to reduce the write current by reducing the distance between the write lead wire 18 and MTJ3 and the distance between the bit line 19 and MTJ 3 while reducing the write current. It is possible to reduce the interlayer capacity by sufficiently increasing the distance between the two.

 In the present embodiment, in order to realize this structure, the groove 39a for forming the bit line 19 of the memory array 1 and the groove 39b for forming the wiring 42 of the peripheral circuit section 2 are separated. The manufacturing process formed in this process is adopted (see FIGS. 10A to 10E). The depth force of the groove 39a for forming the bit line 19 is made deeper than the depth of the groove 39b for forming the wiring 42, so that the write word line 18 and the bit line 19 of the memory array 1 are connected. Distance force between them is made smaller than the distance between the wiring 41 and the wiring 42 in the peripheral circuit section 2. Accordingly, in the present embodiment, the interlayer insulating film 38 is formed of two layers of insulating films 38a and 38b. The via 20 connected to the MTJ3 is formed so as to reach the upper surface of the insulating film 38a, and the via 44 connected to the wiring 41 is formed so as to reach the upper surface of the insulating film 38b. Hereinafter, the manufacturing process employed in the present embodiment will be described in detail.

 In the manufacturing process for forming the bit lines 19 of the memory array 1 and the wirings 42 of the peripheral circuit portion 2, first, grooves 39 a are formed in the memory array 1 as shown in FIG. 1OA. The trench 39a is formed to reach the via 20 through the interlayer insulating film 39 and the insulating film 38a. In this process, no groove is formed in the peripheral circuit portion 2.

Subsequently, as shown in FIG. 10B, a barrier layer 61a, a ferromagnetic layer 62a, and a barrier layer 63a are formed on the side wall of the groove 39a. The formation of the noria layer 61a, the ferromagnetic layer 62a, and the barrier layer 63a is performed in the same process as in the second embodiment. Specifically, first, a first barrier film, a ferromagnetic film, and a second barrier film are sequentially formed. In this embodiment, a multilayer film (TaZTaN film) of a tantalum film and a tantalum nitride film is used as the barrier film, and ferromagnetic film is used. A NiFe film is used as the film. Subsequently, of the two barrier films and the ferromagnetic film thus formed, the portion covering the upper surface of the interlayer insulating film 39 and the bottom surface of the groove 39a is removed by anisotropic etching. As a result, the barrier layer 61a, the ferromagnetic layer 62a, and the barrier layer 63a are left only on the side wall of the groove 39a.

 Three

 Subsequently, as shown in FIG. 10C, after the resist mask 71 is formed, a groove 39b is formed in the peripheral circuit portion 2 by etching using the resist mask 71. The resist mask 71 has an opening at a position corresponding to the groove 39b, and is formed so as to completely cover the memory array 1. The depth of the groove 39b formed in the peripheral circuit portion 2 is shallower than the depth of the groove 39a formed in the memory array 1.

 Subsequently, as shown in FIG. 10D, after the resist mask 71 is removed, the groove 39a of the memory array 1 and the groove of the peripheral circuit section 2 are performed by the same process as the manufacturing process of the second embodiment. 39b is loaded. More specifically, after the resist mask 71 is removed, a barrier film and a seed film (not shown) for adhesion are formed. Furthermore, a wiring metal film is formed by plating using the seed film. Subsequently, the formed barrier film and wiring metal film are removed by partial force CMP (chemical mechanical polishing) located outside the grooves 39a and 39b. As a result, the conductor layer 19a composed of the barrier layer 64a and the wiring metal layer 65a is formed inside the groove 39a, and the wiring 42 composed of the barrier layer 64b and the wiring metal layer 65b is formed inside the groove 39b. .

 Subsequently, as shown in FIG. 10E, after the first barrier film, the ferromagnetic film, and the second barrier film are formed in accordance with the same, they are patterned to form the memory array 1. A barrier layer 66, a ferromagnetic layer 67, and a barrier layer 68 covering the groove 39a are formed. The noak layer 61a, the ferromagnetic layer 62a, the noria layer 63a, the noria layer 66, the ferromagnetic layer 67, and the barrier layer 68 constitute the fork layer 19b, and the formation of the bit line 19 is completed.

 [0068] As can be understood from FIG. 10E, according to such a manufacturing process, the distance force S between the write word line 18 and the bit line 19 of the memory array 1 and the wiring 41 of the peripheral circuit section 2 are obtained. It is possible to form a structure that is smaller than the distance between the wiring 42 and the wiring 42.

[0069] In the manufacturing process of the present embodiment, there is a strong force inside the groove 39b in which the wiring 42 is formed. This is also effective in reducing the problem of difficulty in etching ferromagnetic materials since the magnetic film is not formed.

 [0070] Fourth Summary

 As described above, in the magnetic memories according to the first to third embodiments, the yoke layers 18b and 19b are formed on the write lead line 18 and the bit line 19, while the peripheral circuit portion 2 has Wiring force The ferromagnetic layer is actively eliminated. This makes it possible to prevent malfunction of the peripheral circuit unit 2 due to an increase in wiring inductance while reducing the write current.

 In the magnetic memories of the second and third embodiments, the write node 18 of the memory array 1 and the interconnect 41 of the peripheral circuit section 2 are formed in the same interconnect layer, and the bit The line 19 and the wiring 42 of the peripheral circuit section 2 are formed in the same wiring layer. As a result, the total number of wiring layers can be reduced.

 Further, in the magnetic memory of the third embodiment, the distance between the write word line 18 and the bit line 19 in the memory array 1 is larger than the distance between the wiring 41 and the wiring 42 in the peripheral circuit section 2. A structure that makes it smaller is adopted. This makes it possible to reduce the interlayer capacitance while reducing the write current.

 The present invention can also be applied to a semiconductor device in which a logic circuit and a magnetic memory are integrated on the same substrate. In this case, the logic circuit is formed in the same structure as that of the peripheral circuit unit 2, and malfunction of the logic circuit due to an increase in wiring inductance is prevented.

Claims

The scope of the claims

 [1] Memory array,

 Circuit formed on the same substrate as the memory array

 And

 The memory array is

 A magnetoresistive element;

 A write wiring through which a write current for writing data to the magnetoresistive element flows,

 The write wiring is

 A conductor portion;

 A yoke layer covering the conductor and including a ferromagnetic layer

 And

 The ferromagnetic layer is substantially excluded from the wiring of the circuit.

 Semiconductor device.

 [2] The semiconductor device according to claim 1,

 The semiconductor device is a peripheral circuit used for accessing the magnetoresistive element.

 [3] The semiconductor device according to claim 1,

 The wiring of the circuit is formed in a base circuit layer,

 The magnetoresistive element and the write wiring of the memory array are formed in a memory layer formed on the base circuit layer,

 The circuit has no wiring in the memory layer

 Semiconductor device.

 [4] Memory array;

 Circuit formed on the same substrate as the memory array

 And

 The memory array is

A magnetoresistive element; A write wiring through which a write current for writing data to the magnetoresistive element flows,

 The write wiring is

 A word line,

 Bit line crossing the word line

 And

 The magnetoresistive element is provided at a position where the word line and the bit line intersect, and the word line and the bit line include a yoke layer including a ferromagnetic layer at a facing portion of at least a portion facing the magnetoresistive element Have

 The ferromagnetic layer is substantially excluded from the wiring of the circuit.

 Semiconductor device.

[5] The semiconductor device according to claim 4,

 The semiconductor device is a peripheral circuit used for accessing the magnetoresistive element.

[6] The semiconductor device according to claim 4,

 The circuit is

 A peripheral circuit used to access the magnetoresistive element;

 Logic circuit for controlling the memory of the magnetoresistive element

 And including

 Semiconductor device.

[7] The semiconductor device according to claim 4,

 The wiring of the circuit includes a first wiring located in the same wiring layer as the word line, and a second wiring located in the same wiring layer as the bit line,

 A semiconductor device in which a ferromagnetic layer is substantially excluded from the first wiring and the second wiring.

[8] Memory array,

 Circuit formed on the same substrate as the memory array

And The memory array is

 A magnetoresistive element;

 A write wiring through which a write current for writing data to the magnetoresistive element flows,

 The write wiring is

 A conductor portion;

 A yoke layer covering the conductor and including a ferromagnetic layer

And

 The circuit includes a wiring located in the same wiring layer as the write wiring, and the ferromagnetic layer is substantially excluded from the wiring.

 Semiconductor device.

 The semiconductor device according to claim 8, wherein

 The write wiring is

 Word line and

 Bit line crossing the word line

And

 The magnetoresistive element is provided at a position where the word line and the bit line intersect, and the wiring of the circuit is

 A first wiring located in the same wiring layer as the word line;

 Second wiring located in the same wiring layer as the bit line

Including

 The distance between the word line and the bit line is smaller than the distance between the first wiring and the second wiring.

 Semiconductor device.

 A memory array;

 Circuit formed on the same substrate as the memory array

And

The memory array is A magnetoresistive element;

 A write wiring through which a write current for writing data to the magnetoresistive element flows,

 The write wiring is

 A conductor portion;

 A yoke layer covering the conductor and including a ferromagnetic layer

 And

 The circuit is

 A wiring located in the same wiring layer as the write wiring, which is held in a groove formed in the interlayer insulating film;

 Includes ferromagnetic residue formed in the corner of the groove

 Semiconductor device.

 [11] A method of manufacturing a semiconductor device including a memory array including a magnetoresistive element and a circuit formed on the same substrate as the memory array,

 (A) forming an interlayer insulating film;

 (B) forming a first groove corresponding to a write wiring through which a write current for writing data to the magnetoresistive element flows and a second groove corresponding to the circuit wiring in the interlayer insulating film;

 (C) forming a ferromagnetic film covering the first groove and the second groove;

(D) removing at least a part of a portion of the ferromagnetic film located inside the second groove;

 (E) After the step (D), the step of forming the write wiring and the wiring of the circuit by placing a conductor in the first groove and the second groove

 And comprising

 A method for manufacturing a semiconductor device.

 [12] A method of manufacturing a semiconductor device according to claim 11,

A method for manufacturing a semiconductor device, wherein a part of a portion of the ferromagnetic film located inside the second groove remains. [13] A method of manufacturing a semiconductor device including a memory array including a magnetoresistive element and a circuit formed on the same substrate as the memory array,

 (F) forming an interlayer insulating film;

 (G) forming a first groove in the interlayer insulating film corresponding to a write wiring through which a write current for writing data to the magnetoresistive element flows;

 (H) forming a ferromagnetic film on the interlayer insulating film so as to cover the first groove;

 (I) forming a second groove corresponding to the wiring of the circuit in the interlayer insulating film by etching the ferromagnetic film and the interlayer insulating film;

 CO After the step (I), a step of forming the write wiring and the wiring of the circuit by simultaneously burying a conductor in the first groove and the second groove

 And comprising

 A method for manufacturing a semiconductor device.

[14] A method of manufacturing a semiconductor device including a memory array including a magnetoresistive element and a circuit formed on the same substrate as the memory array,

 (K) forming an interlayer insulating film covering the magnetoresistive element;

 (L) forming a first groove corresponding to a write wiring through which a write current for writing data to the magnetoresistive element flows and a second groove corresponding to the circuit wiring in the interlayer insulating film;

 (M) forming a ferromagnetic film that covers the first groove and the second groove; and (N) a first side wall portion that covers a side wall of the first groove in the ferromagnetic film; Removing a portion other than the second sidewall portion covering the sidewall of the second groove;

 (O) removing the second sidewall portion of the ferromagnetic film;

 (P) After the step (O), the step of simultaneously loading the first conductor in the first groove and the second conductor in the second groove

 And comprising

 A method for manufacturing a semiconductor device.

[15] A memory array including magnetoresistive elements and a circuit formed on the same substrate as the memory array. A method of manufacturing a semiconductor device including a road,

 (Q) forming an interlayer insulating film covering the magnetoresistive element;

 (R) forming a first groove in the interlayer insulating film corresponding to a write wiring through which a write current for writing data to the magnetoresistive element flows;

 (S) forming a ferromagnetic layer covering the side wall of the first groove;

 (T) After the step (S), forming a second groove corresponding to the wiring of the circuit; (U) After the step (T), the first conductor is placed in the first groove, and The process of simultaneously loading the second conductor into the two grooves

 And comprising

 A method for manufacturing a semiconductor device.

 [16] The method of manufacturing a semiconductor device according to claim 15,

 The depth of the first groove is deeper than the depth of the second groove.

 A method for manufacturing a semiconductor device.

[17] A method of manufacturing a semiconductor device according to claim 15 or claim 16,

 (V) forming a ferromagnetic layer covering the upper surface of the first conductor

 Further comprising

 A method for manufacturing a semiconductor device.