KR101154468B1 - Solid-state memory device and method for arrangement of solid-state memory cells - Google Patents

Abstract

A large capacity magnetic memory device in which a writing magnetic field is almost uniform for all memory elements. This apparatus is realized by reducing the deformation of the resist pattern generated during the photolithography process when the mask patterns are in close proximity to each other. A magnetic memory device is an MRAM composed of many memory cells, each memory cell including one TMR element, one read (select) transistor, and a read plug that connects the TMR element to a read (select) transistor. This memory cell is formed such that the TMR element has translational symmetry. For writing, each memory cell is connected by bit lines or writing word lines orthogonal to each other. Since the long axis of the TMR element is oriented with an inclination of 45 degrees with respect to these lines, the TMR elements enable toggle mode writing.

Description

Solid-state memory device and method for arrangement of solid-state memory cells

1 is a plan view showing an arrangement of memory cells in an MRAM according to Embodiment 1 of the present invention.

2 is a cross-sectional view showing an arrangement relationship between memory cells in the same MRAM as described above.

3 is a plan view showing the arrangement of memory cells in the MRAM according to the second embodiment of the present invention.

4 is a plan view showing the arrangement of memory cells in an MRAM according to Embodiment 3 of the present invention.

Fig. 5 is a plan view showing the arrangement of memory cells in an MRAM according to Embodiment 4 of the present invention.

6 is a schematic perspective view of a TMR element of an MRAM.

7 is a schematic perspective view showing a part of a memory cell of the MRAM.

8 is an equivalent circuit diagram of an MRAM.

9 is an equivalent circuit diagram of the MRAM.

10 is a schematic cross-sectional view of a memory cell of a conventional MRAM.

Fig. 11 is a magnetic field response characteristic at the time of writing of a TMR element.

Fig. 12 is a magnetic field response characteristic diagram during writing of two TMR elements.

Fig. 13 is a principle diagram showing a read operation of the TMR element.

14 is a layout view of elements in a 1 M bit MRAM.

Fig. 15 is a plan view showing the arrangement of memory cells in a conventional MRAM.

FIG. 16 is a cross-sectional view showing an arrangement relationship between memory cells in a conventional MRAM. FIG.

17 (17a-17d) are schematic cross-sectional views showing a manufacturing process of a memory cell of a conventional MRAM.

18 (18a-18d) are schematic cross-sectional views showing a manufacturing process of a memory cell of a conventional MRAM.

19 is a graph showing an example of distribution of read resistance of a conventional TMR element.

20 is a graph showing an example of distribution of asteroid writing characteristics of a conventional TMR element.

21 is an explanatory diagram showing a proximity effect in the process of forming a resist mask pattern corresponding to the shape of a TMR element in the fabrication of a memory cell of a conventional MRAM.

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a solid state memory device and a method of arranging solid state memory cells fabricated by a lithography process, wherein the solid state memory device includes a magnetic random access memory (MRAM), a dynamic random access memory (DRAM), and a static random access memory (SRAM). , Ferroelectric Random Access Memory (FRAM), Read Only Memory (ROM), Programmable ROM (PROM), and Erasable and Programmable ROM (EPROM). More specifically, the present invention relates to an arrangement pattern of information storage portions of a memory element.

BACKGROUND ART [0002] In recent years, with the rapid expansion of personal communication devices such as personal communication devices such as portable terminals, improved performances such as high integration, high speed, low power consumption, and the like are required for memories and logic elements constituting such devices.

In particular, nonvolatile memory is considered indispensable in the era of ubiquitous computing. This is because nonvolatile memory can protect important information including personal information in the event of power consumption, server failure, or network failure. Modern portable devices are designed to reduce power consumption as much as possible by keeping unnecessary circuit blocks in a standby state, but it is possible to save power consumption and memory if a high-speed, large capacity nonvolatile memory is realized. In addition, if a high-capacity large-capacity nonvolatile memory can be realized, an "instant-on" function that can be started immediately after the power supply is enabled also becomes possible.

Examples of the nonvolatile memory include flash memory using a semiconductor, ferroelectric random access memory (FRAM), and the like using ferroelectrics.

However, in the flash memory, the information writing time is limited in units of μsec, and for the FRAM, the rewriting period is 10 ¹² to 10 ¹⁴ , that is, the static random access memory (SRAM) and the dynamic random access memory (DRAM). The problem that the durability is small and the microfabrication of a ferroelectric capacitor is difficult when trying to replace) is pointed out.

Without these drawbacks, high-speed, large-capacity (or high-density), low power consumption nonvolatile memories have attracted attention, which are magnetic memory devices called MRAMs (Magnetic Random Access Memory).

Early MRAMs were reported in JMDaughton, Thin Solid Films, vol. 216, pp. 162-168, 1992, anisotropic magnetoresistive (AMR) effects, DDTang et al., IEDM Technical Digest, pp. 995-997 And spin valves using the Giant Magnetoresistance (GMR) effect reported in 1997. However, such a memory has a drawback in that the load has a low memory cell resistance of 10 to 100 Ω, so that the power consumption per bit for reading is large and the capacity of the memory is difficult.

On the other hand, there is another type of MRAM using the tunnel magnetoresistance TMR (Tunnel Magnetoresistance) effect. It has a resistance change rate of almost 20% (T. Miyazaki et al., 1 to 2% at room temperature, as reported in R. Meservey et al., Physics Reports, vol.238, pp.214-217, 1994). , J.Magnetism & Magnetic Material, vol.139, (L231), as reported in 1995).

The TMR element is composed of two magnetic layers, a magnetization free layer (memory layer) and a magnetization pinned layer, and has a structure in which a tunnel barrier layer is inserted between these two magnetization layers, and the magnetization directions of the two magnetization layers are "parallel". Information of " 0 " or " 1 " This relative difference in magnetization direction changes the strength of the current flowing through the tunnel barrier layer, which allows reading of the information.

The TMR type MRAM has a TMR element arranged in a matrix pattern, and in order to write information to the TMR element, bit lines for access in the column direction and the row direction, and word lines for writing. Have Information is selectively written only in a TMR element located at the intersection of two lines. This process utilizes the steroid properties described below.

Therefore, TMR type MRAM is a semiconductor magnetic memory that can read information by using the magnetoresistive effect generated from the spin-dependent conduction peculiar to the nano magnetic material. Nonvolatile memory that can be stored. In addition, since the structure is simple, high integration is easy. In addition, since the recording is performed by the rotation of the magnetic moment, rewriting can be performed many times, and the access time can be extremely high. In fact, it is already reported that it can operate at 100 MHz in R. Scheuerlein et al., ISSCC Digest of Technical Papers, pp. 128-129, Feb. 2000.

Hereinafter, the TMR type MRAM will be described in more detail.

6 is a perspective view of a TMR element 10 serving as a storage element of a memory cell of an MRAM. The TMR element 10 is formed on the support substrate 8, and includes a magnetization free layer (memory layer) 2 in which the magnetization direction is relatively easily reversed, and a magnetization pinned layer 4 in which the magnetization direction is fixed. have. As the magnetization free layer (memory layer) 2 and the magnetization pinned layer 4, a ferromagnetic material mainly containing nickel, iron, cobalt, or such an alloy is used. The magnetized pinned layer 4 may be a multilayer film (lamination film of ferromagnetic material / metal / ferromagnetic material) having a synthetic antiferromagnetic (SAF: Synthetic Antiferromagnet) bond. SAF is reported in S. S. Parkin et. Al., Physical Review Letters, 7, May, pp. 2304-2307 (1990).

The magnetized pinned layer 4 is in contact with the antiferromagnetic layer 5, and according to the exchange interaction occurring between these two layers, the magnetized pinned layer 4 has strong magnetic anisotropy. As the material of the antiferromagnetic layer 5, a manganese alloy such as iron, nickel, platinum, iridium, rhodium, or cobalt or nickel oxide can be used.

The magnetization free layer (memory layer) 2 has an easy magnetization axis (direction axis in which the ferromagnetic material is easily magnetized) parallel to the magnetization direction of the magnetization pinned layer 4, and is parallel to the magnetization direction of the magnetization pinned layer 4. Alternatively, it is easy to magnetize in the antiparallel direction, and the magnetization direction can be reversed relatively easily between these two states. Therefore, if the magnetization in two states (which becomes "parallel" and "antiparallel" with respect to the magnetization direction of the magnetization pinned layer 4) corresponds to 0 and 1 indicating information, then the magnetization free layer (memory layer) 2 is It can be used as an information storage medium.

Also, between the magnetization free layer (memory layer) 2 and the magnetization pinned layer 4, a tunnel barrier layer 3 formed of an insulator composed of an oxide, nitride, or the like of aluminum, magnesium, or silicon is inserted. . It breaks the magnetic coupling between the two layers 2 and 4 and plays a role of flowing a tunnel current corresponding to the magnetization direction of the magnetization free layer (memory layer) 2. The magnetic layer and the conductor layer constituting the TMR element 10 are mainly formed by sputtering, and the tunnel barrier layer 3 is formed by oxidizing or nitriding a metal film formed by sputtering.

The top coat layer (1) serves to prevent mutual diffusion between the TMR element 10 and the wiring connected thereto, and to reduce contact resistance and prevent oxidation of the magnetization free layer (memory layer) 2. Usually, the material of copper, tantalum, titanium, or titanium nitride can be used. The lead electrode layer 6 is used for the connection with the switching element connected in series with the TMR element 10. The lead electrode layer 6 also functions as the antiferromagnetic layer 5.

7 is an enlarged perspective view showing a simplified part of a memory section of a general MRAM. The read circuit portion is omitted here for simplicity, and the MRAM has nine memory cells and a bit line 11 and a writing word line 12 that cross each other. Each TMR element 10 is located at an intersection.

8 and 9 show an equivalent circuit diagram of the MRAM. 8 shows the overall configuration, and FIG. 9 is a partially enlarged view thereof. In FIG. 9, six memory cells are shown as an example, but are connected in series with the TMR element 10 together with the TMR element 10 at each intersection point of the bit line 11 and the write word line 12. And a field effect transistor 15 for element selection at the time of reading information is disposed. There is also a read word line 13 for controlling ON and OFF of the field effect transistor 15, and a sense line 14 for outputting the read information. In the peripheral circuit portion, the bit line current driving circuit 16 is connected to the bit line 11, and the bidirectional writing word line current driving circuit 17 is connected to the writing word line 12. The sense line 14 is connected to the sense line 14 for detecting the read information.

10 is a schematic cross-sectional view showing one of memory cells disposed in a memory section of a conventional MRAM. However, in FIG. 10, the interlayer insulating film 40 is shown with the boundary and hatching between the interlayer insulating films omitted for clarity. (The same applies to the following.)

Above the memory cell, the above-described TMR element 10, bit line 11, and writing word line 12 are disposed. The bit line 11 formed on the TMR element 10 is electrically connected to the upper coat layer 1. The write word line 12 is formed under the TMR element 10 with an insulating layer interposed therebetween.

On the other hand, in the p-type well region 21 formed in the p-type silicon semiconductor substrate 20 under the memory cell, the drain electrode 23, the drain region 24, the gate electrode 13, and the gate insulating film 25. And an n-type MOS field effect transistor 15 including a source region 26 and a source electrode 27 are formed. Since the gate electrode 13 of the transistor 15 is an elongated strip connecting cells, the gate electrode 13 also serves as a read word line 13. In addition, the drain electrode 23 is connected to the lead-out electrode layer 6 of the TMR element 10 through the lead-out wiring 7, the read connection plugs 30 and 32, and the read landing pads 31 and 33. The source electrode 27 is connected to the sense line 14. (In the following drawings, the connection plug is abbreviated as a plug, and the landing pad is abbreviated as a land.) According to the illustrated example, the lead wire 7 is shown. Is connected via the read landing pad 31 and the read connection plug 30, but it is also possible to omit the read connection plug 30 so that the lead-out wiring layer is formed directly in the connection hole. Applies).

The memory cell configured as described above is a method of generating a coupling magnetic field in which a current flows through the bit line 11 and the writing word line 12 so that two currents magnetize the magnetization free layer (memory layer) 2. Information is written into the element 10. The magnetization direction is assigned to [parallel] or [antiparallel] according to the magnetization direction of the magnetized pinned layer 4.

The magnetic field in the magnetization free layer (memory layer) 2 of the TMR element 10 is the vector sum of two magnetic fields H _EA and H _HA . The magnetic field H _EA in the easy axis of magnetization direction is applied by the write current flowing through the bit line 11, and the magnetic field H _HA in the hard axis of magnetization direction is applied to the word line 12 for writing. Is applied by a write current flowing through

Writing in the MRAM results in two magnetic fields H _EA (<Hs), H not being large enough to cause magnetization reversal in the memory cell at the intersection of the bit line 11 supplying the current and the word line 12 for writing. _This is done by applying _HA (<Hs) to the memory cell. Therefore, inversion of the magnetic spin occurs only in the memory cell in which the magnetic fields H _HA and H _EA act. This phenomenon is based on the magnetization reversal indicated by the steroid curve. In addition, Hs represents a one-way inversion magnetic field. The principle of the above-described phenomenon is explained in the following. (See US Patent No. 6161445 specification.)

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Fig. 11 is a graph of an steroid curve showing the magnetic field response characteristics of the magnetization free layer (memory layer) 2 of the TMR element during the information writing operation. The steroid curve is expressed by the following equation from the minimum energy condition.
It is represented by H _EA ^2/3 + H _HA ^2/3 = Hs ^2/3 .

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The threshold value of the applied magnetic field for inverting the writing condition of the TMR element, that is, the magnetization direction of the magnetization free layer (memory layer) 2 is shown. Here, the magnitude of the one-way inversion magnetic field Hs depends not only on the shape of the magnetization free layer (memory layer) 2 but also on the material.

As shown in Fig. 11, when the magnetic field H _EA applied in the easy magnetization axis direction is Hx (<Hs) and the magnetic field H _HA applied in the difficult magnetization axis direction is Hy (<Hs), Hx and Hy The magnetization free layer (memory layer) 2 acts by the coupling magnetic field H, which becomes the vector sum, and only this coupling magnetic field H is larger than the threshold Hc corresponding to the point C on the asteroid curve, and the region outside the steroid curve 151. When the size reaches (A) or 152, the magnetization direction of the magnetization free layer (memory layer) 2 can be reversed. On the other hand, when the coupling magnetic field H remains as a vector sum in the region 150 inside the asteroid curve, the magnetization direction of the magnetization free layer (memory layer) 2 cannot be reversed.

When the magnetization direction reversal characteristic described above exists in both the easy magnetization axial magnetic field H _EA and the hard magnetization axial magnetic field H _HA , the magnitude of the magnetic field required for inverting the magnetization direction is smaller than in the case where each acts. If two of the bit line 11 and the word line 12 for writing are used at the same time, it indicates that it is possible to selectively write information only in the TMR element 10 (memory cell) at the intersection of the two lines. .

That is, the write current flowing through the bit line 11 applies Hx (easy magnetization axial magnetic field H _EA ) to all the TMR elements 10 disposed below the bit line 11, and writes the word line ( The write current flowing through 12 applies Hy (non-magnetization axis direction magnetic field H _HA ) to all the TMR elements 10A disposed above the write word line 12. However, when a single magnetic field acts in the easy magnetization axis direction or the hard magnetization axis direction, it is smaller than the threshold of the magnetic field required for magnetization reversal. In this case, the threshold is a value on the X-axis (or easy magnetization axis) or Y-axis (or difficult magnetization axis) of the steroid curve, Hs (or semi-inverted magnetic field). Therefore, even if Hx and Hy smaller than Hs are applied, the magnetization directions of the magnetization free layer (memory layer) 2 cannot be reversed, respectively. However, at the intersection of the bit line 11 and the write word line 12, the write current is coupled above the threshold Hc on the steroid curve (up to the region 151 (A) outside of the steroid curve). Generate a magnetic field (H). Therefore, the memory cell at the intersection is affected by Hx and Hy, and it is possible to reverse the magnetization direction of the magnetization free layer (memory layer) 2 of the memory cell.

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In addition, when Hx or Hy is larger than the one-way inversion magnetic field Hs, information is written into all the memory cells on which it operates. Therefore, Hx and Hy should be less than Hs and should not reach region 152. The gray area 151 (A) shown in FIG. 11 is an area suitable as a coupling magnetic field applied to the magnetization free layer (memory layer) 2 for writing information.

The above fact also applies to a single memory cell. However, the actual magnetization memory device includes a very large number of TMR elements 10 so as to say about 1 million in 1M bit MRAM. These TMR elements are slightly different in characteristics from each other. Therefore, it should be noted that each element has a different threshold shown in the asteroid curve and that the proper area A of the coupling magnetic field applied for writing is different.

FIG. 12 is a graph showing two regions for an appropriate coupling magnetic field applied for writing to the magnetization free layer (memory layer) 2 of two TMR elements 10 having different magnitudes of one-way inversion magnetic field Hs. An appropriate region of the coupling magnetic field for writing information to the TMR element 10 having the one-way inversion magnetic field is Hs1, and an appropriate region of the coupling magnetic field for writing information to the TMR element 10 with the one-way inversion magnetic field is Hs2. If A2 is set, the coupling magnetic field applied to properly write information to these two TMR elements must be in a region where A2 overlaps each other with A1. If a group of memory cells includes TMR elements 10 that differ greatly in one-way inversion magnetic field Hs, the coupling magnetic field capable of accurately driving all TMR elements 10 will be limited to a very narrow range.

13 is a schematic cross-sectional view for explaining the operation of reading information in the TMR element 10. Here, the layer structure of the TMR element 10 is shown schematically, and the upper coat layer 1, the antiferromagnetic layer 5, and the extraction electrode layer 6 are not shown.

Reading of the information recorded in the TMR element 10 is performed using the TMR effect which is one of magnetoresistance effects. The TMR effect is a phenomenon in which resistance to tunnel current flowing between two magnetic layers facing each other with a tunnel barrier layer becomes smaller when the direction of magnetic spin of the two magnetic layers is "parallel", and becomes larger when "antiparallel". to be.

Specifically, it will be described with reference to FIG. Tunnel current flowing from the bit line 11 through the magnetization free layer (memory layer) 2, the tunnel barrier and the magnetization pinned layer 4 flows. Since the read current which varies with the resistance to the tunnel current is derived from the lead electrode layer 6, the magnitude of the read current indicates the direction of the magnetic spin of the magnetization free layer (memory layer) 2.

That is, as shown in the left side of FIG. 13, when the magnetization directions of the magnetization free layer (memory layer) 2 and the magnetization pinned layer 4 are "parallel" with each other, and the magnetic spin is prepared by this, these 2 The resistance between the two layers is small, and a large reading current flows through the tunnel barrier layer 3. On the other hand, as shown in the right side of Fig. 13, the magnetization directions of the magnetization free layer (memory layer) 2 and the magnetization pinned layer 4 are &quot; antiparallel to each other &quot;, whereby the magnetic spins are reversed. The resistance between the two layers is large, and the read current flowing through the tunnel barrier layer 3 is small.

As shown in FIG. 10, the lead electrode layer 6 of the TMR element 10 is used for reading through the lead wire 7, the read connection plugs 30 and 32, and the read landing pads 31 and 32. It is connected to the drain electrode 23 of the transistor 15, and the source electrode 27 of the read transistor 15 is connected to the sense line 14. Therefore, in the read operation of the MRAM, one TMR element is generated by a control signal to the gate electrode (reading word line) 13 of the TMR elements 10 connected to the bit line 11 to which the drive current is applied. (10) is selected. Only the read current of the selected TMR element 10 is output to the sense line 14 through the read field effect transistor 15. In this way, the field effect transistor 15 functions as a switching element for selectively reading out the information stored in the TMR element 10.

Meanwhile, the transistor 15 may be an n-type or p-type field effect transistor, but various switching elements such as diodes, bipolar transistors, and metal semiconductor field effect transistors (MESFETs) may be used.

Fig. 14 is a plan view showing the arrangement of 1M bit MRAM. As shown in FIG. 14, a plurality of memory cells are formed in a memory unit, and peripheral circuits such as control circuits are formed around the memory unit.

Fig. 15 is a plan view showing an example of a conventional memory cell arrangement in MRAM. Two symmetric memory cells form a pair, which is one unit of a plurality of memory cells. One memory cell includes one TMR element 10 and one read (select) transistor. It is a 1T1J type memory cell, and a read connection for connecting the lead wire 7 and the lead wire 7 extending from the lead electrode 6 of the TMR element 10 to the drain electrode of the read transistor (selection). And a plug 30. In addition, a bit line 11 and a writing word line 12 connected to each memory cell are formed. For simplicity, the bottom wiring and the readout (selection) transistors are not shown.

16 is a schematic cross-sectional view showing the arrangement of four memory cells in the MRAM described above. The structure of one memory cell is essentially the same as the memory cell shown in FIG. That is, the above-described TMR element 10, bit line 11, and writing word line 12 are disposed on the memory cell, and the bit line 11 is placed on the TMR element 10. It is formed and electrically connected to the upper coat layer 1 of the TMR element 10, and the word line 12 for writing is formed below the TMR element 10 with an insulating layer interposed therebetween. Below the memory cell is a p-type well region 21 formed in the p-type silicon semiconductor substrate 20. In the p-type well region 21, n including a drain electrode 23, a drain region 24, a gate electrode 13, a gate insulating film 25, a source region 26, and a source electrode 27. A MOS field effect transistor 15 for selecting a type is formed. The gate electrode 13 of the transistor 15 is a long narrow strip connecting cells, and also serves as a read word line 13. In addition, the drain electrode 23 is the lead electrode layer 6 of the TMR element 10 through the lead wire 7, the read connection plugs 30, 32, 34 and the read landing pads 31, 33, 35. ), And the source electrode 27 is connected to the sense line 14. Two memory cells that are symmetrical with each other share the source region 26, the source electrode 27, and the sense line 14.

The outline of the manufacturing process of the memory section of the MRAM shown in Figs. 15 and 16 is as follows.

First, in the p-type well region 21 of the silicon substrate 20, by using a known semiconductor technology, a shallow trench isolation (STI) and a local oxide (LOCOS) which separate the read-out MOS field effect transistor (15) therebetween. an oxide film 22 such as of Silicon.

Next, an insulating film and a lower wiring are formed. In the formation of the word line 12 for writing and the landing pad 31 for reading, a silicon oxide film is deposited as an interlayer insulating film by CVD (Chemical Vapor Deposition) method, a photolithography technique and dry etching. After the interlayer insulating film is patterned by using a thin film of tantalum or tantalum nitride (not shown) as a barrier layer, a sputtering method is formed on the entire surface of the interlayer insulating film, and copper is injected into the wiring grooves and openings by CVD or plating. The surface is planarized by CMP (chemical mechanical polishing) to form a word line 12 for writing and a landing pad 31 for reading. In the formation of the sense line 14, an aluminum thin film is formed by sputtering or vapor deposition, patterned by photolithography and dry etching, and aluminum wiring is formed.

17 and 18 are schematic cross-sectional views showing the flow of a process of producing an upper structure such as the TMR element 10 on the lower wiring layer formed as described above. However, the positions of the components of this cross section are the same as those of the cross section shown in Fig. 16, and for the sake of simplicity, only the upper portion of the interlayer insulating film on which the writing word line 12 and the reading landing pad 31 are formed is shown.

After forming a silicon nitride film (not shown) by the CVD method as a diffusion preventing film for preventing the diffusion of copper ions, as shown in Fig. 17A, a silicon oxide film as the interlayer insulating film 50 is deposited by the CVD method, The openings 51 are formed by patterning by photolithography techniques and dry etching.

Next, as shown in FIG. 17B, a thin film of titanium nitride (not shown) is formed as a barrier layer on the entire surface of the interlayer insulating film 50 by sputtering, followed by tungsten or the like by CVD. To the opening 51. Thereafter, the surface is flattened according to the CMP method, and a read connection plug (tungsten plug) 30 is formed.

Next, as shown in Fig. 17C, a tantalum layer serving as the lead electrode layer 6 and the lead wiring 7, a platinum manganese alloy layer serving as the antiferromagnetic layer 5, and a magnetized pinned layer on the entire surface by the sputtering method. (4) an alloy layer of iron and cobalt, an aluminum oxide layer serving as a tunnel barrier layer (3), an alloy layer of iron, cobalt, and boron serving as a magnetization free layer (coFe-30B), an upper portion The tarium layer used as the coat layer 1 is laminated in order. Thus, each layer which comprises the TMR element 10 is formed, and the tunnel barrier layer 3 is formed by oxidizing or nitriding the metal film formed by sputtering method.

Next, as shown in FIG. 17D, a positive resist layer 52 is formed on the surface by coating, and a resist layer is formed through a photomask 55 having an exposure pattern corresponding to the shape of the TMR element. After exposing (52), it is developed and the resist mask 56 patterned in the shape of a TMR element is formed. As will be described later, if the TMR element patterns are close to each other, the exposure pattern 53 is deformed by the proximity effect, and as a result, the resist mask 56 which is accurately patterned in the shape of the TMR element cannot be formed.

Next, as shown in Fig. 18A, dry etching is performed through the resist mask 56 to form the top coat layer 1 corresponding to the shape of the TMR element.

Next, after removing the resist mask 56, as shown in FIG. 18B, the upper coat layer 1, the tunnel barrier layer 3, the magnetization pinned layer 4, and the antiferromagnetic layer on the storage layer 2 are shown. Since (5) is etched, it is formed in accordance with the shape of the TMR element 10.

Next, as shown in FIG. 18C, a resist mask 57 is formed by photolithography, the lead electrode layer 6 is etched, and the lead electrode layer 6 and lead wires 7 of the TMR element 10 are etched. ). Thereafter, the resist mask 57 is removed.

Next, although not illustrated, the TMR element 10 and the lead-out wiring 7 are embedded because the silicon oxide film serving as the interlayer insulating film 54 is deposited by the CVD method. Next, the bit line 11 which consists of copper or aluminum is formed by the above-mentioned method, and a protective layer is formed on it.

Here, the lead wire 7 is connected to the reading landing pad 31 via the read connection plug 30. However, in such a structure, the step of forming the read connection plug 30 shown in Fig. 17B is omitted, and it is also possible for the lead-out wiring 7 to be formed directly on the opening 51.

In any case, a connection hole for connecting the TMR element 10 with the adjacent read transistor 15 is required. On the other hand, generally, the surface shape of the periphery of the connection holes is not flat, which hinders in forming the planar shape of the TMR element 10. Therefore, in order to form the planar TMR element 10, all the connection holes in the periphery of the TMR element 10 instead of the connection holes such as the specific read connection plug 30 formed in the vicinity of the TMR element 10 or the like. It is preferred that they are arranged uniformly and apart.

As described above, an MRAM using a TMR element has a characteristic of being a nonvolatile RAM having a simple structure and capable of high-speed writing by reversing the magnetic moment, but using a large-capacity (highly integrated) memory at a high product ratio. In order to realize the MRAM and put it into practical use, it is necessary to suppress the gap between the write and read characteristics of the TMR element so that the write and read operations can be performed with a wide margin.

Regarding the read characteristics, in each TMR element constituting the memory cell, the junction area (projection area) of the tunnel barrier layer inserted between the magnetization free layer (memory layer) and the magnetization pinned layer is made uniform, There is an effect of reducing the change of, thereby suppressing the difference in resistance value, thereby improving the yield.

19 is a graph showing an example of the distribution of the read resistance of the TMR element. In the case where the difference between the average resistance value in the zero state and the average resistance value in the one state is the same, if the dispersion width of the read resistance is suppressed, the operation margin can be increased and the yield can be high. In addition, in the case of the same design margin, the TMR element will further increase the signal voltage and enable high speed operation.

On the other hand, one method of improving the write characteristics is to suppress the dispersion width of the unidirectional inverting field Hs of each TMR element 10 constituting the memory cell, which is necessary for realizing a large capacity memory. As described using the asteroid characteristic of FIG. 12, when the dispersion width of Hs is large, the range of the coupling magnetic field applied for writing of the TMR element is narrowed, and thus, it is included in one MRAM device due to the narrow range of the coupling magnetic field as shown in FIG. 20. It becomes impossible to write stably to all the TMR elements that have been used, and a large capacity memory cannot be realized.

The magnitude of the one-way inversion magnetic field Hs is mainly determined by the shape anisotropy of the magnetization free layer (memory layer) 2 if the material of the magnetization free layer (memory layer) 2 is the same, so that the dispersion width is suppressed. To do this, it is important to control the area of the magnetization free layer (memory layer) 2 of the TMR element 10 and its shape aspect ratio (aspect ratio).

Therefore, in the manufacturing process of the memory cell of the conventional MRAM, the patterning process of the resist layer 52 by photolithography shown in FIG. 17D is particularly important. Since the exposure pattern 53 formed in this step determines the pattern of the resist mask 56 after development, the shape of the TMR element 10 is formed by etching using the resist mask 56, which is inaccurate. This is because the patterning process makes the TMR element 10 having an incorrect shape.

However, the above description is not sufficiently considered with respect to the arrangement of the conventional memory cell shown in FIG. That is, the arrangement shown in FIG. 15 constitutes a pair of two symmetrical memory cells, with the result that the TMR elements 10 are arranged at equal intervals as schematically shown in FIG. 21 showing only the TMR element 10. Although not shown, the two sets of TMR elements are arranged adjacent to each other. When the two mask patterns are arranged in this manner, a problem arises in that the resist mask pattern 56 is deformed due to the proximity effect between the exposure patterns 53 generated by scattering of the irradiated light. Since such deformation can easily occur in the resist pattern 56 corresponding to two adjacent TMR elements, the shape of the TMR element formed from these resist mask patterns tends to be irregular.

Deformation due to the proximity effect can be corrected according to the Optical Proximity Correction (OPC) method. However, in the case of an element arranged in a two-dimensional pattern shape such as the TMR element 10 and sensitive to writing and reading characteristics, The correction is insufficient. Further, in processing the TMR element 10, the planar shape of the TMR element 10 is masked not only by the proximity effect but also by the loading effect of dry etching and the shadow effect at the time of ion milling. There is also a problem that the variation in the pattern and the resist pattern results in a larger gap in the one-way inversion magnetic field.

The present invention has been invented in view of the above circumstances, and an object thereof is to provide a large capacity solid state memory device such as an MRAM having a small gap between the write characteristics and the read characteristics in the information storage portion. The memory device is a product that can be produced with high reliability and high yield. This object is achieved by manufacturing a resist mask pattern corresponding to the information storage portion in order to keep the deformation uniform.

The present invention relates to a solid state memory device disposed two-dimensionally in an information storage portion, wherein the arrangement refers to a pattern corresponding to translational symmetry, and the present invention also relates to an arrangement method of a solid state memory cell. do.

According to the present invention, the information storage portion is arranged so as to correspond to the pattern of translational symmetry. That is, the information storage portion and its peripheral portions are arranged to be identical throughout the entire array. The structure arranged in this manner prevents the proximity effect from occurring in a specific portion in the lithography process of producing a resist mask pattern corresponding to the shape of the information storage portion.

According to the present invention, the proximity effect occurring in the lithography process occurs uniformly in the resist mask pattern corresponding to each of the information storage portions. In addition, also in the subsequent fabrication process, the loading effect by dry etching and the shadow effect by ion milling also appear uniformly in each of the information storage portions, so that the difference in shape of the information storage portion is suppressed. As a result, uniform write characteristics and read characteristics are obtained in the information storage portion, whereby a highly reliable, large capacity solid state memory device can be effectively produced.

The present invention is applied to a magnetic memory device in which a magnetic memory element having a stack of a magnetized pinned layer having a fixed magnetization direction, a tunnel barrier layer, and a magnetized free layer having a changed magnetization direction as the information storage portion is arranged. In the DRAM (Dynamic Random Access Memory) having a capacitor driven by a metal oxide semiconductor (MOS) transistor as the information storage portion, the capacitor is formed in the same lithography process, and thus the same effect can be obtained. The same applies to the case of static random access memory (SRAM), ferroelectric random access memory (FRAM), read only memory (ROM), programmable ROM (PROM), erasable and programmable ROM (EPROM).

The present invention can be applied to MRAM which becomes a high speed, nonvolatile high capacity memory which is indispensable in the era of ubiquitous computing. MRAMs are suitable for portable terminals of all kinds of electronic equipment, especially personal communication equipment requiring high integration, high speed and low power consumption.

The above and other objects, features and advantages of the present invention will become apparent from the accompanying claims and the description taken in conjunction with the accompanying drawings.

The present invention relates to a magnetic memory device comprising an array of magnetic memory elements each including a stack comprising a magnetization pinned layer having a fixed magnetization direction, a tunnel barrier layer, and a magnetization free layer capable of changing the magnetization direction. When applied to the best effect. The laminate is driven by a first wiring electrically connected to the laminate and a second wiring electrically insulated from the laminate. In the magnetic memory element, the effect of the present invention is obtained based on the fact that the write characteristics and the read characteristics are sensitive to the two-dimensional pattern shape of the laminate.

According to this invention, it is preferable that the pattern of a laminated body has a line symmetry axis | shaft, and the laminated bodies adjacent to each other are arrange | positioned so that it may become symmetrical with respect to the said line symmetry axis | shaft.

In addition, two laminated bodies which adjoin each other should be arrange | positioned by half pitch shift in the direction along one of the 2nd wiring. The effect of such an arrangement is that, as described with reference to the drawings of Embodiment 2, the connection holes and the like formed around the magnetic memory elements can be arranged uniformly from the magnetic memory elements, and are formed by the electric connection holes and the like. It is possible to maximally protect the magnetic memory device from being affected by irregular surface shapes.

Further, the first wiring and the second wiring are orthogonal to each other, and the pattern of the laminate has a line symmetry axis, and the line symmetry axis is arranged so as to intersect at 0 degrees, 90 degrees, 180 degrees, and 270 degrees with respect to the first or second wiring. It is preferable that it is done. In this way, toggle mode writing can be performed on the magnetic memory device. Toggle mode writing does not need to reverse the direction of the write current, which simplifies and speeds up the drive circuit. In addition, since the write wiring and the read wiring can be formed independently of each other, it becomes possible to perform writing and reading almost independently.

At this time, since the pattern of the connection hole for connecting the lead-out wiring of the laminated body with the lower layer wiring also has a line symmetry axis, the connection holes adjacent to each other are arranged so as to be symmetrical with respect to the line symmetry axis. This will have the same effect as the above-described effect. That is, since the connection holes formed around the magnetic memory element are uniformly spaced apart from the magnetic memory element, the shape of the magnetic memory element can be protected as much as possible from the irregular surface shape formed by the connection hole. have.

A dummy pattern having the same shape as that of the laminate should be formed outside the arrangement region of the laminate. In this case, since the laminate located at the outermost side of the array is also completely surrounded by the laminate as the laminate inside the array, the laminate at the outermost side of the array under the same conditions as the laminate inside the array. Can be formed.

It is preferable that the MRAM which concerns on this invention is comprised as follows. The magnetization free layer and the magnetization pinned layer are separated by a tunnel barrier layer interposed therebetween. In a particular direction, information is written by magnetizing the magnetization free layer. This magnetization is made by a magnetic field caused by a current flowing through the bit line as the first wiring and the write word line as the second wiring, respectively. This written information is read using the tunnel magnetoresistive effect generated by the tunnel barrier layer. This is a standard configuration of the MRAM.

In another preferred pattern of the arrangement, the information storage portions have a planar pattern having a line symmetry axis, and the information storage portions adjacent to each other are symmetrical about the line symmetry axis.

In another preferred pattern of the arrangement, the information storage portions adjacent to each other are arranged so that one of them is shifted by a half pitch in the direction of the wiring.

In another preferred pattern of arrangement, the information storage portions have a linear symmetry axis, and the information storage portions adjacent to each other are arranged inclined with respect to the linear symmetry axis at 0 degrees, 90 degrees, 180 degrees, and 270 degrees.

In another preferred pattern of the arrangement, a dummy pattern having the same shape as the information storage portion is formed outside the arrangement area of the information storage portion.

Preferred embodiments of the present invention will be specifically described with reference to the drawings. Embodiments 1 to 4 of the following embodiments are cases where the solid state memory device is a magnetic memory device (MRAM).

Embodiment 1

1 is a plan view showing the arrangement of memory cells in a magnetic memory device (MRAM) according to the first embodiment. This magnetic memory device is comparable to the MRAM of the conventional example shown in FIG. As in FIG. 15, for simplicity, FIG. 1 omits read (selection) transistors and wirings formed in the lower layer.

In the MRAM shown in Fig. 1, the conventional MRAM shown in Fig. 15 is characterized in that each memory cell is a 1T1J type memory cell including one TMR element 10 and one read (selection) transistor. same. Each memory cell has a lead wire 7 extending from the lead electrode 6 of the TMR element 10 and a read connection plug for connecting the lead wire 7 to the drain electrode of the read (select) transistor ( 30). In addition, each memory cell includes a bit line 11 and a writing word line 12 connected to each memory cell.

The difference is in the arrangement of the memory cells. In the conventional example MRAM shown in Fig. 15, a plurality of memory cells are arranged such that one pair of left and right symmetric memory cells constitute one unit. In contrast, in the MRAM shown in FIG. 1, since a plurality of memory cells are arranged at equal intervals in the horizontal direction and the vertical direction, each memory cell constitutes one unit. That is, the array has a pattern of translational symmetry.

As shown in Fig. 1, in the MRAM of the present embodiment, the relationship between one TMR element and the TMR element surrounding it is arranged so as to be the same for all TMR elements. Therefore, the proximity effect is the same for all TMR elements, whereby the change can be reduced.

The above description does not apply to the TMR element 10 positioned at the outermost side of the array, and there is no TMR element 10 surrounding the TMR element 10 outside thereof. This problem is solved by forming a dummy pattern of the same shape as the TMR element 10 on the outside of the arrangement region. As a result, the TMR element 10 positioned at the outermost side of the array is also surrounded by the TMR element 10 and the dummy element 10b, similarly to the TMR element 10 inside the array. It may be formed under the same conditions as for the TMR element 10. In addition, the arrangement shown in FIG. 1 is arranged on the assumption that dummy elements 10b are arranged on the top and right sides of the arrangement.

2 is a schematic cross-sectional view showing an arrangement relationship of four memory cells in the above-described MRAM.

The components of each memory cell are the same as the conventional memory cell shown in FIG. In other words, the above-described TMR element 10, bit line 11, and writing word line 12 are disposed above the memory cell. The bit line 11 is formed on the TMR element 10 and is electrically connected to the upper coat layer 1 of the TMR element 10. The write word line 12 is formed under the TMR element 10 with an insulating layer interposed therebetween. Below the memory cell is a p-type well region 21 formed in the p-type silicon semiconductor substrate 20. The p-type well region 21 includes an n-type composed of a drain electrode 23, a drain region 24, a gate electrode 13, a gate insulating film 25, a source region 26, and a source electrode 27. MOS field effect transistor 15 is formed. The gate electrode 13 of the transistor 15 is an elongated strip which also serves as a read word line 13 and connects the memory cells. The drain electrode 23 is connected to the lead electrode layer 6 of the TMR element 10 through the lead wire 7, the read connection plugs 30, 32, 34, and the read landing pads 31, 33, 35. Connected. The source electrode 27 is connected to the sense line 14.

The TMR element 10 has a structure shown in FIG. 6 as in the conventional example. The TMR element 10 is formed on the support substrate 8 (here, the interlayer insulating film), and the magnetization free layer (memory layer) 2 whose magnetization direction is relatively easily reversed and the magnetization direction are fixed. The fixed layer 4 is included. As the magnetization free layer (memory layer) 2 and the magnetization pinned layer 4, a ferromagnetic material mainly containing nickel, iron, cobalt, or an alloy thereof is used. The magnetized pinned layer 4 should be a multilayer film (lamination film composed of ferromagnetic material / metal / ferromagnetic material) having a synthetic antiferromagnetic (SAF) bond.

The magnetized pinned layer 4 is formed in contact with the antiferromagnetic layer 5, and these two layers generate exchange interactions, whereby the magnetized pinned layer 4 has strong magnetic anisotropy. As the material of the antiferromagnetic layer 5, manganese alloys such as iron, nickel, platinum, iridium and rhodium, or cobalt or nickel oxide can be used.

The magnetization free layer (memory layer) 2 has an easy magnetization axis (direction axis in which the ferromagnetic material is easily magnetized) parallel to the magnetization direction of the magnetization pinned layer 4, and is parallel to the magnetization direction of the magnetization pinned layer 4. Alternatively, since it is easy to magnetize in the antiparallel direction, the magnetization direction can be reversed relatively easily between these two states. Therefore, if two magnetization states ("parallel" and "antiparallel" with respect to the magnetization direction of the magnetization pinned layer 4) correspond to "0" and "1" indicating information, the magnetization free layer (memory layer) 2 ) Can be used as an information storage medium.

In addition, between the magnetization free layer (memory layer) 2 and the magnetization pinned layer 4, a tunnel barrier layer 3 formed of an insulator composed of an oxide, nitride, or the like of aluminum, magnesium, or silicon is interposed therebetween. have. The layer breaks the magnetic coupling between the magnetization free layer (memory layer) 2 and the magnetization pinned layer 4, and plays a role of flowing tunnel current along the magnetization direction of the magnetization free layer (memory layer) 2. have. The magnetic layer and the conductor layer constituting the TMR element 10 are mainly formed by the sputtering method, and the tunnel barrier layer 3 is formed by oxidizing or nitriding a metal film formed by the sputtering method.

The upper coat layer 1 prevents mutual diffusion prevention between the TMR element 10 and the wiring connected to the TMR element 10, and reduces contact resistance and prevents oxidation of the magnetization free layer (memory layer) 2. It is usually used, and materials such as copper, tantalum, titanium or titanium nitride can be used. The lead electrode layer 6 is used for connection with a switching element connected in series with the TMR element 10, and the lead electrode layer 6 can function as the antiferromagnetic layer 5.

The difference between the conventional memory cell shown in FIG. 16 and the above-described memory cell is that one memory cell is provided because two adjacent memory cells share the source region 26, the source electrode 27, and the sense line 14. Read landing pad 33 serves as a read wiring 33b for another memory cell.

In the MRAM shown in Fig. 2, it is assumed that the three-layer metal wiring performs the basic function of the MRAM cell arrangement, but like the MRAM shown in Fig. 15, it has a four-layer wiring process. This is because four or more layers of metal wiring are used for the high-speed memory circuit or the logic circuit of the device according to the latest design rule for 0.18 μm.

In Fig. 16 of the conventional example, it can be seen from Figs. 2 and 16 that the bottom and the top are also composed of one set of symmetric memory cells. The lower symmetry structure was adopted to simplify the wiring, whereby the upper TMR element 10 is also arranged in a symmetrical pattern. On the contrary, in the present embodiment, the read landing pad 33b is formed in the memory cell, and the read landing pad 33b allows the lower structure to have a symmetrical structure in which wiring can be simplified as in the prior art. It becomes However, the arrangement of the upper part is changed to a structure having a pattern of translational symmetry, whereby the left and right symmetry is most suitable for the lower structure, and the translational symmetry is most suitable for the upper structure.

Embodiment 2

3 is a plan view showing the arrangement of memory cells in the magnetic memory device (MRAM) according to the second embodiment.

Like the MRAM of Embodiment 1 shown in FIG. 1, in the MRAM shown in FIG. 3, each memory cell includes a 1T1J type including one TMR element 10 and one read (selection) transistor. Is a memory cell. Each memory cell has a read connection plug 30 for connecting the lead wire 7 extending from the lead electrode 6 of the TMR element 10 and the lead wire 7 to the drain electrode of the read transistor (selection). It also includes. In addition, it includes a bit line 11 and a writing word line 12 connected to each memory cell. As shown in FIG. 1, FIG. 3 omits the wiring and the readout (selection) transistor formed in the lower layer for the sake of simplicity.

This embodiment differs from the first embodiment in terms of arrangement. In the arrangement of Embodiment 1, the TMR elements 10 in all columns are arranged at the same position as the direction of the write word line 12. However, in the second embodiment, the TMR elements 10 in the columns of the write word line 12 are formed such that the TMR elements in one column are arranged at a half pitch shift from the elements in the adjacent columns.

The arrangement of Embodiment 1 is formed such that the TMR elements 10 in one column are aligned with the TMR elements in adjacent columns in the direction of the write word line 12. As a result, the memory cell read connection plug 30 in the left column is disposed close to the TMR element 10 in the right column. As described above, in the region where the read connection plug 30 is formed, the surface state is frequently damaged, so in the arrangement of Embodiment 1, the damaged surface state easily affects the TMR element 10.

In contrast, in the arrangement of Embodiment 2, since the TMR elements 10 in one column are shifted by half pitch from the TMR elements in adjacent columns in the direction of the write word line 12, the read connection of the memory cells in the left column is performed. The plug 30 is arranged to be separated from the TMR element 10 in the right column. For this reason, in the arrangement of Embodiment 2, there is a benefit that the TMR element 10 is less affected by the damaged surface in the region where the read connection plug 30 and the like are formed.

The other advantage of Embodiment 2 is the same as that of Embodiment 1. In other words, the relationship between one TMR element and its surrounding TMR elements is arranged to be equal for all TMR elements. Therefore, since the proximity effect is uniform for all TMR elements, the change is reduced.

In addition, although abbreviate | omitted in FIG. 3, it is preferable to form the dummy pattern of the same shape as the TMR element 10 in the outer side of the memory cell arrangement area. Therefore, the TMR element 10 located at the outermost side of the array can also be formed under the same conditions as the TMR element 10 inside the array.

Embodiment 3

4 is a plan view showing the arrangement of memory cells in the magnetic memory device (MRAM) according to the third embodiment.

Like the MRAM of Embodiment 1 shown in FIG. 1, in the MRAM shown in FIG. 4, each memory cell includes a 1T1J type including one TMR element 10 and one read (selective) transistor. Is a memory cell. Each memory cell has a lead wire 7 extending from the lead electrode 6 of the TMR element 10 and a read connection plug 30 for connecting the lead wire 7 to the drain electrode of the read (select) transistor. ). In addition, each memory cell includes a bit line 11 and a writing word line 12 connected to each memory cell. As shown in FIG. 1, FIG. 4 omits the wiring and the readout (selection) transistor formed in the lower layer for the sake of simplicity.

The difference between Embodiments 1 and 3 lies in the arrangement method. In the arrangement of Embodiment 1, the elongated axis of the pattern of the TMR elements 10 is oriented to intersect the bit line 11 at right angles, and in the arrangement of Embodiment 3, the TMR elements 10 The long axis of the pattern is oriented so as to be inclined 45 degrees with respect to the direction of the bit line 11 and the direction of the word line 12 for writing. The orientation of the TMR element 10 is a structure that enables the toggle mode writing disclosed in US Patent 6543906.

In the TMR element 10 used in the toggle mode, a three-layered magnetization free layer (ferromagnetic layer / antiferromagnetic coupling layer / ferromagnetic layer laminated film) of SAF is provided, and the upper ferromagnetic layer and the lower ferromagnetic layer are mutually different. In the reverse direction, it is formed to magnetize with a nearly balanced force. The magnetization direction of the lower layer in contact with the tunnel barrier layer is read as information. Toggle mode writing prevents the write current direction inversion in order to simplify the driving circuit and speed up the writing.
In addition, since the write wiring and the read wiring can be formed independently, it is possible to perform writing and reading almost independently.

Other features are the same as those in the first embodiment. That is, since the relationship between one TMR element and the TMR element in the vicinity thereof is arranged to be equal for all TMR elements, the proximity effect becomes uniform for all TMR elements, and the change is reduced.

Although not shown in FIG. 4, it is preferable that a dummy pattern having the same shape as the TMR element 10 is formed outside the array region of the memory cell. In this way, the TMR element 10 positioned at the outermost side of the array can also be formed under the same conditions as the TMR element 10 inside the array.

Embodiment 4

FIG. 5 is a plan view showing the arrangement of memory cells in a magnetic memory device (MRAM) according to the fourth embodiment.

Like the MRAM of Embodiment 3 shown in Fig. 4, in the MRAM shown in Fig. 5, each of the memory cells is of the type 1T1J including one TMR element 10 and one read (selection) transistor. Read connection plug 30 which is a memory cell and connects the lead wire 7 extending from the lead electrode 6 of the TMR element 10 and the lead wire 7 to the drain electrode of the read transistor (selection). Each memory cell includes a bit line 11 and a writing word line 12 connected to each memory cell. As shown in FIG. 1, FIG. 5 omits the wiring and the readout (selection) transistor formed in the lower layer for the sake of simplicity.

A feature of Embodiment 3 is that the elongated axis of the pattern of the TMR element 10 is oriented so as to be inclined at 45 degrees with respect to the direction of the bit line 11 and the writing word line 12. Therefore, the TMR element 10 is capable of toggle mode writing.

The MRAM shown in FIG. 5 has better symmetry than the MRAM of Embodiment 3 shown in FIG. In FIG. 5, a chain line (auxiliary line) is shown for clarity of pattern symmetry. In the MRAM shown in FIG. 4, the positional relationship between the TMR element 10 and its adjacent TMR element 10 is the same for all TMR elements 10 in the cell array, but two adjacent elements are elongated axes of the bit pattern. It is not symmetric about. Therefore, there is a possibility that the resist pattern becomes asymmetric with respect to the long axis. In this embodiment, all the TMR elements 10 are symmetrical about the long and short axes of the bit pattern, and the proximity effect is uniform for all the elements, thereby forming a pattern with better symmetry. As a result, the gap between the TMR elements 10 is improved, and an MRAM device in which symmetrically arranged TMR elements 10 that can easily control characteristics can be formed.

Other features are the same as those in the first embodiment. That is, since the relationship between one TMR element and its surrounding TMR elements is arranged to be equal for all TMR elements, the proximity effect becomes uniform for all TMR elements, and the gap is improved.

Although not shown in FIG. 5, it is preferable that a dummy pattern having the same shape as the TMR element 10 is formed outside the array area of the memory cell. In this way, the TMR element 10 positioned at the outermost side of the array can also be formed under the same conditions as the TMR element 10 inside the array.

As mentioned above, although this invention was demonstrated based on embodiment, it cannot be overemphasized that this invention is not limited to this example and can be suitably changed in the range which does not deviate from the main point of invention.

According to the present invention, the information storage portion is arranged so as to correspond to the pattern of translational symmetry. That is, the information storage portion and its peripheral portions are arranged to be identical throughout the entire array. The structure arranged in this manner prevents the proximity effect from occurring in a specific portion in the lithography process of producing a resist mask pattern corresponding to the shape of the information storage portion.

According to the present invention, the proximity effect occurring in the lithography process occurs uniformly in the resist mask pattern corresponding to each of the information storage portions. In addition, also in the subsequent fabrication process, the loading effect by dry etching and the shadow effect by ion milling also appear uniformly in each of the information storage portions, so that the difference in shape of the information storage portion is suppressed. As a result, uniform write characteristics and read characteristics are obtained in the information storage portion, whereby a highly reliable, large capacity solid state memory device can be effectively produced.

The present invention is applied to a magnetic memory device in which a magnetic memory element having a stack of a magnetized pinned layer having a fixed magnetization direction, a tunnel barrier layer, and a magnetized free layer having a changed magnetization direction as the information storage portion is arranged. In the DRAM (Dynamic Random Access Memory) having a capacitor driven by a metal oxide semiconductor (MOS) transistor as the information storage portion, the capacitor is formed in the same lithography process, and thus the same effect can be obtained. The same applies to the case of static random access memory (SRAM), ferroelectric random access memory (FRAM), read only memory (ROM), programmable ROM (PROM), erasable and programmable ROM (EPROM).

The present invention can be applied to MRAM which becomes a high speed, nonvolatile high capacity memory which is indispensable in the era of ubiquitous computing. MRAMs are suitable for portable terminals of all kinds of electronic equipment, especially personal communication equipment requiring high integration, high speed and low power consumption.

Claims (14)

In a solid state memory device in which information storage portions are arranged two-dimensionally, The solid state memory device is composed of memory cells, Each of the memory cells, A 1T1J type memory cell including one TMR element 10 and one read (select) transistor, Each of the memory cells, A lead wire 7 extending from the lead electrode 6 of the TMR element 10, A read connection plug 30 that connects the lead wire 7 to the drain electrode of the read (selection) transistor, and A bit line 11 and a write word line 12 connected to the respective memory cells, And said array is formed in a pattern having translational symmetry. The method of claim 1, It consists of an arrangement of magnetic memory elements each having a magnetization fixed layer having a fixed magnetization direction, a tunnel barrier layer, and a magnetization free layer capable of changing the magnetization direction as the information storage portion, and electrically connected to the laminate. A solid state memory device configured as a magnetic memory device in which the laminate is driven by a first wiring and a second wiring electrically insulated from the laminate. 3. The method of claim 2, Since the pattern of the stack has a line symmetry axis, the stacks adjacent to each other are arranged so as to be symmetrical with respect to the line symmetry axis. 3. The method of claim 2, And one of the adjacent stacks is disposed half-pitch shifted in the direction along the second wiring with the other of the adjacent stacks. 3. The method of claim 2, The first wiring and the second wiring are orthogonal to each other, and the pattern of the laminate has a line symmetry axis, and the line symmetry axis is at an angle of 0 degrees, 90 degrees, 180 degrees, and 270 degrees with the first or second wiring. Solid memory devices arranged to intersect. The method of claim 5, And a connecting hole for connecting the lead-out wiring of the laminate with the lower layer wiring, and is arranged in a pattern having a line symmetry axis, and connecting holes adjacent to each other are symmetrical with respect to the line symmetry axis. 3. The method of claim 2, And an array area of the stack is surrounded by a dummy pattern having the same shape as the stack. 3. The method of claim 2, The tunnel barrier layer is inserted between the magnetization pinned layer and the magnetization free layer, and the magnetic field caused by the current flowing through the first wiring serving as a bit line and the second wiring serving as a writing word line. And magnetize the magnetization free layer for writing information, and read write information using the tunnel magnetoresistive effect by the tunnel barrier layer. The method of claim 1, And the information storage portion has a planar pattern having a linear symmetry axis, and the information storage portions adjacent to each other are arranged so as to be symmetrical with respect to the linear symmetry axis. The method of claim 1, One of the adjacent stacks is disposed in a half pitch shift in the direction along the wiring of the other of the adjacent stacks. The method of claim 1, And the information storage portion has a planar pattern having a line symmetry axis, and the line symmetry axis is disposed so as to be inclined at 0 degrees, 90 degrees, 180 degrees, and 270 degrees with respect to the wiring. The method of claim 1, And an array area of the information storage portion is surrounded by a dummy pattern having the same shape as the information storage portion. In the two-dimensional arrangement method of the information storage portion in a solid state memory device, And the arrangement is a pattern having a translational symmetry. The method of claim 13, The stack consists of magnetic elements each having a magnetization fixed layer having a fixed magnetization direction, a tunnel barrier layer, and a magnetization free layer capable of changing the magnetization direction as the information storage portion, and electrically connected to the stack. A method of arranging information storage portions in a solid state memory device in which the laminate is driven by a first wiring and a second wiring electrically insulated from the laminate.

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