US20020084500A1

US20020084500A1 - Magnetic random access memory and method for manufacturing the same

Info

Publication number: US20020084500A1
Application number: US10/026,531
Authority: US
Inventors: Chang-Yong Kang; Chang-Suk Kim
Original assignee: Hynix Semiconductor Inc
Current assignee: SK Hynix Inc
Priority date: 2000-12-28
Filing date: 2001-12-27
Publication date: 2002-07-04
Also published as: US6542398B2; US20020097599A1; TW521397B; JP4298196B2; KR20020054656A; JP2002280527A; KR100390978B1

Abstract

A magnetic random access memory (RAM) is implemented by a gate electrode formed on an active region in a semiconductor substrate and being a word line used as a write line, a ground line formed in one side of the word line, a lower lead layer formed in the other side of the word line, a seed layer connected to the lower lead layer and overlapped with the word line, a magnetic tunnel junction (MTJ) cell made on the seed layer and located in an upper portion of the word line and an upper lead layer being a bit line formed connected to the MTJ cell.

Description

FIELD OF THE INVENTION

The present invention relates to a magnetic random access memory (RAM); and, more particularly, to a magnetic RAM having the characteristics of a non-volatile memory such as a flash memory, a faster speed than a static RAM and integration identical to that of a dynamic RAM, and a method for manufacturing the magnetic RAM.

BACKGROUND OF THE INVENTION

Most semiconductor memory manufacturing companies are developing a magnetic RAM using ferromagnetic materials as one of the next generation of memory devices.

The magnetic RAM is a memory device that is manufactured by forming a multi-layer of ferromagnetic thin films and reads and writes information by detecting a current variation according to the magnetization direction of each thin film. Therefore, the magnetic RAM can achieve high speed, low power and high integration by using unique characteristics of a magnetic film, and can perform the operation of a non-volatile memory, e.g., a flash memory.

The magnetic RAM employs a method for implementing a memory device by utilizing the spin polarization magnetic permeation phenomenon or the colossal magnetoresistance (CMR) effect caused by the spin having a substantial influence on the propagation phenomenon of an electron.

The magnetic RAM implements a CMR magnetic memory device by using a phenomenon in which there is a big difference between the resistance when the spin directions of two magnetic layers are identical to each other, the two magnetic layers including a non-magnetic layer therebetween, and the resistance when the spin directions of the two magnetic layers are different from each other.

The magnetic RAM using the spin polarization magnetic permeation phenomenon embodies a magnetic permeation junction memory by utilizing a phenomenon in which the current permeation well occurs in the case in which the spin directions of two magnetic layers are identical to each other, the two magnetic layers including a dielectric layer therebetween, compared to the case in which the spin directions of the two magnetic layers are different from each other.

However, research on the magnetic RAM is in the early stage and mainly concentrated on the formation of a multi-layer of magnetic thin films. Therefore, research on a unit cell structure and peripheral detecting circuits is deficient.

Referring to FIG. 1, there is shown a cross-sectional view of a conventional magnetic RAM.

A

gate electrode

33, i.e., a first word line, is formed on the top of a semiconductor substrate 31.

Next, source/

drain junction regions

35 a and 35 b are formed inside the semiconductor substrate 31 on both sides of the first word line 33 and there are formed a ground line 37 a and a first conductive layer 37 b connected to the source/

drain junction regions

35 a and 35 b, respectively. At this time, the ground line 37 a is generated in the process of making the first conductive layer 37 b.

Subsequently, there are formed a first

layer insulating film

39 for planarization of the top surface of an intermediate product and a first contact plug 41 exposing the first conductive layer 37 b.

There is patternized a

lower lead layer

43 which is a second conductive layer and connected to the first contact plug 41.

A second layer

insulating film

45 is formed to planarize the top surface of the intermediate product and, then, there is formed a second word line being used as a write line 47 on the top of the second layer insulating film 45.

To planarize the top surface of the intermediate product including the

write line

47, a third layer insulating film 48 is constructed thereafter.

A

second contact plug

49 is formed exposing the second conductive layer 43.

Next, there is formed a

seed layer

51 attached to the second contact plug 49. At this time, the seed layer 51 is made covering an upper portion of the second contact plug 49 and that of the write line 47.

Subsequently, a magnetic tunnel junction (MTJ)

cell

100 is formed by sequentially stacking an antiferromagnetic layer (not shown), a pinned ferromagnetic layer 55, a tunnel junction layer 57 and a free ferromagnetic layer 59. The MTJ cell 100 has a pattern size identical to that of the write line 47 and is aligned with the write line 47.

Herein, the antiferromagnetic layer plays a role of keeping the magnetization direction of the pinned ferromagnetic layer unchanged, so that the magnetization direction of the pinned ferromagnetic layer 55 is fixed in one direction. Meanwhile, the free ferromagnetic layer 59 can store “0” or “1” information according to its magnetization direction when its magnetization direction is changed by an external magnetic field.

Finally, after forming a fourth

layer insulating film

60 to planarize the top surface of the intermediate product and expose the free ferromagnetic layer 59, a bit line 61 is formed thereon.

Hereinafter, there will be described the structure and operation of the magnetic RAM with reference to FIG. 1.

A unit cell of the magnetic RAM comprises a field effect transistor including the

first word line

33 being used as a read line used in reading information, the MTJ cell 100, the second word line 47 being used as a write line determining the magnetization direction of the MTJ cell 100 by forming an external magnetic field through the use of the current provided thereto and the bit line 61 being an upper lead layer for detecting the magnetization direction of the free ferromagnetic layer 59 by supplying the current in a direction perpendicular to the MTJ cell 100.

In the operation of reading information stored in the

MTJ cell

100, the magnetization direction of the free ferromagnetic layer 59 is checked by providing a voltage to the first word line 33 to actuate the field effect transistor and detecting an amplitude of the current flowing through the MTJ cell 100 when supplying the current to the bit line 61.

In the operation of writing information in the

MTJ cell

100, the magnetization direction of the free ferromagnetic layer 59 is controlled by using a magnetic field caused by providing the current to the bit line 61 and the second word line 47 in a condition of maintaining the field effect transistor turned off.

Herein, the reason that the current is supplied to both the

bit line

61 and the write line 47 at the same time is that a large magnetic field is induced at a point where two metal lines are perpendicularly crossed, so that it is possible to select one cell from several cell arrays.

There will be explained the operation of the

MTJ cell

100 within the magnetic RAM herein below.

First of all, a tunneling current flows through a

dielectric layer

57 when the current flows in a direction perpendicular to the MTJ cell 100.

The tunneling current becomes larger if the magnetization direction of the free

ferromagnetic layer

59 is identical to that of the pinned ferromagnetic layer 55. On the other hand, if the magnetization direction of the free ferromagnetic layer 59 is different from that of the pinned ferromagnetic layer 59, the tunneling current becomes smaller. This is called a tunneling magnetoresistance (TMR) effect.

The information stored in the

MTJ cell

100 can be detected by detecting the magnetization direction of the free ferromagnetic layer 59 by sensing the amplitude of the tunneling current due to the TMR effect.

As described above, the conventional magnetic RAM has problems with the complexity of a manufacturing process caused by a lot of processes and a laminated structure, and the deterioration of the productivity of devices due to an increased cell size, so that it is difficult to achieve the large scaled integration of semiconductor devices.

SUMMARY OF THE INVENTION

It is, therefore, a primary object of the present invention to provide a magnetic RAM capable of achieving large scaled integration by simplifying the structure through the use of one word line as a read line and a write line and a method of manufacturing the magnetic RAM.

In accordance with one aspect of the present invention, there is provided a magnetic random access memory (RAM) comprising: a gate electrode formed on an active region in a semiconductor substrate and being a word line used as a write line; a ground line formed in one side of the word line; a lower lead layer formed in the other side of the word line; a seed layer connected to the lower lead layer and overlapped with the word line; a magnetic tunnel junction (MTJ) cell formed on the seed layer and located in an upper portion of the word line; and an upper lead layer being a bit line formed connected to the MTJ cell.

In accordance with another aspect of the present invention, there is provided a method for manufacturing the magnetic RAM in accordance with the present invention, which comprises the steps of: forming a gate electrode on an active region in a semiconductor substrate, wherein the gate electrode is a word line used as a write line; forming a ground line in one side of the word line; forming a lower lead layer in the other side of the word line; forming a seed layer connected to the lower lead layer and overlapped with the word line; forming a magnetic tunnel junction (MTJ) cell on the seed layer and in an upper portion of the word line; and forming an upper lead layer being a bit line connected to the MTJ cell.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and features of the instant invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which: [0033]
FIG. 1 shows a cross-sectional view of a conventional magnetic RAM; and [0034]
FIG. 2 illustrates a cross-sectional view of a magnetic RAM in accordance with the present invention.[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. [0036]
Referring to FIG. 2, there is illustrated a cross-sectional view of a magnetic RAM in accordance with an embodiment of the present invention. [0037]
First of all, there is formed on a semiconductor substrate [0038] 111 a device separating film (not shown) defining an active region.
Next, a transistor is made by forming a [0039] gate electrode 113 including a gate dielectric film on the active region of the semiconductor substrate 111, making dielectric film spacers (not shown) on sidewalls of the gate electrode 113 and forming source/ drain junction regions 115 a and 115 b by implanting impurities into the active region of the semiconductor substrate 111.
Herein, since the effect of a magnetic field increases as the distance between an MTJ cell and the [0040] gate electrode 113 used as a write line becomes smaller, an insulating film between two layers is formed having a small thickness in the following manufacturing process.
The [0041] gate electrode 113 has a laminated structure of polysilicon/tungsten films, poly-silicon/tungsten/poly-silicon films or copper/poly-silicon/copper films, so that the formation of a dielectric material can be smoothly performed on the top of the gate electrode 113.
Subsequently, a first layer [0042] insulating film 121 is formed planarizing the top surface of an intermediate product. At this time, the first layer insulating film 121 covers a ground line 117 connected to the source junction region 115 a and a lower lead layer 119 connected to the drain junction region 115 b, which are formed prior to the first layer insulating film 121.
In other words, the first layer [0043] insulating film 121 is made by planarizing dielectric materials deposited on the top surface of the intermediate product as well as exposing the surfaces of the lower lead layer 119 and the gate electrode 113 being a word line.
Next, a second layer [0044] insulating film 123 is formed on the top of the first layer insulating film 121 and there is made a contact plug 125 that is connected to the lower lead layer 119 through the second layer insulating film 123.
A [0045] seed layer 127 is formed connected to the contact plug 125. An area of the seed layer 127 is made sufficiently overlapped with the word line 113.
After that, a third layer [0046] insulating film 129 is formed exposing the surface of the seed layer 127.
An MTJ cell [0047] 137 is formed on the seed layer 127 and located at an upper portion of the word line 113.
The MTJ cell [0048] 137 has a laminated structure, which is made by stacking an antiferromagnetic layer (not shown), a pinned ferromagnetic layer 131, a tunnel junction layer 133 and a free ferromagnetic layer 135 and patterning the stacked layers through the use of a mask for forming an MTJ cell.
Then, a fourth layer [0049] insulating film 139 is formed exposing the MTJ cell 137 and an upper lead layer 141, i.e., a bit line, is made connected to the free ferromagnetic layer 135 of the MTJ cell 137, thereby producing the magnetic RAM in accordance with the present invention.
Hereinafter, there is described a data storing operation of the magnetic RAM in accordance with the present invention. [0050]
Initially, the free spin structure of the MTJ cell [0051] 137 is changed by a magnetic field induced by the current flowing through the gate electrode, i.e., the word line 113 and the current is transferred to the semiconductor substrate 111 from the MTJ cell 137. The current flowing through the MTJ cell 137 drains out to the ground line 117 through the transistor when the word line 113 is at a high state. To prevent the current from flowing off, by raising the ground potential of the ground line 117 by providing a voltage or current to the ground line 117, the current flowing through the MTJ cell 137 does not flow off to the ground line 117 via the transistor.
At this time, it is possible to supply a substrate voltage Vbs to the [0052] semiconductor substrate 111 at the same time a ground voltage Vss is provided to the ground line 117.
Further, the substrate voltage Vbs can be supplied to the [0053] ground line 117 instead of the ground voltage Vss.
As described above, the magnetic RAM in accordance with the present invention can omit the process of forming a second word line by allowing one word line to play the role of both the write line and a read line, so that it is possible to achieve large scaled integration and enhance the processing stability by decreasing processing steps. [0054]
While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims. [0055]

Claims

What is claimed is:

1. A magnetic random access memory (RAM) comprising:

a gate electrode formed on an active region in a semiconductor substrate and being a word line used as a write line;

a ground line formed in one side of the word line;

a lower lead layer formed in the other side of the word line;

a seed layer connected to the lower lead layer and overlapped with the word line;

a magnetic tunnel junction (MTJ) cell formed on the seed layer and located in an upper portion of the word line; and

an upper lead layer being a bit line formed connected to the MTJ cell.

2. The magnetic RAM as recited in claim 1, wherein the gate electrode has a laminated structure selected from the group consisting of stacked poly-silicon and tungsten films, stacked poly-silicon, tungsten and poly-silicon films and stacked copper, poly-silicon and copper films.

3. The magnetic RAM as recited in claim 1, wherein the gate electrode is separated from neighboring conductive layers by a dielectric film planarized to expose the surface of the gate electrode.

4. The magnetic RAM as recited in claim 1, wherein the MTJ cell has a laminated structure of a pinned ferromagnetic layer, a tunnel junction layer and a free ferromagnetic layer.

5. The magnetic RAM as recited in claim 1, wherein the potential of the ground line is raised in a data storing operation.

6. The magnetic RAM as recited in claim 5, wherein the ground line is provided with a substrate voltage Vbs.

7. The magnetic RAM as recited in claim 5, wherein the ground line is provided with a ground voltage Vss and the semiconductor substrate is supplied with a substrate voltage Vbs.

8. A method for manufacturing a magnetic RAM a gate electrode formed on an active region in a semiconductor substrate and being a word line used as a write line, a ground line formed in one side of the word line, a lower lead layer formed in the other side of the word line, a seed layer connected to the lower lead layer and overlapped with the word line, a magnetic tunnel junction (MTJ) cell formed on the seed layer and located in an upper portion of the word line, and an upper lead layer being a bit line formed connected to the MTJ cell, wherein the method comprises the steps of:

forming a gate electrode on an active region in a semiconductor substrate, wherein the gate electrode is a word line used as a write line;

forming a ground line in one side of the word line;

forming a lower lead layer in the other side of the word line;

forming a seed layer connected to the lower lead layer and overlapped with the word line;

forming a magnetic tunnel junction (MTJ) cell on the seed layer and in an upper portion of the word line; and

forming an upper lead layer being a bit line connected to the MTJ cell.