WO2006051666A1 - Materiel et procede d'essai de memoire a semi-conducteurs avec blocs multiples - Google Patents

Materiel et procede d'essai de memoire a semi-conducteurs avec blocs multiples Download PDF

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Publication number
WO2006051666A1
WO2006051666A1 PCT/JP2005/018846 JP2005018846W WO2006051666A1 WO 2006051666 A1 WO2006051666 A1 WO 2006051666A1 JP 2005018846 W JP2005018846 W JP 2005018846W WO 2006051666 A1 WO2006051666 A1 WO 2006051666A1
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WIPO (PCT)
Prior art keywords
test
data
under test
memory under
memory
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PCT/JP2005/018846
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English (en)
Japanese (ja)
Inventor
Takashi Hasegawa
Naoyoshi Watanabe
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Advantest Corporation
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Publication of WO2006051666A1 publication Critical patent/WO2006051666A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56004—Pattern generation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C2029/5606—Error catch memory

Definitions

  • the present invention relates to a test apparatus and a test method.
  • the present invention relates to a test apparatus and a test method for testing a memory under test in which data is written to or read from a plurality of storage areas simultaneously.
  • a test apparatus and a test method for testing a memory under test in which data is written to or read from a plurality of storage areas simultaneously.
  • a conventional test apparatus stores a test result for the block in a bad block memory in association with addresses of a plurality of blocks of the memory under test, and generates a map of defective blocks. Then, the pass / fail judgment of the memory under test is performed with reference to the map of defective blocks. Specifically, the test pattern data is written to the defective block and the expected value of the output data from the defective block so that unnecessary tests are not repeatedly performed on the defective block of the memory under test. Prohibiting comparison prevents the test throughput from decreasing (for example, see Patent Document 1) o
  • Patent Document 1 Japanese Unexamined Patent Application Publication No. 2002-15596
  • An AND-type flash memory has a plurality of banks including a plurality of blocks, and a plurality of blocks each including a plurality of banks including data supplied to a plurality of data registers provided corresponding to the plurality of banks. The data stored in each of the plurality of blocks included in each of the plurality of banks is simultaneously read into each of the plurality of data registers.
  • a defective block of a memory under test is referred to by referring to a map of a defective block.
  • the above-mentioned AND type flash memory is tested in the same way, there is a problem in that blocks other than defective blocks may not be properly tested.
  • the test apparatus disclosed in Japanese Patent Laid-Open No. 2002-15596 has a problem that the hardware configuration becomes large and complicated.
  • an object of the present invention is to provide a test apparatus that can solve the above-described problems.
  • This object is achieved by a combination of features described in the independent claims.
  • the dependent claims define further advantageous specific examples of the present invention.
  • a test apparatus for testing a memory under test in which data is written to or read from a plurality of storage areas simultaneously, and a plurality of memories included in the memory under test.
  • a plurality of addresses indicating each of the areas
  • a pattern generator that generates a plurality of test pattern data to be written to each of the plurality of storage areas
  • storage of defects in the plurality of storage areas of the memory under test A write inhibit signal is tested when the defective storage area storage section that stores information indicating the area and the predetermined address generated by the pattern generator indicates a defective storage area stored in the defective storage area storage section.
  • a write prohibition signal generator for prohibiting the writing of test pattern data to the memory under test and the test pattern to be supplied to the storage area indicated by the predetermined address
  • a write forced valid signal generator for releasing the prohibition of writing test pattern data to the memory under test by supplying a write forced valid signal to the memory under test when generation of data is finished .
  • the non-turn generator continuously supplies a set of addresses and test pattern data to a plurality of memories under test and holds them in a plurality of data registers of a memory under test, and then stores a plurality of test pattern data.
  • the execution command for causing the memory under test to execute the transfer to the memory area indicated by each of the plurality of addresses from the plurality of data registers is generated and supplied to the memory under test. It is possible to supply a forced write enable signal before the execution command is supplied to the memory under test.
  • the write forced valid signal generator supplies the memory under test continuously by the pattern generator.
  • writing is forced between the last set and the execution command. You may supply a valid signal.
  • a logical comparator that compares the output data output from the memory under test according to the address and test pattern data generated by the non-turn generator with the expected value data generated in advance, and the defective storage area storage unit store the data. Defective memory area power
  • a comparison inhibit signal is supplied to the logical comparator to compare the output data by the logical comparator with the expected value data.
  • the comparison compulsory valid signal is sent to the logical comparator.
  • a compulsory compulsory valid signal generation unit that cancels the prohibition of comparison between the output data and the expected value data by the logical comparator.
  • the memory under test includes a plurality of banks having a plurality of blocks as a plurality of storage areas, and a plurality of data registers corresponding to the plurality of banks, and is supplied to each of the plurality of data registers.
  • the defective data storage unit stores information indicating that the block indicated by the address is defective in association with the address of the block. May be stored.
  • a test method for testing a memory under test in which data is written to or read from a plurality of storage areas at the same time.
  • a pattern generation stage for generating a plurality of test pattern data to be written to each of a plurality of addresses and a plurality of storage areas, and a defective storage area of the plurality of storage areas of the memory under test.
  • the predetermined address generated in the defective storage area storage stage storing the information to be stored in the defective storage area storage section and the pattern generation stage indicates a defective storage area stored in the defective storage area storage section.
  • FIG. 1 is a diagram showing a configuration of a test apparatus 100.
  • FIG. 2 is a diagram showing a configuration of a memory under test 150.
  • FIG. 3 is a diagram showing a configuration of a memory under test 150.
  • FIG. 4 is a diagram showing defect information of a memory under test 150.
  • FIG. 5 is a diagram showing a multi-bank operation of the memory under test 150.
  • FIG. 6 is a diagram showing a multi-bank operation of the memory under test 150.
  • FIG. 7 is a diagram showing a first example of a detailed configuration of the test apparatus 100.
  • FIG. 8 is a diagram showing a write enable signal for the memory under test 150.
  • FIG. 9 is a diagram showing a second example of a detailed configuration of the test apparatus 100.
  • FIG. 1 shows an exemplary configuration of a test apparatus 100 according to an embodiment of the present invention.
  • the test apparatus 100 includes a timing generator 102, a pattern generator 104, a waveform shaper 106, a driver 108, a comparator 110, a logical comparator 112, a fail memory 114, and a pass / fail judgment unit 116.
  • the test throughput is increased without redundantly testing defective blocks of the memory under test 150, and the memory under test 150 includes a plurality of banks having a plurality of blocks.
  • the memory under test 150 includes a plurality of banks having a plurality of blocks.
  • a multi-bank operation that simultaneously writes or reads data to multiple blocks is performed. The purpose is to appropriately test the memory under test 150 even in the case of failure.
  • the non-turn generator 104 outputs a timing set signal (hereinafter referred to as “TS signal”) and supplies it to the timing generator 102.
  • the timing generator 102 based on the timing data specified by a TS signal, and generate a periodic clock and the delayed clock Te, supplies a delayed clock to the pattern generator 104, supplies the delayed clock to the waveform shaper 106 To do.
  • the non-turn generator 104 generates an address indicating each of a plurality of blocks, which are a plurality of storage areas of the memory under test 150, and a plurality of test pattern data to be written in each of the plurality of blocks. To supply.
  • the waveform shaper 106 generates a test pattern signal indicated by the test pattern data generated by the pattern generator 104 based on the delay clock supplied from the timing generator 102. Then, the waveform shaper 106 supplies the address supplied from the pattern generator 104 and the generated test pattern signal to the memory under test 150 via the driver 108.
  • the pattern generator 104 generates in advance expected value data that is output data that the memory under test 150 should output in accordance with the address and the test pattern signal, and supplies the expected value data to the logic comparator 112. Then, the logical comparator 112 compares the output data output from the memory under test 150 according to the address and the test pattern data with the expected value data supplied from the pattern generator 104, and outputs the output data and the expected value. I'm sorry for the data! In case of /, output fail data.
  • the fail memory 114 sequentially stores the fail data output from the logical comparator 112 in association with the address generated by the pattern generator 104.
  • the fail memory 114 counts the number of fail data output from the logical comparator 112 for each bank.
  • the pass / fail judgment unit 116 judges pass / fail of the memory under test 150 based on the fail data stored in the fail memory 114 and the number of fail data counted by the fail memory 114.
  • the test apparatus 100 in the test of the memory under test 150 including a plurality of banks having a plurality of blocks, the throughput of the test without redundantly testing the defective blocks of the memory under test 150 In addition, even when the memory under test 150 is operated in a multi-bank, it can be tested appropriately.
  • FIG. 2 and 3 show an example of the configuration of the memory under test 150 according to the present embodiment.
  • FIG. 4 shows an example of defect information of the memory under test 150 according to this embodiment. 2, 3, and 4, a 1 Gbit AND flash memory, which is an example of the memory under test 150, will be described.
  • the 1 Gbit AND flash memory is divided into four banks (banks 0 to 3). As shown in Fig. 2, one bank consists of 8192 blocks, one block consists of 2 pages, and one page consists of a 2048-byte data area and a 64-byte defect information area. In addition, not all blocks can be used at the time of shipment in the AND type flash memory, and some of them include defective blocks discovered by the test apparatus 100. Therefore, when using an AND-type flash memory, a bad block is determined based on the bad information written in the bad information area of each page, and it is used avoiding the bad block. For example, when data as shown in FIG. 4 is written in the defect information area of the page, it is determined that the block is usable.
  • FIG. 5 and FIG. 6 show an example of the multi-bank operation of the memory under test 150 according to this embodiment.
  • FIG. 5A shows an example of the configuration of the memory under test 150 and the order of data write operations.
  • FIG. 5B shows an example of write data to the memory under test 150.
  • FIG. 6A shows an example of the configuration of the memory under test 150 and the order of data read operations.
  • FIG. 6 (b) shows an example of read data to the memory under test 150.
  • the memory under test 150 includes a plurality of banks 0 to 3 each having a plurality of blocks and a plurality of data corresponding to each of the plurality of banks.
  • Registers 500 to 503 and an I / O pin 504 are provided.
  • the I / O pin 504 supplies the data input to the memory under test 150 to the plurality of data registers 500 to 503, and supplies the data output from the block and held in the data registers 500 to 503 to the outside.
  • the IZO pin 504 inputs a data string as shown in FIG. That is, the IZO pin 504 continuously inputs a data input command, an address indicating a block included in the bank, and data to be written to the block indicated by the address, and the data register for each of the knocks 0 to 3 Data is stored in 500 to 503 (steps (1) to (4)). After the data is stored in the data registers 500 to 503, the write command is written from the IZO pin 504. When the command is input, the data registers 500 to 503 simultaneously write the data stored therein to the corresponding bank block of the banks 0 to 3 (step (5)).
  • Whether or not the data writing from the data registers 500 to 503 to the block is completed is determined by the level of the RYZBY pin of the memory under test 150. For example, when the level of the RYZ BY pin is low, it is determined that the internal operation of the memory under test 150 is being executed. When the level of the RYZBY pin is high, the memory under test 150 is determined. It is determined that the internal operation of is finished.
  • the IZO pin 504 inputs a data string as shown in FIG. That is, the IZO pin 504 inputs a data output command and an address indicating a block included in the banks 0 to 3 and then inputs a data read execution command.
  • data blocks 500 to 503 are simultaneously read from the blocks of data bank 0 to 3 stored in the block indicated by the input address (step (1)).
  • the level of the RYZBY pin of the memory under test 150 changes to the Hi level.
  • the address indicating the block is input again, the data force stored in the data registers 500 to 503 is sequentially output from the IZO pin 504 (steps (2) to (5)).
  • FIG. 7 shows a first example of a detailed configuration of the test apparatus 100 according to the present embodiment.
  • the test apparatus 100 according to this example further includes a waveform generator 700 and an address selector 710 in addition to the configuration shown in FIG.
  • the fail memory 114 includes an OR circuit 704 and a bad block memory 706.
  • test apparatus 100 In the test of the memory under test 150 by the test apparatus 100, if the bad block is not tested in the subsequent test items, the writing of data to the bad block is repeated. It takes time to return, reducing the throughput of the test. Therefore, the test apparatus 100 excludes defective blocks from the test target and performs subsequent test item tests.
  • the logical comparator 112 compares the output data output from the memory under test 150 with the expected value data supplied from the pattern generator 104, and generates a fail data if they do not match.
  • the bad block memory 706 stores information indicating a defective block among a plurality of blocks included in the memory under test 150.
  • the address selector 710 supplies the bad block memory 706 with the address of the bad block memory 706 corresponding to the address of the block of the memory under test 150 that has stored the output data. Then, the node block memory 706 associates with the address of the block in which the output data is stored, and indicates that the block indicated by the address is defective as information indicating that the block indicated by the address is defective. Store the data.
  • the OR circuit 704 implements the read-modify-write operation of the bad block memory 706. That is, when an address is supplied from the address selector 710 to the bad block memory 706, a logical sum operation is performed on the data string read from the bad block memory 706 and the fail data supplied from the logical comparator 112. The address selector 710 rewrites the address supplied to the bad block memory 706.
  • Bad block memory 706 force When information indicating that the block indicated by the address is defective is stored in association with the address of the block, a test for the block indicated by the address is performed in the subsequent test items. It is forbidden. Specifically, when the address of the bad block memory 706 corresponding to the address of the block under test in the memory under test 150 is supplied to the bad block memory 706, the bad block memory 706 stores the address in the address, Fail data is generated as a comparison inhibit signal and supplied to the logic comparator 112. As a result, the logical comparator 112 is prohibited from comparing the output data with the expected value data.
  • the bad block memory 706 may generate the fail data stored at the address as a write inhibit signal and supply it to the waveform generator 700. Then, the waveform generator 700 receives the write enable signal when the write inhibit signal is supplied from the bad block memory 706. Is supplied to the write enable pin of the memory under test 150. As a result, excessive writing to the defective block in the memory under test 150 is prohibited.
  • the comparison result for the cycle in which the logical comparison is prohibited is forcibly regarded as a nose, and the process proceeds to the next address or test item. Therefore, since the logical comparison is not performed, the test for the defective block is not repeated, and the test for the next block can proceed. If the total number of defective blocks in the memory under test 150 exceeds the number that can be remedied using the repair circuit provided in the memory under test 150, the memory under test 150 is excluded as a defective device. However, the following test items are not performed for the memory under test 150. In this way, by masking the defective blocks found during the test, the test time due to the defective blocks can be prevented from increasing, and defective devices can be eliminated early. Can do.
  • FIG. 8 shows an example of a write enable signal for the memory under test 150 according to the present embodiment. Specifically, Figure 8 shows that the data string input from the IZO pin 504 of the memory under test 150, the level of the RYZBY pin of the memory under test 150, and the block to be tested in bank 1 are defective. The write enable signal when it is a block and the write enable signal when the block to be tested in bank 3 is a bad block are shown.
  • the bad block memory 706 when data is written to the memory under test 150 by the multi-bank operation, the bad block memory 706 generates a write inhibit signal and a compare inhibit signal during the bank bank 1 test. As a result, the waveform generator 700 controls the write enable signal to Hi level so that writing to the memory under test 150 is prohibited. Therefore, the data input from the IZO pin 504 is not written to the data register 501 register corresponding to the bank 1.
  • the data registers 502 and 503 corresponding to bank 2 and bank 3 have data input from the IZO pin 504. Is written.
  • the execution command is input, the data written in the data registers 500, 502, and 503 is written into the corresponding block.
  • the data written in the block is read and compared with the expected value data in the logical comparator 112. For the test on the block in the bank 1, logical comparison by the logical comparator 112 is prohibited. Therefore, the comparison result is forcibly regarded as a pass.
  • the node block memory 706 when data is written to the memory under test 150 by the multi-bank operation, the node block memory 706 generates a write inhibit signal and a compare inhibit signal during the bank bank 3 test. As a result, the waveform generator 700 controls the write enable signal to Hi level so that writing to the memory under test 150 is prohibited.
  • the node block memory 706 continues to generate the write inhibit signal and the comparison inhibit signal. Therefore, data written to data registers 500, 501, and 502 is not written to the corresponding block. Further, since the logical comparison by the logical comparator 112 is prohibited, the level of the RYZBY pin is detected, and all the comparison results for the banks 0 to 3 are forcibly regarded as a pass.
  • FIG. 9 shows a second example of a detailed configuration of the test apparatus 100 according to the present embodiment.
  • the test apparatus 100 according to this example further includes a waveform generator 800, an AND circuit 802, a forced valid signal generator 808, and an address selector 810 in addition to the configuration shown in FIG.
  • the fail memory 114 includes an OR circuit 804 and a bad block memory 806.
  • the bad block memory 806 is an example of the defective storage area storage unit, the write prohibition signal generation unit, and the comparison prohibition signal generation unit of the present invention. It functions as a signal generator and a comparison prohibition signal generator.
  • the forced valid signal generation unit 808 is an example of the write forced valid signal generation unit and the comparative forced valid signal generation unit of the present invention, and the write forced valid signal generation unit and the comparative forced valid signal generation of the present invention. It has a function as a part.
  • the logical comparator 112 compares the output data output from the memory under test 150 with the expected value data supplied from the pattern generator 104, and generates a fail data if they do not match. Then, the bad block memory 806 is supplied.
  • the bad block memory 806 stores information indicating a defective block among a plurality of blocks included in the memory under test 150.
  • the address selector 810 supplies the bad block memory 806 with the address of the bad block memory 806 corresponding to the address of the block of the memory under test 150 storing the output data. Then, the node block memory 806 associates with the address of the block where the output data is stored, and indicates that the block indicated by the address is defective as information indicating that the block indicated by the address is defective. Store the data.
  • the OR circuit 804 implements the read-modify-write operation of the bad block memory 806. That is, when an address is supplied from the address selector 810 to the bad block memory 806, the data string read from the bad block memory 806 and the fail data supplied from the logical comparator 112 are logically ORed. Then, the address selector 810 writes again to the address supplied to the bad block memory 806.
  • the bad block memory 806 supplies a write inhibit signal to the memory under test 150 when the predetermined address force generated by the pattern generator 104 indicates a defective block stored in the bad block memory 806. Writing test pattern data to the memory under test 150 is prohibited. Specifically, the bad block memory 806 generates the file data stored at the address as a write inhibit signal and supplies it to the waveform generator 800 via the AND circuit 802. Then, when the write inhibit signal is supplied from the node block memory 806, the waveform generator 800 controls the write enable signal to control the write enable of the memory under test 150. Supply to Rubin. This prohibits excessive writing to bad blocks in the memory under test 150.
  • the bad block memory 806 sends a comparison inhibit signal to the logical comparator 112 when the output data from which the bad block power of the memory under test 150 stored in the bad block memory 806 is also read is output from the memory under test 150. , The comparison between the output data and the expected value data by the logic comparator 112 is prohibited. More specifically, when the address power address selector 810 of the bad block memory 806 corresponding to the address of the block under test in the memory under test 150 is supplied to the bad block memory 806, the nod block memory 806 Fail data stored at the address is generated as a comparison prohibition signal, and is supplied to the logical comparator 112 via the logical product circuit 802. As a result, the logical comparator 112 is prohibited from comparing the output data with the expected value data.
  • the forced valid signal generation unit 808 supplies the write forced valid signal to the memory under test 150 to thereby supply the test memory 150 with the test valid data. Cancel the prohibition of writing test pattern data.
  • the forced valid signal generation unit 808 supplies a write forced valid signal to the AND circuit 802.
  • the AND circuit 802 performs an AND operation on the waveform of the write inhibit signal supplied from the bad block memory 806 and the inverted signal of the write forced enable signal supplied from the forced valid signal generator 808.
  • the waveform generator 800 controls the write enable signal based on the signal supplied from the AND circuit 802 and supplies it to the write enable pin of the memory under test 150. This forcibly enables writing to the bad block in the memory under test 150.
  • the compulsory valid signal generation unit 808 compares the compulsory compulsory signal 806 when the output from the memory under test 150 of the output memory data read out from the memory under test 150 stored in the bad block memory 806 is completed. By supplying the valid signal to the logical comparator 112, the prohibition of comparison between the output data by the logical comparator 112 and the expected value data is released. Specifically, the forced valid signal generation unit 808 supplies a comparison forced valid signal to the AND circuit 802. The AND circuit 802 logically combines the comparison inhibit signal supplied from the nod block memory 806 and the inverted signal of the comparison forced enable signal supplied from the forced valid signal generation unit 808. The product is calculated and supplied to the logical comparator 112. Then, based on the signal supplied from the AND circuit 802, the logical comparator 112 forcibly enables the comparison processing between the output data and the expected value data.
  • the pattern generator 104 has a memory under test 150 that supplies a plurality of sets of block addresses and test pattern data to the memory under test 150 in succession.
  • the data is held in a plurality of data registers 500 to 503.
  • the pattern generator 104 generates an execution command for causing the memory under test 150 to transfer a plurality of test pattern data from a plurality of data registers 500 to 503 to a block indicated by each of the plurality of addresses.
  • the forced valid signal generator 808 preferably supplies a write forced valid signal before the pattern generator 104 supplies an execution command to the memory under test 150.
  • the forced valid signal generator 808 includes an address power bad block memory 806 included in the last set of the set of addresses and test pattern data that the pattern generator 104 continuously supplies to the memory under test 150. When indicating a bad block to be stored, it is preferable to supply a write forced valid signal between the last set and the execution command.
  • the data registers 500 to 503 are initialized every time the test cycle is completed, and for example, 1 is stored in all the memory cells.
  • the initialized data registers 500 to 503 do not write the stored data to the blocks in the banks 0 to 3 even when the execution command is supplied to the memory under test 150. . Therefore, since the data registers 500 to 503 to which no data is supplied by the write inhibit signal do not write data to the blocks in the banks 0 to 3, it is possible to prevent the test time from being prolonged due to the data writing to the defective block. .
  • the last set of the address and the test pattern data generated by the pattern generator 104 is the memory under test 150.
  • the write block signal generated by the bad block memory 806 for the memory under test 150 and the comparison signal generated by the bad block memory 806 for the logical comparator 112 are input to the forced valid signal generator. It is invalidated by a write forced valid signal and a comparative forced valid signal generated by 808. Data to the memory under test 150 And the logical comparison by the logical comparator 112 are forcibly enabled.
  • a test apparatus and a test method for appropriately testing a memory under test that simultaneously writes data to or reads data from a plurality of blocks by multi-bank operation. Can provide.

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

L'invention concerne le matériel d'essai qui comprend un générateur de séquence qui crée une pluralité d'adresses indiquant des zones mémoire multiples d'une mémoire à l'essai et une pluralité de données de séquence d'essai écrites dans ces zones, un module pour stocker des données indiquant des zones mémoire défaillantes parmi la pluralité de zones mémoire, un module produisant un signal pour inhiber l'écriture de données de séquence d'essai dans la mémoire lorsqu'une adresse prédéterminée créée par le générateur de séquence indique une zone mémoire défaillante et un module générant un signal d'autorisation d'écriture forcée pour lever l'inhibition de l'écriture de données de séquence d'essai dans la mémoire au terme de la génération de données de séquence d'essai alimentant une zone mémoire indiquée par l'adresse prédéterminée.
PCT/JP2005/018846 2004-11-15 2005-10-13 Materiel et procede d'essai de memoire a semi-conducteurs avec blocs multiples WO2006051666A1 (fr)

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WO2008078529A1 (fr) * 2006-12-26 2008-07-03 Advantest Corporation Appareillage de test et procédé de test
KR101015488B1 (ko) 2007-03-08 2011-02-22 가부시키가이샤 어드밴티스트 시험 장치
KR101096138B1 (ko) 2007-10-09 2011-12-20 가부시키가이샤 어드밴티스트 시험 장치 및 시험 방법
JP4889792B2 (ja) 2007-11-14 2012-03-07 株式会社アドバンテスト 試験装置
KR102468381B1 (ko) * 2021-01-12 2022-11-16 중앙대학교 산학협력단 병렬 스토리지 장치를 위한 저장매체 검사 장치 및 방법과 이를 위한 컴퓨터 프로그램

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JP2001167597A (ja) * 2000-01-24 2001-06-22 Advantest Corp 半導体メモリ試験装置
JP2002050193A (ja) * 2000-05-24 2002-02-15 Advantest Corp メモリ試験方法・メモリ試験装置
WO2002097822A1 (fr) * 2001-05-25 2002-12-05 Advantest Corporation Dispositif d'essai de semiconducteurs

Patent Citations (3)

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Publication number Priority date Publication date Assignee Title
JP2001167597A (ja) * 2000-01-24 2001-06-22 Advantest Corp 半導体メモリ試験装置
JP2002050193A (ja) * 2000-05-24 2002-02-15 Advantest Corp メモリ試験方法・メモリ試験装置
WO2002097822A1 (fr) * 2001-05-25 2002-12-05 Advantest Corporation Dispositif d'essai de semiconducteurs

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