WO2006044163A2 - Systeme et procede pour eviter un decalage dans une memoire permanente et reduire l'encombrement de celle-ci - Google Patents

Systeme et procede pour eviter un decalage dans une memoire permanente et reduire l'encombrement de celle-ci Download PDF

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Publication number
WO2006044163A2
WO2006044163A2 PCT/US2005/035166 US2005035166W WO2006044163A2 WO 2006044163 A2 WO2006044163 A2 WO 2006044163A2 US 2005035166 W US2005035166 W US 2005035166W WO 2006044163 A2 WO2006044163 A2 WO 2006044163A2
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WO
WIPO (PCT)
Prior art keywords
coupled
memory
cell line
circuits
verify
Prior art date
Application number
PCT/US2005/035166
Other languages
English (en)
Other versions
WO2006044163A3 (fr
Inventor
Massimiliano Frulio
Riccardo Riva Reggiori
Andrea Sacco
Luca Figini
Original Assignee
Atmel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from IT001927A external-priority patent/ITMI20041927A1/it
Application filed by Atmel Corporation filed Critical Atmel Corporation
Publication of WO2006044163A2 publication Critical patent/WO2006044163A2/fr
Publication of WO2006044163A3 publication Critical patent/WO2006044163A3/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

Definitions

  • the present invention relates to non- volatile memory, and more particularly to avoiding offset in and reducing the footprint of a non- volatile memory.
  • Non- volatile memory is a type of memory that preserves data with or without power applied to the memory.
  • Most computer and electronic systems use a binary number system with bits. Two distinctly different current levels that flow through the memory under the correct conditions represent each bit, a one or a zero.
  • Some memory is single-level, where one bit of information is stored in each memory cell.
  • current through the memory cell is compared to a reference memory cell. A current through the memory cell that is lower than that through the reference cell represents one bit value, while a current through the memory cell that is higher than that through the reference cell represents the other bit value.
  • a memory device In advanced memory devices, it is desirable to simultaneously perform multiple operations on memory, for example read while writing, or read while erasing.
  • a memory device is organized into smaller blocks of memory called 'banks.' One operation may be performed on one bank while another operation is performed on another bank.
  • FIG. 1 is a schematic diagram illustrating one solution to this problem with conventional system 90.
  • System 90 is a non- volatile memory with memory banks 100 connected to Y-decoder and sense amplifier circuit 102, and to X-decoder circuit 104. Rather than having only two sets of amplifiers, as in previously described memory architecture, each memory bank 100 has amplifier circuit 102.
  • bias circuit 103 activates a reference cell current from reference matrix 101.
  • FIG. 1 is a schematic diagram illustrating components of conventional system
  • Bias circuit 103 includes transistor 110, which, during a memory read, for example, activates reference matrix 101.
  • Reference matrix 101 includes transistors 112 and 114.
  • Transistor 114 is also activated during a memory read, which causes a reference cell current to flow through reference cell 118.
  • Cell 116 is used during verify operations. Current through reference cell 118 flows through transistor 120 and is mirrored by transistor 122, and caused to flow through transistor 124.
  • transistor 126 mirrors reference cell current and causes it to flow through transistor 128.
  • memory block 100 with memory cell 130 is biased by transistor 132, causing current to flow, with a voltage drop across transistors 132 and memory cell 130, and other associated components that are not illustrated for simplicity.
  • Sense amplifier 134 compares the current through (or voltage across) memory cell 130 with the current through reference cell 118.
  • the bit value stored in memory cell 130 is related to the current through memory cell 130 relative to current through reference cell 118.
  • One problem with conventional system 90 is that it takes a large amount of space to implement (it has a large "footprint"). Another problem is that it takes a significant amount of time to test conventional system 90.
  • the present invention provides a system and method for avoiding offset, reducing test time and reducing the footprint of a non- volatile memory that has a plurality of memory bank circuits.
  • Each memory bank circuit has memory cells coupled to sense amplifiers, row and column decoders coupled to the memory cells, and bias circuits coupled to the sense amplifiers.
  • the system includes a reference cell matrix coupled to each of the plurality of memory bank circuits. The reference cell matrix is configured to provide reference cell current for each of the plurality of memory bank circuits.
  • the present invention reduces the footprint necessary by connecting a single reference cell matrix to multiple memory banks, rather than having a single reference cell for each memory bank. Offset has not been affected over conventional system 90 because there are still sets of sense amplifiers for each memory bank, and testing time is improved over a conventional system.
  • Figure 1 is a schematic diagram illustrating a conventional memory and reference cell routing system.
  • Figure 2 is a schematic diagram illustrating components of the conventional system from FIG. 1.
  • Figure 3 is a schematic diagram illustrating one embodiment of the invention.
  • Figure 4 is a schematic diagram illustrating more detail of the embodiment from
  • the present invention relates to non-volatile memory, and more particularly to avoiding offset in and reducing the footprint of a non-volatile memory.
  • FIG. 3 is a schematic diagram illustrating one embodiment of the invention in a non- volatile memory 300.
  • a non- volatile memory 300 has, for example, memory banks 302 connected to X-decoders 304 and sense amplifiers 306.
  • Biasing circuits 308 connect to sense amplifiers 306. Both the biasing circuits 308 and the sense amplifiers 306 are local to memory banks 302, in other words a given biasing circuit and a given sense amplifier serve a particular memory bank.
  • the sense amplifiers 306 include Y- decoders, while the X-decoder 304 is also local to a particular memory bank. Keeping sense amplifiers 306 local avoids the problem of offset arising in some conventional systems.
  • a reference cell matrix 310 attaches to each of the biasing circuits 308 and is global, i.e. it provides reference cell current to multiple biasing circuits 308.
  • FIG. 3 six memory banks are illustrated, though less or more may be implemented in system 300. All six memory banks are connected to a global reference cell 310.
  • the reference cell matrix 310 may be connected to less or more memory banks 302, and need not be connected to every memory bank 302 in system 300.
  • Lines 312 may be connected to ground in order to shield reference current from interference and noise.
  • one of the biasing circuits 308 biases the reference cell matrix 310 in order that the reference cell matrix 310 may provide reference cell current to one of the sense amplifiers 306. Then the sense amplifier 306 that receives the reference cell current compares the reference cell current to current in a memory cell (see FIG. 4) of memory banks 302 in order that the value of data held in the memory cell may be determined.
  • the system 300 provides a global reference cell matrix 310 for multiple memory blocks 302, as opposed to conventional systems, which utilizes a local reference matrix for each memory block.
  • Figure 4 is a schematic diagram illustrating more detail from system 300 from
  • the memory block 302 includes, among other circuits, a memory cell 400.
  • a transistor 402 connects to the memory cell 400 and other circuits (not shown).
  • Transistors 404 and 406 connect to provide a point of contact for an amplifier 408, which compares current through the memory cell 400 with a reference cell current during memory read operations, for example.
  • FIG. 4 Although only a single memory cell 400 and a single amplifier 306 are illustrated in FIG. 4, a typical non- volatile memory has more than one of each of these.
  • one of the memory banks 302 typically has more than one memory cell 400, while one of the sense amplifiers 306 typically has more than one amplifier 408.
  • Transistors 410 and 412 comprise a current mirror to reflect current through the biasing circuit 308 to the sense amplifiers 306. Multiple sense amplifiers 306 are typically connected to each biasing circuit 308. Transistors 414 and 416 comprise a current mirror to reflect reference cell current passing through the reference cell matrix 310 to the biasing circuit 308.
  • a bias transistor 418 biases both of the transistors 420 and 422, which in one embodiment are verify and read transistors.
  • the verify transistor 420 may be biased for a memory verify operation, while the read transistor 422 may be biased for a memory read operation.
  • One of the memory banks 302 may be conducting a memory verify operation with the transistors 418 and 420 biased (respective to the relevant memory bank 302), while another memory bank is conducting a memory read operation with the transistors 418 and 422 biased (respective to the relevant memory bank 302).
  • the read transistor 422 biases the read cell 424 through the read cell line 426.
  • the verify transistor 420 biases the verify cell 428 through the verify cell line 430.
  • the verify cell 428 and the read cell 424 are part of the global reference cell matrix 310, serving multiple memory banks 302.
  • the lines 312 may be grounded and function to shield the verify cell line 430 and the read cell line 426 from interference and noise that could decrease error margin.
  • the advantages of the invention include minimizing test time, reducing circuit footprint by keeping local the circuitry that biases the reference cells.
  • the number of reference cells are reduced and placed in a global location and offset is avoided by using local sense amplifiers.

Abstract

L'invention concerne un système et un procédé permettant d'éviter un décalage dans une mémoire permanente comportant une pluralité de circuits de bloc de mémoire et réduire l'encombrement de celle-ci. Chaque circuit de bloc de mémoire comporte des cellules de mémoire couplées à des amplificateurs de détection, des décodeurs de rangée et de colonne couplés aux cellules de mémoire, et des circuits de polarisation couplés aux amplificateurs de détection. Le système comprend une matrice de cellule de référence couplée à chacun des circuits de bloc de mémoire. La matrice de cellule de référence est configurée pour fournir un courant de cellule de référence à chacun des circuits de bloc de mémoire.
PCT/US2005/035166 2004-10-12 2005-10-03 Systeme et procede pour eviter un decalage dans une memoire permanente et reduire l'encombrement de celle-ci WO2006044163A2 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
ITMI2004A001927 2004-10-12
IT001927A ITMI20041927A1 (it) 2004-10-12 2004-10-12 Sistema e metodo pee evitare l'offset e ridurre il footprint di una memoria non volatile
US11/126,473 US7301814B2 (en) 2004-10-12 2005-05-11 System and method for avoiding offset in and reducing the footprint of a non-volatile memory
US11/126,473 2005-05-11

Publications (2)

Publication Number Publication Date
WO2006044163A2 true WO2006044163A2 (fr) 2006-04-27
WO2006044163A3 WO2006044163A3 (fr) 2006-08-10

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108109662A (zh) * 2016-11-24 2018-06-01 北京兆易创新科技股份有限公司 一种选通开关电路及包含该电路的存储器

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6118703A (en) * 1998-04-22 2000-09-12 Nec Corporation Nonvolatile storage device and control method therefor
US6504778B1 (en) * 1999-10-13 2003-01-07 Nec Corporation Semiconductor memory device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6118703A (en) * 1998-04-22 2000-09-12 Nec Corporation Nonvolatile storage device and control method therefor
US6504778B1 (en) * 1999-10-13 2003-01-07 Nec Corporation Semiconductor memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108109662A (zh) * 2016-11-24 2018-06-01 北京兆易创新科技股份有限公司 一种选通开关电路及包含该电路的存储器

Also Published As

Publication number Publication date
WO2006044163A3 (fr) 2006-08-10

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