WO2006034696A3 - Schicht zwischen grenzflächen unterschiedlicher komponenten in halbleiterbauteilen, sowie verfahren zu deren herstellung - Google Patents

Schicht zwischen grenzflächen unterschiedlicher komponenten in halbleiterbauteilen, sowie verfahren zu deren herstellung Download PDF

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Publication number
WO2006034696A3
WO2006034696A3 PCT/DE2005/001722 DE2005001722W WO2006034696A3 WO 2006034696 A3 WO2006034696 A3 WO 2006034696A3 DE 2005001722 W DE2005001722 W DE 2005001722W WO 2006034696 A3 WO2006034696 A3 WO 2006034696A3
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WO
WIPO (PCT)
Prior art keywords
layer
production
semiconductor modules
differing components
boundary surfaces
Prior art date
Application number
PCT/DE2005/001722
Other languages
English (en)
French (fr)
Other versions
WO2006034696A2 (de
Inventor
Michael Bauer
Alfred Haimerl
Khalil Hosseini
Angela Kessler
Joachim Mahler
Wolfgang Schober
Original Assignee
Infineon Technologies Ag
Michael Bauer
Alfred Haimerl
Khalil Hosseini
Angela Kessler
Joachim Mahler
Wolfgang Schober
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Michael Bauer, Alfred Haimerl, Khalil Hosseini, Angela Kessler, Joachim Mahler, Wolfgang Schober filed Critical Infineon Technologies Ag
Priority to CN2005800329107A priority Critical patent/CN101091245B/zh
Publication of WO2006034696A2 publication Critical patent/WO2006034696A2/de
Publication of WO2006034696A3 publication Critical patent/WO2006034696A3/de
Priority to US11/692,322 priority patent/US7834467B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Nanotechnology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Carbon And Carbon Compounds (AREA)
  • Laminated Bodies (AREA)

Abstract

Die Erfindung betrifft eine Schicht (1) zwischen Grenzflächen (2) unterschiedlicher Komponenten (5, 6) in Halbleiterbautei-len (10), sowie ein Verfahren zu deren Herstellung. Dazu weist eine Komponente (5) als Grenzfläche (2) Oberflächen (3) eines Schaltungsträgers (11) auf und eine andere Komponente (6) weist als Grenzfläche (2) Berührungsflächen (4) einer Kunststoffgehäusemasse (9) auf. Die haftverbessernde Schicht (1) ist dabei eine Mischung aus polymeren Kettenmolekülen und Kohlenstoff-Nanoröhren.
PCT/DE2005/001722 2004-09-30 2005-09-28 Schicht zwischen grenzflächen unterschiedlicher komponenten in halbleiterbauteilen, sowie verfahren zu deren herstellung WO2006034696A2 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN2005800329107A CN101091245B (zh) 2004-09-30 2005-09-28 半导体器件中不同部件界面间的层及其制造方法、具有该层的半导体器件及其制造方法
US11/692,322 US7834467B2 (en) 2004-09-30 2007-03-28 Layer between interfaces of different components in semiconductor devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004048201.2 2004-09-30
DE102004048201A DE102004048201B4 (de) 2004-09-30 2004-09-30 Halbleiterbauteil mit Haftvermittlerschicht, sowie Verfahren zu deren Herstellung

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/692,322 Continuation US7834467B2 (en) 2004-09-30 2007-03-28 Layer between interfaces of different components in semiconductor devices

Publications (2)

Publication Number Publication Date
WO2006034696A2 WO2006034696A2 (de) 2006-04-06
WO2006034696A3 true WO2006034696A3 (de) 2006-07-06

Family

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PCT/DE2005/001722 WO2006034696A2 (de) 2004-09-30 2005-09-28 Schicht zwischen grenzflächen unterschiedlicher komponenten in halbleiterbauteilen, sowie verfahren zu deren herstellung

Country Status (4)

Country Link
US (1) US7834467B2 (de)
CN (1) CN101091245B (de)
DE (1) DE102004048201B4 (de)
WO (1) WO2006034696A2 (de)

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DE102005025083B4 (de) 2005-05-30 2007-05-24 Infineon Technologies Ag Thermoplast-Duroplast-Verbund und Verfahren zum Verbinden eines thermoplastischen Materials mit einem duroplastischen Material
US20080026505A1 (en) * 2006-07-28 2008-01-31 Nirupama Chakrapani Electronic packages with roughened wetting and non-wetting zones
US20080067502A1 (en) * 2006-09-14 2008-03-20 Nirupama Chakrapani Electronic packages with fine particle wetting and non-wetting zones
US8530279B2 (en) * 2008-09-11 2013-09-10 Texas Instruments Incorporated Offset gravure printing process for improved mold compound and die attach adhesive adhesion on leadframe surface using selective adhesion promoter
DE102010001711A1 (de) * 2010-02-09 2011-08-11 Robert Bosch GmbH, 70469 Halbleiter-Bauelement und entsprechendes Herstellungsverfahren
JP6278297B2 (ja) * 2013-07-24 2018-02-14 株式会社日立製作所 接合構造およびそれを用いた半導体装置
US9362191B2 (en) * 2013-08-29 2016-06-07 Infineon Technologies Austria Ag Encapsulated semiconductor device
US9281060B1 (en) 2015-06-01 2016-03-08 International Business Machines Corporation Device and method for storing or switching
US9704786B2 (en) * 2015-09-25 2017-07-11 Infineon Technologies Ag Direct selective adhesion promotor plating
US10727085B2 (en) * 2015-12-30 2020-07-28 Texas Instruments Incorporated Printed adhesion deposition to mitigate integrated circuit package delamination
JP6686691B2 (ja) * 2016-05-16 2020-04-22 株式会社デンソー 電子装置

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WO1999040812A1 (en) * 1998-02-12 1999-08-19 Board Of Trustees Operating Michigan State University - Micro-fastening system and method of manufacture
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US20030208888A1 (en) * 2002-05-13 2003-11-13 Fearing Ronald S. Adhesive microstructure and method of forming same
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DE102004048201A1 (de) 2006-04-13
CN101091245B (zh) 2010-06-16
DE102004048201B4 (de) 2009-05-20
US20070205518A1 (en) 2007-09-06
WO2006034696A2 (de) 2006-04-06
US7834467B2 (en) 2010-11-16

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