WO2006030662A1 - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
WO2006030662A1
WO2006030662A1 PCT/JP2005/016267 JP2005016267W WO2006030662A1 WO 2006030662 A1 WO2006030662 A1 WO 2006030662A1 JP 2005016267 W JP2005016267 W JP 2005016267W WO 2006030662 A1 WO2006030662 A1 WO 2006030662A1
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WO
WIPO (PCT)
Prior art keywords
electrodes
semiconductor
semiconductor device
electrode
wiring board
Prior art date
Application number
PCT/JP2005/016267
Other languages
French (fr)
Japanese (ja)
Inventor
Tomoaki Kuroishi
Yoshihiko Yagi
Original Assignee
Matsushita Electric Industrial Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2004266186A external-priority patent/JP2006086145A/en
Priority claimed from JP2004353465A external-priority patent/JP4578220B2/en
Application filed by Matsushita Electric Industrial Co., Ltd. filed Critical Matsushita Electric Industrial Co., Ltd.
Publication of WO2006030662A1 publication Critical patent/WO2006030662A1/en

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    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
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    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
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    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • the present invention relates to a semiconductor device in which a plurality of semiconductor chips are stacked on a wiring board, and a manufacturing method thereof.
  • bare chips are mounted as electronic components instead of semiconductor packages, and the mounting area has been greatly reduced.
  • Methods for mounting bare chips on a wiring board include wire bonding and flip chip bonding.
  • Various methods for stacking a plurality of bare chips have been proposed in order to improve the packaging density.
  • a first layer bare chip (hereinafter simply referred to as a semiconductor chip) is fixed to one surface of a printed wiring board with a first stop, and the electrode and the printed wiring board are electrically connected with a conductive wire.
  • a second-layer semiconductor chip face-down on the first-layer semiconductor chip so that the electrodes are in contact with each other (see, for example, JP-A-9-330952).
  • the first and second layer semiconductor chips are mounted in a state where the electrodes are in contact with each other, so that the semiconductor chips of each layer are electrically connected to the wiring board independently of each other. There is a problem that can not be connected to.
  • the thickness is the sum of the thicknesses of the wiring board and its electrodes, bonding wires, and two-layer semiconductor chips, and is formed on both sides of the wiring board.
  • the superiority is small compared to the method of mounting semiconductor chips.
  • the present invention has been made in view of the above problems, and it is possible to reduce the thickness of a semiconductor device having a structure in which semiconductor chips are stacked on a wiring board, and to independently circuit each semiconductor chip on the wiring board.
  • the purpose is to make an electrical connection.
  • the present invention provides a semiconductor device in which a plurality of semiconductor chips are stacked on a wiring board, and a plurality of semiconductor chips having two layers on one surface of the wiring board.
  • the electrodes of the semiconductor chip are stacked in contact with each other, and the electrodes of the V or misaligned semiconductor chip are electrically connected to the conductor portion of the wiring board via the conductive wires, and at least of the plurality of sets of electrodes in contact with each other.
  • one electrode is formed as a dummy electrode that is not electrically connected to the internal circuit of the semiconductor chip to which the electrode belongs.
  • a semiconductor chip including a dummy electrode that is not electrically connected to an internal circuit is used in at least one of two stacked semiconductor chips.
  • a first-layer semiconductor chip is mounted on one side of the wiring board with the electrode formation surface facing up, and each electrode of the first-layer semiconductor chip and the conductor portion of the wiring board are electrically connected via a conductive wire.
  • the dummy electrode and the electrode electrically connected to the internal circuit are opposed to each other so that the second layer semiconductor chip is in contact with the plurality of electrodes on the first layer semiconductor chip. Can be implemented.
  • the semiconductor device of the present invention is a semiconductor device in which a plurality of semiconductor chips are stacked on a wiring board, wherein a plurality of conductor portions exposed on both sides are formed on a part of the wiring board. Two layers of semiconductor chips are laminated opposite to each other on both sides of the conductor portion, and electrodes of the opposing semiconductor chip are bonded to at least one surface of each conductor portion.
  • a semiconductor device in which a plurality of semiconductor chips are stacked on a wiring board is formed with a plurality of conductor parts exposed on both sides of a part of the wiring board, and two layers on both sides of the plurality of conductor parts.
  • Semiconductor chips are stacked opposite to each other, and the two-layer semiconductor chip has a plurality of electrodes, sandwiching the conductor portions between the electrodes, and sandwiching the plurality of conductor portions.
  • At least a part of the plurality of sets of electrodes is characterized in that one electrode is formed as a dummy electrode that is not electrically connected to the internal circuit of the semiconductor chip to which the electrode belongs.
  • the wiring board A plurality of conductor portions exposed on both sides are formed in parallel, and two layers of semiconductor chips are stacked on both sides of the plurality of conductor portions so as to face each other on the electrode formation surface. It has a plurality of electrodes facing the conductor part of one row and an insulating part facing the conductor part of the other row, and the conductor portion is sandwiched between each electrode and the insulating portion.
  • a semiconductor device in which a plurality of semiconductor chips are stacked on a wiring substrate, a plurality of conductor portions exposed on both sides are formed in parallel on a part of the wiring substrate, and two layers of semiconductors are formed on both sides of the plurality of conductor portions.
  • the chips are stacked opposite to each other on the electrode forming surfaces, and the two-layer semiconductor chip has a plurality of electrodes facing each conductor portion of each row and an insulating portion corresponding to each conductor portion, At least a part of a plurality of sets of electrodes that are in contact with the plurality of conductor portions from both sides with a conductor portion sandwiched between the electrodes and the insulating portion is a semiconductor chip to which one electrode belongs. It is characterized by being formed as a dummy electrode that is not electrically connected to the internal circuit.
  • a semiconductor device in which a plurality of semiconductor chips are stacked on a wiring substrate, a plurality of conductor portions exposed on both sides are formed in parallel on a part of the wiring substrate, and two conductor portions are formed on both sides of the plurality of conductor portions.
  • the semiconductor chips of the layers are stacked so as to face each other on the electrode forming surfaces, and the semiconductor chip of the first layer has a plurality of electrodes opposed to the conductor portions of each row and an insulating portion corresponding to each conductor portion,
  • the two-layer semiconductor chip has a plurality of electrodes facing the insulating portion of the first-layer semiconductor chip, and the first-layer semiconductor chip and the second-layer semiconductor chip are between the electrodes facing each other and the insulating portion.
  • the plurality of conductor portions exposed on both sides are part of the intermediate wiring layer of the wiring board. Further, it is convenient that the plurality of conductor portions exposed on both sides are in a single opening formed in the wiring board.
  • a plurality of semiconductor chips may be stacked in parallel to a single semiconductor chip.
  • Each of the semiconductor devices described above may be a semiconductor chip memory IC chip.
  • a semiconductor device module in which any of the semiconductor devices described above is stacked in a plurality of stages also forms a part of the present invention.
  • a two-layer semiconductor chip fixing structure is provided by providing a dummy electrode in a semiconductor device having a structure in which two layers of semiconductor chips are stacked in contact with each other on one side of a wiring board.
  • a dummy electrode in a semiconductor device having a structure in which two layers of semiconductor chips are stacked in contact with each other on one side of a wiring board.
  • the semiconductor chip When the conductor portion exposed on both sides is a part of the intermediate wiring layer of the wiring board or in a single opening of the wiring board, the semiconductor chip enters inside the surface of the wiring board. The thickness after mounting becomes thinner.
  • FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
  • FIG. 2 Cross-sectional view of the semiconductor device shown in Fig. 1 during manufacturing
  • FIG. 3 is an exploded perspective view of the first example semiconductor device having the cross section shown in FIG. 4] An exploded perspective view of the second example semiconductor device having the cross section shown in FIG.
  • FIG. 5 is a sectional view of a semiconductor device according to another embodiment of the present invention.
  • FIG. 6 is a sectional view of a semiconductor device according to still another embodiment of the present invention.
  • FIG. 7 is an exploded perspective view of the semiconductor device of FIG.
  • FIG. 8 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device in FIG.
  • FIG. 9 is a perspective view showing the configuration of another wiring board used in the semiconductor device of FIG.
  • FIG. 10 is an exploded perspective view of the first example semiconductor device having the cross section shown in FIG.
  • FIG. 11 is an exploded perspective view of the second example semiconductor device having the cross section shown in FIG.
  • FIG. 12 is a sectional view of a semiconductor device according to still another embodiment of the present invention.
  • FIG. 13 is a cross-sectional view and an exploded perspective view of a semiconductor device according to still another embodiment of the present invention.
  • FIG. 14 is a sectional view of a semiconductor device according to still another embodiment of the present invention.
  • FIG. 15 is a sectional view of a semiconductor device according to still another embodiment of the present invention.
  • FIG. 16 is a cross-sectional view of a semiconductor device according to still another embodiment of the present invention.
  • FIG. 17 is a sectional view of a semiconductor device module using the semiconductor device shown in FIG.
  • FIG. 18 is a cross-sectional view of another semiconductor device module using the semiconductor device shown in FIG.
  • FIG. 19 is a cross-sectional view of still another semiconductor device module using the semiconductor device shown in FIG.
  • FIG. 20 is a cross-sectional view of still another semiconductor device module using the semiconductor device shown in FIG.
  • FIG. 21 is a cross-sectional view of a semiconductor device module using the semiconductor device shown in FIG.
  • FIG. 22 is a cross-sectional view of another semiconductor device module using the semiconductor device shown in FIG. 12. BEST MODE FOR CARRYING OUT THE INVENTION
  • the adhesive 4 is provided on one surface of the printed wiring board 1 having the wiring 2 formed on the front surface, on the back surface where the first-layer semiconductor chip 5 is opposite to the circuit 6 and the electrodes 7 and 8.
  • the conductive protrusions 7a and 8a formed on the electrodes 7 and 8 and the pad electrode (not shown) of the wiring 2 of the printed wiring board 1 are electrically connected by the conductive wires 9, respectively. Connected ing.
  • the semiconductor chip 11 of the second layer has its circuit 12 and the electrodes 13 and 14 facing the circuit formation surface of the semiconductor chip 5 of the first layer, and The conductive protrusions 13a and 14a formed on the electrodes 13 and 14 are mounted in contact with the conductive protrusions 7a and 8a on the electrodes 7 and 8 of the first-layer semiconductor chip 5, respectively. Between and around the semiconductor chips 5 and 11 are sealed with grease (see FIG. 17 described later).
  • the electrode 7 is electrically connected to the circuit 6 through the circuit 15!, But the electrode 8 is electrically connected to the circuit 6. It is a dummy electrode (shown electrode).
  • the electrode 14 is electrically connected to the circuit 12 through the circuit 16, but the electrode 13 is electrically connected to the circuit 12 and is not a dummy electrode. It is.
  • the circuit 6 of the semiconductor chip 5 in the first layer is connected to the wiring 2 on the right side of the printed wiring board 1 through the circuit 15, the electrode 7, the conductive protrusion 7a, and the conductive wire 9. They are electrically connected and there is no electrical continuity between the circuit 6 and the wiring 2 on the left side of the printed wiring board 1.
  • the circuit 12 of the second-layer semiconductor chip 11 is electrically connected to the wiring 2 on the left side of the printed wiring board 1 through the circuit 16, the electrode 14, the conductive protrusion 14a, and the conductive wire 9. There is no electrical continuity between 12 and the wiring 2 on the right side of the printed circuit board 1.
  • the circuits 6 and 12 of the stacked semiconductor chips 5 and 11 are electrically connected to the printed wiring board 1 independently.
  • the semiconductor chip 5 is mounted on one surface of the printed wiring board 1 with the electrode formation surface facing up, and then the semiconductor chip 5 is Each electrode 7, 8 and the wiring 2 of the printed wiring board 1 are electrically connected by the conductive wire 9, and then placed on the semiconductor chip 5 to make a pair with each electrode 7, 8 of the semiconductor chip 5.
  • the semiconductor chip 11 on which the electrodes 13 and 14 are formed is mounted in contact with each other so that the dummy electrodes 8 and 13 and the electrodes 7 and 14 electrically connected to the internal circuit face each other. To do.
  • FIG. 3 shows a first example of the semiconductor device having the cross section shown in FIG. 1, and shows a state before the second-layer semiconductor chip 11 is mounted.
  • the conductive protrusions (7a, 8a, 13a, 14a) are not shown. However, the conductive protrusions (7a, 8a, 13a, 14a) are not essential.
  • the semiconductor chip 5 and the semiconductor chip 11 have the same structure. In the semiconductor chip 5, the electrodes 7 and 8 are alternately formed along a pair of non-adjacent sides. In the semiconductor chip 11, the electrodes 13 and 14 are formed along a pair of non-adjacent sides. And are formed alternately.
  • the electrodes 8 and 13 are dummy electrodes that are not connected to the circuits 6 and 12 of the semiconductor chips 5 and 11 to which they belong, respectively.
  • the electrode 8 of the semiconductor chip 5 comes into contact with the electrode 14 of the semiconductor chip 11 and the electrode 7 of the semiconductor chip 5 is connected as shown in FIG. Since it is in contact with the electrode 13 of the semiconductor chip 11 and the electrodes 8 and 13 are single electrodes, the circuit 6 of the first semiconductor chip 5 and the circuit 12 of the second semiconductor chip 11 are printed. It becomes a completely independent connection state with respect to the wiring board 1.
  • FIG. 4 is a second example of the semiconductor device having the cross section shown in FIG. 1, and shows a state before the second-layer semiconductor chip 11 is mounted.
  • the conductive protrusions (7a, 8a, 13a, 14a) are not shown.
  • the semiconductor chip 5 and the semiconductor chip 11 have the same structure.
  • an electrode 7 is formed along each of a pair of sides that are not adjacent to each other, and an electrode 8 is formed along each of the other pair of sides.
  • an electrode 13 is formed along each of a pair of sides that are not adjacent to each other, and an electrode 14 is formed along each of the other pair of sides.
  • the electrodes 8 and 13 are dummy electrodes that are not connected to the circuits 6 and 12 of the semiconductor chips 5 and 11 to which they belong, respectively.
  • the electrode 8 of the semiconductor chip 5 comes into contact with the electrode 14 of the semiconductor chip 11 and the electrode 7 of the semiconductor chip 5 is connected as shown in FIG. Since it is in contact with the electrode 13 of the semiconductor chip 11 and the electrodes 8 and 13 are single electrodes, the circuit 6 of the first semiconductor chip 5 and the circuit 12 of the second semiconductor chip 11 are printed. It becomes a completely independent connection state with respect to the wiring board 1.
  • one dummy electrode and one circuit connection electrode are provided.
  • a force that alternately or alternately arranges one side at a time A dummy electrode is placed in a part of the area, two semiconductor chips are wired independently only in that area, and a circuit that passes the same signal in other areas (signal line) ) Let's make each other conductive.
  • the semiconductor device shown in FIG. 6 has two layers of semiconductor patterns 101 and 102 facing each other on the electrode formation surface, and both sides of a conductive pattern 104 exposed on both sides of a printed wiring board 103 (hereinafter simply referred to as wiring board 103).
  • the bump electrodes 105 and 106 (hereinafter simply referred to as electrodes 105 and 106) of the semiconductor chips 101 and 102 are bonded to the opposing surface of the conductor pattern 104, respectively.
  • 101c and 102c in the figure are electrode pads.
  • a rectangular opening 103a is formed in the wiring board 103, and a plurality of conductor patterns 104 that are part of the intermediate wiring layer face the opening 103a.
  • the conductor pattern 104 in each row is located in the center of the substrate thickness direction between the upper and lower surface wiring layers 107 and the insulating layer 107a in the region around the opening 103a, and the flying lead structure extending in the direction in which the tips face each other. It is made.
  • the semiconductor chips 101, 102 are formed to have an outer dimension smaller than the opening 103a of the wiring board 103, and a plurality of electrodes 105, 106 are opposed to each other along each pair of opposite sides and are conductive patterns.
  • the conductive pattern 104 is formed so as to be opposed to the conductive pattern 104 and sandwiched between the electrodes 105 and 106. Bonding of the electrode 105, the conductor pattern 104, and the electrode 106 and sealing of the surrounding resin are performed by an anisotropic conductive resin 108.
  • the electrodes 105a arranged along one side are electrically connected to the chip internal circuit 101a via the circuit 101b.
  • the electrodes 105b arranged along the other side are
  • the chip internal circuit 101a is a dummy electrode (fake electrode) that is not electrically connected.
  • they are arranged along one side.
  • the electrode 106a is electrically connected to the chip internal circuit 102a via the circuit 102b.
  • the electrode 106b arranged along the other side is electrically connected to the chip internal circuit 102a! It is a dummy electrode.
  • the chip internal circuit 101a of the semiconductor chip 101 is electrically connected to the predetermined conductor pattern 104 through the electrode 105a, while the chip internal circuit 102a of the semiconductor chip 102 is electrically connected to the predetermined conductor pattern 104 through the electrode 106a.
  • 104 is electrically connected. That is, the internal circuits 101a and 102a of the semiconductor chips 101 and 102 mounted in a stacked manner are electrically connected independently to the printed wiring board 101 through the electrodes 105a and 106a.
  • FIG. 8 (a) When manufacturing this semiconductor device, as shown in FIG. 8 (a), as shown in FIG. 8 (a), a sheet-like anisotropic conductive resin 108 having a size substantially equal to the opening 103 3 a of the wiring substrate 103 is formed on both sides of the conductor pattern 104. As shown in FIG. 8 (b), the semiconductor chips 101, 102 are temporarily placed on both surfaces of the anisotropic conductive resin 108, and as shown in FIG. , 102 are pressed from both sides and pressed against the conductor pattern 104 at the same time.
  • the thickness of the semiconductor device as a finished product is the sum of the chip thickness and electrode thickness of the semiconductor chip 101, the chip thickness and electrode thickness of the semiconductor chip 102, and the thickness of the conductor pattern 104.
  • the thickness force S of the electrodes 105, 106 of the semiconductor chips 101, 102 is small, the chip portion enters the opening 103a of the wiring substrate 103 as shown in the figure. Therefore, the thickness can be greatly reduced as compared with a conventional semiconductor device in which a semiconductor chip is stacked on one side of a wiring board. This structure is very advantageous because a larger number of semiconductor chips can be stacked when the thickness of the entire semiconductor device is required to be kept below a certain value.
  • a similar stacked mounting structure can be realized by using two wiring boards 103 provided in parallel with the opening 103a in which the conductive patterns 104 exposed on both sides are arranged as shown in FIG.
  • a flexible printed wiring board in which copper foil is used as an intermediate wiring layer, both sides are sandwiched between resin insulation layers such as PET and polyimide, and a part of the resin insulation layer is removed from the window has a thickness. Since it is small, it can be suitably used.
  • the wiring board has a conductive pattern exposed on both sides, it can be used regardless of the material and structure as long as the wiring board is preferably a thin wiring board having a conductive pattern at the center in the thickness direction of the board.
  • the periphery of the substrate may have a three-layer structure with a surface wiring layer 107 above and below, a two-layer structure with a surface wiring layer 107 on one side, or an intermediate Even if there is another part where one side or both sides of the wiring layer are exposed.
  • an electrode 105a and a dummy electrode 105b electrically connected to the chip internal circuit 101a are connected to the semiconductor chip 101 along each of a pair of opposite sides.
  • the electrodes 106a and the dummy electrodes 106b that are electrically connected to the chip internal circuit 102a are alternately formed on the semiconductor chip 102 one by one along each pair of opposite sides. It is also possible to use one.
  • a wiring board 103 in which a plurality of conductive patterns 104 exposed on both sides are arranged along each of the four sides facing the rectangular opening 103a is used. Yes.
  • the semiconductor chips 101 and 102 those formed along the four sides so that the electrodes 105 and 106 face the conductor pattern 104 and face each other are used.
  • an electrode 105a electrically connected to the internal circuit 101a is formed along each of the pair of opposite sides, and a dummy electrode 105b is formed along the other pair of opposite sides.
  • an electrode 106a electrically connected to the internal circuit 102a is formed along each of the pair of opposite sides, and a dummy electrode 106b is formed along the other pair of opposite sides.
  • the electrodes electrically connected to the internal circuits of the first and second layer semiconductor chips and the dummy electrodes are alternately arranged one by one or alternately by one side.
  • the internal circuits in the entire area of each semiconductor chip were independently connected to the printed wiring board.
  • the configuration may be applied only to some areas. In other words, circuits (signal lines) that route the first and second layer semiconductor chips independently only in some areas and flow the same signal between the first and second layer semiconductor chips in other areas.
  • An electrode connected to the internal circuit and a dummy electrode may be arranged so that they are electrically connected to each other! /.
  • bus lines address and data
  • chip enable pins wire each signal line independently
  • the structure described above is advantageous. However, even when no dummy electrode is provided, the thickness of the device can be reduced by the chip portion entering the opening 103a of the wiring board 103, and such a structure is also included in the present invention.
  • the electrodes of the first and second semiconductor chips are in contact with both sides of one conductor pattern, and if there are a plurality of such electrodes, At least a part of this is a dummy electrode.
  • semiconductor chips 101 and 102 are stacked and mounted in each of the two openings 103a of the wiring board 103.
  • the arrangement of the conductor patterns 104 in the openings 103a may be as shown in FIG. 7 or as shown in FIG. This semiconductor device can achieve the same thickness as the semiconductor device shown in FIG.
  • a plurality of conductor patterns 104 exposed on both sides are arranged along each of two pairs of opposite sides facing the rectangular opening 103a. It is used.
  • a plurality of electrodes 105 are formed on each side of the four circumferences of the semiconductor chip 111 disposed on one side of the conductor pattern 104 so as to face each conductor pattern 104. (In FIG. 13 (a), part of the electrode 105 is omitted!).
  • semiconductor chips 112 and 113 are arranged in parallel.
  • a plurality of electrodes 106 are formed along the three sides of the semiconductor chips 112, 113 so as to face the electrodes 105 of the semiconductor chip 111, respectively.
  • the semiconductor chip 111 and the semiconductor chips 112 and 113 sandwich the conductor pattern 104 between the electrodes 105 and 106 facing each other. This semiconductor device can achieve the same thickness as the semiconductor device shown in FIG.
  • a plurality of conductor patterns 104 exposed on both sides are arranged in two rows as a wiring board 103 along each of a pair of opposite sides facing the rectangular opening 103a. (The same wiring board as in Fig. 7).
  • a plurality of electrodes 105 facing each of the conductor patterns 104 in one row are formed on the semiconductor chip 121 arranged on one side of the conductor pattern 104.
  • the semiconductor chip 122 arranged on the other side of the conductor pattern 104 has a conductor pattern 104 in the other row.
  • a plurality of electrodes 106 are formed to face each of the electrodes. These semiconductor chips 121 and 122 are formed by sandwiching the conductive pattern 104 in one row between the electrode 105 and the insulating surface of the chip facing the other side, and the insulating pattern of the chip facing the electrode 106 in the other row. They are stacked between the surface.
  • the thickness of the semiconductor device is substantially the sum of the thickness of the chip of the semiconductor chip 121, the electrode 105 or the electrode 106, the conductor pattern 104, and the chip of the semiconductor chip 122. .
  • a further reduction in height can be realized by not providing the dummy electrodes to face each other.
  • a plurality of conductive patterns 104 exposed on both sides are arranged in two rows as a wiring board 103 along each of a pair of opposite sides facing the rectangular opening 103a. (The same wiring board as in Fig. 7).
  • a plurality of electrodes 105 are formed in the vicinity of the outer peripheral edge so as to face each of the conductor patterns 104 in one row, and the other row A plurality of electrodes 105 are formed slightly inside the outer peripheral edge so as to face each of the conductor patterns 104.
  • a plurality of electrodes 106 are formed in the vicinity of the outer periphery so as to face each of the conductor patterns 104 in the other row, and the conductor pattern in one row A plurality of electrodes 106 are formed slightly inside the outer peripheral edge so as to face each of 104.
  • the electrodes 105 and 106 facing the conductor pattern 104 in each row are positioned so as to be aligned in the longitudinal direction of the conductor pattern 104 without facing each other.
  • These semiconductor chips 131 and 132 are laminated such that the conductor patterns 104 in each row are sandwiched between the insulating surfaces of the opposing chips by the electrodes 105 and 106 arranged in the longitudinal direction.
  • the thickness of the semiconductor device is substantially the sum of the thickness of the chip of the semiconductor chip 131, the electrode 105 or the electrode 106, the conductor pattern 104, and the chip of the semiconductor chip 132.
  • a further reduction in height can be realized by the amount of dummy electrodes that do not face each other.
  • the semiconductor device in FIG. 14 it has a larger number of electrodes and is suitable for a semiconductor chip.
  • a plurality of conductor patterns exposed on both sides are used as the wiring substrate 103.
  • An array 104 is used which is arranged along each of two pairs of opposite sides facing the rectangular opening 103a (a wiring board similar to FIG. 11).
  • a plurality of electrodes 105 are formed along each side of the four circumferences of the semiconductor chip 141 arranged on one side of the conductor pattern 104 so as to face each conductor pattern 104 (part of the electrode 105). Is omitted).
  • semiconductor chips 142 and 143 that are slightly smaller than one half of the semiconductor chip 14 1 are arranged in parallel.
  • a plurality of electrodes 106 are formed along the three sides of the semiconductor chips 142 and 143 so as to face the conductor patterns 104, respectively. The electrodes 105 and 106 facing the conductor pattern 104 in each row are positioned so as to be aligned in the longitudinal direction of the conductor pattern 104 without facing each other.
  • These semiconductor chips 142 and 143 are stacked such that the end of the conductor pattern 104 is sandwiched between the electrodes 106 and the insulating surface of the semiconductor chip 141 facing each other.
  • the electrode 105 of the semiconductor chip 141 is formed by the semiconductor chips 142 and 143. Is also connected to the conductor pattern 104 on the outer peripheral side.
  • the thickness of the semiconductor device is substantially the same as that of the semiconductor chip 141, the thickness of the electrode 105 or 106, the thickness of the conductor pattern 104, the semiconductor chip 142 or the semiconductor chip. It is the sum of the chip thickness of 143.
  • a further reduction in height can be achieved by not making the dummy electrodes face each other.
  • the structure is suitable for a semiconductor chip with a larger number of electrodes and a larger number of chips.
  • a semiconductor device (hereinafter referred to as a semiconductor device module) may be configured by stacking the semiconductor devices as described above as one unit.
  • the semiconductor device shown in FIG. 6 (hereinafter referred to as semiconductor device unit U1) and the semiconductor device shown in FIG. 12 (hereinafter referred to as semiconductor device unit U2) will be described as examples.
  • the semiconductor device module Ml shown in FIG. 17 uses a semiconductor device unit U1 and combines the structures shown in FIG. 1 to realize a four-layer stacked structure.
  • the third semiconductor chip 151 is fixed on the semiconductor chip 101 of the semiconductor device unit U1 with the bonding sheet 152 on the back surface opposite to the circuit formation surface, and provided on the circuit formation surface.
  • Electrode 153 printed circuit board for semiconductor device unit U1 1 03 is electrically connected with a conductive wire 154, and a fourth-layer semiconductor chip 155 is mounted on the semiconductor chip 151 with the circuit forming surfaces facing each other and connected with an electrode 156, and sealed with a resin 157. It has stopped.
  • the semiconductor device module M2 shown in FIG. 18 is the same as the semiconductor device module shown in FIG.
  • Ml is laminated in two stages, and the printed wiring boards 103 facing each other are joined together with a bonding sheet 158 to realize an eight-layer laminated structure.
  • the semiconductor device module M3 shown in FIG. 19 is the same as the semiconductor device module shown in FIG. 19
  • M2 is further stacked in two layers to achieve a 16-layer stack structure.
  • a metal ball 159 is interposed between the facing printed wiring boards 103 using an adhesive 160 so that the semiconductor chips of the semiconductor device module M2 do not contact each other.
  • the semiconductor device units U1 are stacked in eight stages, and the printed wiring boards 103 facing each other are bonded together with a bonding sheet 158 to realize a 16-layer stacked structure. Yes.
  • the semiconductor device unit U2 is stacked in eight stages, and the printed wiring boards 103 facing each other are bonded together with a bonding sheet 158 to realize a stacked structure of 16 layers. Yes.
  • the semiconductor device module M6 shown in FIG. 22 uses a semiconductor device unit U2 and realizes a 16-layer stacked structure by combining the structures shown in FIG. A metal ball 159 is interposed between the facing printed wiring boards 103 using an adhesive 160.
  • Each of the semiconductor device modules in FIGS. 20 and 21 in which 16 layers of semiconductor chips are stacked has a total thickness of 1035 ⁇ m and 1065 ⁇ m using an IC chip with a thickness of 30 ⁇ m.
  • the present invention in a semiconductor device having a structure in which two layers of semiconductor chips are stacked on one side of a wiring board in a state where the electrodes are in contact with each other, by providing a dummy electrode, While securing the fixing structure of the semiconductor chip, at least one internal circuit formed in each semiconductor chip is independently separated from the internal circuit cover of the opposing semiconductor chip and electrically connected to the wiring board. It becomes possible to connect to.
  • a dummy electrode is also provided when a conductor portion exposed on both sides is sandwiched between electrodes of two layers of semiconductor chips.
  • the structures are opposed to each other, the internal circuits of the respective semiconductor chips can be independently separated from the opposed semiconductor chips and electrically connected to the wiring board.
  • the electrodes of the two-layer semiconductor chip are provided so as not to oppose each other corresponding to each conductor portion, and when mounting the conductor portion between one or both electrodes and the insulating portion, the dummy electric current is also provided.
  • the internal circuit of each semiconductor chip can be separated from the opposing semiconductor chip independently, and the wiring board is electrically separated by simply reducing the thickness after mounting compared to the structure where the electrodes face each other. Can be connected. This structure is suitable for semiconductor chips with many electrodes!
  • a conductive resin is interposed between the two wiring boards and pressure is applied from both sides to press the respective electrodes to the conductor portion. It can be mounted easily and inexpensively.
  • the semiconductor device of the present invention has a two-layer semiconductor chip stacked on a wiring board and is electrically connected independently. This is useful for the case where semiconductor memories are stacked and mounted.

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Abstract

In a semiconductor device, on one plane of a printed wiring board (1), two layers of semiconductor chips (5, 11) are stacked in a status wherein a plurality of electrodes (7, 8, 13, 14) of the semiconductor chips are brought into contact with each other, the electrodes (7, 8, 13, 14) of either of the semiconductor chips (5, 11) are electrically connected with wiring (2) of the printed wiring board (1) through a conductive wire (9). At least one of the plurality of pairs of electrodes brought into contact with each other, namely, at least one of the pairs of electrodes (7, 13) and electrodes (8, 14) are formed as dummy electrodes wherein one of the electrodes (8, 13) is not electrically connected with internal circuits (6, 12) of the semiconductor chips (5, 11). By the dummy electrodes (8, 13), while ensuring the fixed structure of the two layers of the semiconductor chips (5, 11), the internal circuits (6, 12) of each of the semiconductor chips (5, 11) can be independently separated from the internal circuits (12, 6) of the opposing semiconductor chips (11, 5) and can be electrically connected with the printed wiring board (1).

Description

明 細 書  Specification
半導体装置およびその製造方法  Semiconductor device and manufacturing method thereof
技術分野  Technical field
[0001] 本発明は複数の半導体チップを配線基板上に積層した半導体装置およびその製 造方法に関するものである。  The present invention relates to a semiconductor device in which a plurality of semiconductor chips are stacked on a wiring board, and a manufacturing method thereof.
背景技術  Background art
[0002] 近年、電子部品として半導体パッケージに代えてベアチップが実装されており、実 装面積の大幅縮小が実現されている。ベアチップを配線基板上に実装する工法に は、ワイヤボンディングゃフリップチップボンディングなどがある。実装密度を向上させ るために複数のベアチップを積層する工法も種々提案されている。たとえば、プリント 配線基板の一方の面に 1層目のベアチップ (以下、単に半導体チップという）をフエ 一ストップで固定し、その電極とプリント配線基板とを導電性ワイヤで電気的に接続し 、この 1層目の半導体チップ上に 2層目の半導体チップをフェースダウンで、且つ電 極どうしが接触するように実装する工法がある（たとえば特開平 9— 330952号公報 参照)。  In recent years, bare chips are mounted as electronic components instead of semiconductor packages, and the mounting area has been greatly reduced. Methods for mounting bare chips on a wiring board include wire bonding and flip chip bonding. Various methods for stacking a plurality of bare chips have been proposed in order to improve the packaging density. For example, a first layer bare chip (hereinafter simply referred to as a semiconductor chip) is fixed to one surface of a printed wiring board with a first stop, and the electrode and the printed wiring board are electrically connected with a conductive wire. There is a method of mounting a second-layer semiconductor chip face-down on the first-layer semiconductor chip so that the electrodes are in contact with each other (see, for example, JP-A-9-330952).
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0003] しかし従来の工法では、上述したように 1層目と 2層目の半導体チップを電極どうし が接触する状態で実装するので、各層の半導体チップをそれぞれ独立して配線基 板に電気的に接続することができないという問題がある。 However, in the conventional method, as described above, the first and second layer semiconductor chips are mounted in a state where the electrodes are in contact with each other, so that the semiconductor chips of each layer are electrically connected to the wiring board independently of each other. There is a problem that can not be connected to.
[0004] また半導体チップを積層することで実装面積は小さくなるものの、厚みに関しては、 配線基板とその電極、ボンディングワイヤ、および 2層の半導体チップのそれぞれの 厚みの和となり、配線基板の両面に半導体チップを実装する工法などに比較して優 位性は小さい。 [0004] Although the mounting area is reduced by stacking semiconductor chips, the thickness is the sum of the thicknesses of the wiring board and its electrodes, bonding wires, and two-layer semiconductor chips, and is formed on both sides of the wiring board. The superiority is small compared to the method of mounting semiconductor chips.
[0005] 本発明は上記問題に鑑みてなされたもので、配線基板上に半導体チップを積層す る構造の半導体装置を薄型化すること、また各半導体チップの回路をそれぞれ独立 して配線基板に電気的に接続することを目的とする。 課題を解決するための手段 [0005] The present invention has been made in view of the above problems, and it is possible to reduce the thickness of a semiconductor device having a structure in which semiconductor chips are stacked on a wiring board, and to independently circuit each semiconductor chip on the wiring board. The purpose is to make an electrical connection. Means for solving the problem
[0006] 上記目的を達成するために本発明は、複数の半導体チップが配線基板上に積層 された半導体装置において、前記配線基板の一方の面に 2層の半導体チップが互 V、の複数の電極どうし接触する状態で積層され、 V、ずれかの半導体チップの電極が 導電性ワイヤを介して配線基板の導体部に電気的に接続され、互 、に接触した複数 組の電極の内の少なくとも一部は、一方の電極が、当該電極が属する半導体チップ の内部回路に電気的に接続しないダミー電極として形成されていることを特徴とする  [0006] In order to achieve the above object, the present invention provides a semiconductor device in which a plurality of semiconductor chips are stacked on a wiring board, and a plurality of semiconductor chips having two layers on one surface of the wiring board. The electrodes of the semiconductor chip are stacked in contact with each other, and the electrodes of the V or misaligned semiconductor chip are electrically connected to the conductor portion of the wiring board via the conductive wires, and at least of the plurality of sets of electrodes in contact with each other. In one part, one electrode is formed as a dummy electrode that is not electrically connected to the internal circuit of the semiconductor chip to which the electrode belongs.
[0007] 上記した半導体装置を製造する際には、積層される 2層の半導体チップの内の少 なくとも一方に、内部回路に電気的に接続しないダミー電極を含んだ半導体チップを 用い、前記配線基板の一方の面に第 1層の半導体チップを電極形成面を上にして 搭載し、前記第 1層の半導体チップの各電極と配線基板の導体部とを導電性ワイヤ を介して電気的に接続し、前記第 1層の半導体チップ上に第 2層の半導体チップを、 互いの複数の電極どうし接触するように、かつ前記ダミー電極と内部回路に電気的に 接続した電極とが対向するように、実装することができる。 [0007] When manufacturing the semiconductor device described above, a semiconductor chip including a dummy electrode that is not electrically connected to an internal circuit is used in at least one of two stacked semiconductor chips. A first-layer semiconductor chip is mounted on one side of the wiring board with the electrode formation surface facing up, and each electrode of the first-layer semiconductor chip and the conductor portion of the wiring board are electrically connected via a conductive wire. The dummy electrode and the electrode electrically connected to the internal circuit are opposed to each other so that the second layer semiconductor chip is in contact with the plurality of electrodes on the first layer semiconductor chip. Can be implemented.
[0008] また、本発明の半導体装置は、複数の半導体チップが配線基板上に積層された半 導体装置において、配線基板の一部に両面露出した複数の導体部が形成され、前 記複数の導体部の両側に 2層の半導体チップが電極形成面どうし対向して積層され 、各導体部の少なくとも片面に、対向する半導体チップの電極が接合されていること を特徴とする。  [0008] Further, the semiconductor device of the present invention is a semiconductor device in which a plurality of semiconductor chips are stacked on a wiring board, wherein a plurality of conductor portions exposed on both sides are formed on a part of the wiring board. Two layers of semiconductor chips are laminated opposite to each other on both sides of the conductor portion, and electrodes of the opposing semiconductor chip are bonded to at least one surface of each conductor portion.
[0009] 複数の半導体チップが配線基板上に積層された半導体装置にぉ ヽて、配線基板 の一部に両面露出した複数の導体部が形成され、前記複数の導体部の両側に 2層 の半導体チップが電極形成面どうし対向して積層され、前記 2層の半導体チップは、 複数の電極をそれぞれ有し、互いの電極の間に前記導体部を挟み、前記複数の導 体部を挟んだ複数組の電極の内の少なくとも一部は、一方の電極が、当該電極が属 する半導体チップの内部回路に電気的に接続しないダミー電極として形成されてい ることを特徴とする。  [0009] A semiconductor device in which a plurality of semiconductor chips are stacked on a wiring board is formed with a plurality of conductor parts exposed on both sides of a part of the wiring board, and two layers on both sides of the plurality of conductor parts. Semiconductor chips are stacked opposite to each other, and the two-layer semiconductor chip has a plurality of electrodes, sandwiching the conductor portions between the electrodes, and sandwiching the plurality of conductor portions. At least a part of the plurality of sets of electrodes is characterized in that one electrode is formed as a dummy electrode that is not electrically connected to the internal circuit of the semiconductor chip to which the electrode belongs.
[0010] 複数の半導体チップが配線基板上に積層された半導体装置にぉ ヽて、配線基板 の一部に両面露出した複数の導体部が並列に形成され、前記複数の導体部の両側 に 2層の半導体チップが電極形成面どうし対向して積層され、前記 2層の半導体チッ プは、一方の列の導体部に対向する複数の電極と他方の列の導体部に対向する絶 縁部とをそれぞれ有し、互いの電極と絶縁部との間に導体部を挟んでいることを特徴 とする。 [0010] In a semiconductor device in which a plurality of semiconductor chips are stacked on a wiring board, the wiring board A plurality of conductor portions exposed on both sides are formed in parallel, and two layers of semiconductor chips are stacked on both sides of the plurality of conductor portions so as to face each other on the electrode formation surface. It has a plurality of electrodes facing the conductor part of one row and an insulating part facing the conductor part of the other row, and the conductor portion is sandwiched between each electrode and the insulating portion. And
[0011] 複数の半導体チップが配線基板上に積層された半導体装置において、配線基板 の一部に両面露出した複数の導体部が並列に形成され、前記複数の導体部の両側 に 2層の半導体チップが電極形成面どうし対向して積層され、前記 2層の半導体チッ プは、各列の導体部に対向する複数の電極と絶縁部とを各導体部に対応してそれ ぞれ有し、互いの電極と絶縁部との間に導体部を挟み、前記複数の導体部に両側か ら接触した複数組の電極の内の少なくとも一部は、一方の電極が、当該電極が属す る半導体チップの内部回路に電気的に接続しないダミー電極として形成されているこ とを特徴とする。  In a semiconductor device in which a plurality of semiconductor chips are stacked on a wiring substrate, a plurality of conductor portions exposed on both sides are formed in parallel on a part of the wiring substrate, and two layers of semiconductors are formed on both sides of the plurality of conductor portions. The chips are stacked opposite to each other on the electrode forming surfaces, and the two-layer semiconductor chip has a plurality of electrodes facing each conductor portion of each row and an insulating portion corresponding to each conductor portion, At least a part of a plurality of sets of electrodes that are in contact with the plurality of conductor portions from both sides with a conductor portion sandwiched between the electrodes and the insulating portion is a semiconductor chip to which one electrode belongs. It is characterized by being formed as a dummy electrode that is not electrically connected to the internal circuit.
[0012] 複数の半導体チップが配線基板上に積層された半導体装置にぉ ヽて、配線基板 の一部に両面露出した複数の導体部が並列に形成され、前記複数の導体部の両側 に 2層の半導体チップが電極形成面どうし対向して積層され、第 1層の半導体チップ は、各列の導体部に対向する複数の電極と絶縁部とを各導体部に対応して有し、第 2層の半導体チップは、前記第 1層の半導体チップの絶縁部に対向する複数の電極 を有し、前記第 1層および第 2層の半導体チップが互いに対向する電極と絶縁部との 間に導体部を挟み、かつ第 1層の半導体チップの電極が導体部に接合し、前記複数 の導体部に両側から接触した複数組の電極の内の少なくとも一部は、一方の電極が 、当該電極が属する半導体チップの内部回路に電気的に接続しな ヽダミー電極とし て形成されて ヽることを特徴とする。  [0012] In a semiconductor device in which a plurality of semiconductor chips are stacked on a wiring substrate, a plurality of conductor portions exposed on both sides are formed in parallel on a part of the wiring substrate, and two conductor portions are formed on both sides of the plurality of conductor portions. The semiconductor chips of the layers are stacked so as to face each other on the electrode forming surfaces, and the semiconductor chip of the first layer has a plurality of electrodes opposed to the conductor portions of each row and an insulating portion corresponding to each conductor portion, The two-layer semiconductor chip has a plurality of electrodes facing the insulating portion of the first-layer semiconductor chip, and the first-layer semiconductor chip and the second-layer semiconductor chip are between the electrodes facing each other and the insulating portion. At least a part of the plurality of sets of electrodes sandwiching the conductor portion and in which the electrode of the first layer semiconductor chip is joined to the conductor portion and is in contact with the plurality of conductor portions from both sides, one electrode is the electrodeヽ Dummy electrode not electrically connected to the internal circuit of the semiconductor chip to which the Wherein the Ru is formed to.
[0013] 両面露出した複数の導体部が配線基板の中間配線層の一部であるのが好都合で ある。また両面露出した複数の導体部が配線基板に形成された単一の開口内にある のが好都合である。単一の半導体チップに対して複数の半導体チップが並列に積層 されていてよい。  [0013] Conveniently, the plurality of conductor portions exposed on both sides are part of the intermediate wiring layer of the wiring board. Further, it is convenient that the plurality of conductor portions exposed on both sides are in a single opening formed in the wiring board. A plurality of semiconductor chips may be stacked in parallel to a single semiconductor chip.
[0014] 上記した各半導体装置を製造する際には、配線基板に両面露出した複数の導体 部の両側に導電性榭脂層を介して 2層の半導体チップを電極形成面どうし対向させ て配置し、前記 2層の半導体チップを両側から加圧してそれぞれの電極を前記導体 部に圧着させることができる。 When manufacturing each of the semiconductor devices described above, a plurality of conductors exposed on both sides of the wiring board Two layers of semiconductor chips are arranged opposite to each other on both sides of the electrode with a conductive resin layer, and the two layers of semiconductor chips are pressed from both sides to crimp each electrode to the conductor. be able to.
[0015] 上記した各半導体装置において、半導体チップカ モリ ICチップであってよい。 [0015] Each of the semiconductor devices described above may be a semiconductor chip memory IC chip.
[0016] 上記したいずれかの半導体装置を複数段に積層した半導体装置モジュールも本 発明の一部を構成する。 [0016] A semiconductor device module in which any of the semiconductor devices described above is stacked in a plurality of stages also forms a part of the present invention.
発明の効果  The invention's effect
[0017] 本発明によれば、配線基板の片側に 2層の半導体チップを電極どうし接触する状 態で積層する構造の半導体装置にダミー電極を設けることにより、 2層の半導体チッ プの固定構造は確保しながら、各半導体チップに少なくとも 1つ形成される内部回路 をそれぞれ独立して、対向する半導体チップの内部回路力も分離して、配線基板に 電気的に接続することが可能となる。  [0017] According to the present invention, a two-layer semiconductor chip fixing structure is provided by providing a dummy electrode in a semiconductor device having a structure in which two layers of semiconductor chips are stacked in contact with each other on one side of a wiring board. In this way, at least one internal circuit formed on each semiconductor chip can be independently connected, and the internal circuit force of the opposing semiconductor chip can be separated and electrically connected to the wiring board.
[0018] 2層の半導体チップを配線基板の両側に積層する構造の半導体装置にぉ 、ても、 両面露出した導体部の両側に 2層の半導体チップの電極を接触させる場合には、ダ ミー電極を設けることにより、各半導体チップの内部回路をそれぞれ独立して、対向 する半導体チップ力も分離して、配線基板に電気的に接続させることが可能となる。  [0018] In a semiconductor device having a structure in which two layers of semiconductor chips are stacked on both sides of a wiring board, if the electrodes of the two layers of semiconductor chips are brought into contact with both sides of a conductor portion exposed on both sides, a dummy is used. By providing the electrodes, the internal circuits of the respective semiconductor chips can be independently connected to each other, and the opposing semiconductor chip forces can be separated and electrically connected to the wiring board.
[0019] 2層の半導体チップを互いの電極と絶縁部との間に導体部を挟んで実装する場合 には、電極どうし対向する構造よりも実装後の厚みが薄くなる。  [0019] When a two-layer semiconductor chip is mounted with the conductor portion sandwiched between the electrodes and the insulating portion, the thickness after mounting becomes thinner than the structure in which the electrodes face each other.
[0020] 両面露出した導体部が配線基板の中間配線層の一部であるときや、配線基板の単 一の開口内にあるときには、半導体チップが配線基板の表面よりも内側へ入り込むの で、実装後の厚みがより薄くなる。  [0020] When the conductor portion exposed on both sides is a part of the intermediate wiring layer of the wiring board or in a single opening of the wiring board, the semiconductor chip enters inside the surface of the wiring board. The thickness after mounting becomes thinner.
[0021] 2層の半導体チップを配線基板の両側に積層する際には、配線基板との間に導電 性榭脂を介在させておき、両側から加圧してそれぞれの電極を導体部に圧着させる だけでよぐ容易にかつ安価に実装できる。  [0021] When two-layer semiconductor chips are stacked on both sides of the wiring board, conductive grease is interposed between the two wiring boards, and pressure is applied from both sides to crimp each electrode to the conductor portion. It can be mounted easily and inexpensively.
図面の簡単な説明  Brief Description of Drawings
[0022] [図 1]本発明の一実施形態における半導体装置の断面図 FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
[図 2]図 1の同半導体装置の製造途中の断面図  [Fig. 2] Cross-sectional view of the semiconductor device shown in Fig. 1 during manufacturing
[図 3]図 1で示される断面を有した第 1例の半導体装置の分解斜視図 圆 4]図 1で示される断面を有した第 2例の半導体装置の分解斜視図FIG. 3 is an exploded perspective view of the first example semiconductor device having the cross section shown in FIG. 4] An exploded perspective view of the second example semiconductor device having the cross section shown in FIG.
[図 5]本発明の他の実施形態における半導体装置の断面図 FIG. 5 is a sectional view of a semiconductor device according to another embodiment of the present invention.
[図 6]本発明のさらに他の実施形態における半導体装置の断面図  FIG. 6 is a sectional view of a semiconductor device according to still another embodiment of the present invention.
[図 7]図 6の半導体装置の分解斜視図  FIG. 7 is an exploded perspective view of the semiconductor device of FIG.
[図 8]図 6の半導体装置の製造方法を説明する工程断面図  8 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device in FIG.
[図 9]図 6の半導体装置に用いられる他の配線基板の構成を示す斜視図  FIG. 9 is a perspective view showing the configuration of another wiring board used in the semiconductor device of FIG.
[図 10]図 6で示される断面を有した第 1例の半導体装置の分解斜視図  10 is an exploded perspective view of the first example semiconductor device having the cross section shown in FIG.
[図 11]図 6で示される断面を有した第 2例の半導体装置の分解斜視図  FIG. 11 is an exploded perspective view of the second example semiconductor device having the cross section shown in FIG.
[図 12]本発明のさらに他の実施形態における半導体装置の断面図  FIG. 12 is a sectional view of a semiconductor device according to still another embodiment of the present invention.
[図 13]本発明のさらに他の実施形態における半導体装置の断面図および分解斜視 図  FIG. 13 is a cross-sectional view and an exploded perspective view of a semiconductor device according to still another embodiment of the present invention.
[図 14]本発明のさらに他の実施形態における半導体装置の断面図  FIG. 14 is a sectional view of a semiconductor device according to still another embodiment of the present invention.
[図 15]本発明のさらに他の実施形態における半導体装置の断面図  FIG. 15 is a sectional view of a semiconductor device according to still another embodiment of the present invention.
[図 16]本発明のさらに他の実施形態における半導体装置の断面図  FIG. 16 is a cross-sectional view of a semiconductor device according to still another embodiment of the present invention.
[図 17]図 6に示した半導体装置を用いた半導体装置モジュールの断面図  FIG. 17 is a sectional view of a semiconductor device module using the semiconductor device shown in FIG.
[図 18]図 6に示した半導体装置を用いた他の半導体装置モジュールの断面図  18 is a cross-sectional view of another semiconductor device module using the semiconductor device shown in FIG.
[図 19]図 6に示した半導体装置を用いたさらに他の半導体装置モジュールの断面図 FIG. 19 is a cross-sectional view of still another semiconductor device module using the semiconductor device shown in FIG.
[図 20]図 6に示した半導体装置を用いたさらに他の半導体装置モジュールの断面図20 is a cross-sectional view of still another semiconductor device module using the semiconductor device shown in FIG.
[図 21]図 12に示した半導体装置を用いた半導体装置モジュールの断面図 FIG. 21 is a cross-sectional view of a semiconductor device module using the semiconductor device shown in FIG.
[図 22]図 12に示した半導体装置を用いた他の半導体装置モジュールの断面図 発明を実施するための最良の形態  22 is a cross-sectional view of another semiconductor device module using the semiconductor device shown in FIG. 12. BEST MODE FOR CARRYING OUT THE INVENTION
[0023] 以下、本発明の実施の形態について図面を参照しながら説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0024] 図 1に示す半導体装置では、プリント配線基板 1上に 2層の半導体チップ 5, 11が 積層して実装されている。 In the semiconductor device shown in FIG. 1, two layers of semiconductor chips 5 and 11 are stacked and mounted on a printed wiring board 1.
[0025] 詳細には、表面に配線 2が形成されたプリント配線基板 1の一方の面に、 1層目の 半導体チップ 5がその回路 6および電極 7、 8に背反する背面において接着材 4を介 して固定され、電極 7、 8上に形成された導電性突起 7a, 8aとプリント配線基板 1の配 線 2のパッド電極（図示せず）とがそれぞれ、導電性ワイヤ 9により電気的に接続され ている。 [0025] Specifically, the adhesive 4 is provided on one surface of the printed wiring board 1 having the wiring 2 formed on the front surface, on the back surface where the first-layer semiconductor chip 5 is opposite to the circuit 6 and the electrodes 7 and 8. The conductive protrusions 7a and 8a formed on the electrodes 7 and 8 and the pad electrode (not shown) of the wiring 2 of the printed wiring board 1 are electrically connected by the conductive wires 9, respectively. Connected ing.
[0026] 1層目の半導体チップ 5の上に、 2層目の半導体チップ 11がその回路 12および電 極 13、 14が 1層目の半導体チップ 5の回路形成面に対向する向きで、かつ電極 13、 14の上に形成された導電性突起 13a, 14aがそれぞれ 1層目の半導体チップ 5の電 極 7、 8上の導電性突起 7a, 8aに接触した状態で実装されている。半導体チップ 5, 11の間および周囲は榭脂で封止されて 、る (後述する図 17参照)。  [0026] On the semiconductor chip 5 of the first layer, the semiconductor chip 11 of the second layer has its circuit 12 and the electrodes 13 and 14 facing the circuit formation surface of the semiconductor chip 5 of the first layer, and The conductive protrusions 13a and 14a formed on the electrodes 13 and 14 are mounted in contact with the conductive protrusions 7a and 8a on the electrodes 7 and 8 of the first-layer semiconductor chip 5, respectively. Between and around the semiconductor chips 5 and 11 are sealed with grease (see FIG. 17 described later).
[0027] 1層目の半導体チップ 5においては、電極 7は回路 15を介して回路 6に電気的に接 続されて!、るが、電極 8は回路 6とは電気的に接続されて ヽな 、ダミー電極 (見せか けの電極）である。 2層目の半導体チップ 11においては、電極 14は回路 16を介して 回路 12に電気的に接続されて!ヽるが、電極 13は回路 12とは電気的に接続されて!ヽ ないダミー電極である。  In the first-layer semiconductor chip 5, the electrode 7 is electrically connected to the circuit 6 through the circuit 15!, But the electrode 8 is electrically connected to the circuit 6. It is a dummy electrode (shown electrode). In the semiconductor chip 11 of the second layer, the electrode 14 is electrically connected to the circuit 12 through the circuit 16, but the electrode 13 is electrically connected to the circuit 12 and is not a dummy electrode. It is.
[0028] このため、 1層目の半導体チップ 5の回路 6は、回路 15と電極 7,導電性突起 7aと 導電性ワイヤ 9とを介してプリント配線基板 1の図中の右側の配線 2に電気的に接続 されており、回路 6とプリント配線基板 1の左側の配線 2との間には電気的導通はない 。 2層目の半導体チップ 11の回路 12は、回路 16と電極 14,導電性突起 14aと導電 性ワイヤ 9とを介してプリント配線基板 1の左側の配線 2に電気的に接続されており、 回路 12とプリント配線基板 1の右側の配線 2との間には電気的導通はない。つまり、 積層された半導体チップ 5, 11のそれぞれの回路 6, 12がプリント配線基板 1に対し て独立して電気的に接続された構造である。  [0028] For this reason, the circuit 6 of the semiconductor chip 5 in the first layer is connected to the wiring 2 on the right side of the printed wiring board 1 through the circuit 15, the electrode 7, the conductive protrusion 7a, and the conductive wire 9. They are electrically connected and there is no electrical continuity between the circuit 6 and the wiring 2 on the left side of the printed wiring board 1. The circuit 12 of the second-layer semiconductor chip 11 is electrically connected to the wiring 2 on the left side of the printed wiring board 1 through the circuit 16, the electrode 14, the conductive protrusion 14a, and the conductive wire 9. There is no electrical continuity between 12 and the wiring 2 on the right side of the printed circuit board 1. In other words, the circuits 6 and 12 of the stacked semiconductor chips 5 and 11 are electrically connected to the printed wiring board 1 independently.
[0029] この半導体装置を製造する際には、図 2に示すように、プリント配線基板 1の一方の 面に半導体チップ 5を電極形成面を上にして搭載し、次 ヽで半導体チップ 5の各電 極 7, 8とプリント配線基板 1の配線 2とを導電性ワイヤ 9により電気的に接続し、その 後に、半導体チップ 5上に、半導体チップ 5の各電極 7, 8と対をなす配置で電極 13, 14が形成された半導体チップ 11を、ダミー電極 8, 13と内部回路に電気的に接続し た電極 7, 14とが対向するように、互いの複数の電極どうし接触させて実装する。  When manufacturing this semiconductor device, as shown in FIG. 2, the semiconductor chip 5 is mounted on one surface of the printed wiring board 1 with the electrode formation surface facing up, and then the semiconductor chip 5 is Each electrode 7, 8 and the wiring 2 of the printed wiring board 1 are electrically connected by the conductive wire 9, and then placed on the semiconductor chip 5 to make a pair with each electrode 7, 8 of the semiconductor chip 5. The semiconductor chip 11 on which the electrodes 13 and 14 are formed is mounted in contact with each other so that the dummy electrodes 8 and 13 and the electrodes 7 and 14 electrically connected to the internal circuit face each other. To do.
[0030] 図 3は、図 1で示される断面を有した半導体装置の第 1例であって、 2層目の半導体 チップ 11を実装する前の状態を示す。導電性突起（7a, 8a, 13a, 14a)の図示は省 略している。ただし導電性突起（7a, 8a, 13a, 14a)は必須でない。 [0031] 半導体チップ 5と半導体チップ 11とは同一の構造を有している。半導体チップ 5で は、隣り合わない一対の辺のそれぞれに沿って電極 7と電極 8とが交互に形成され、 半導体チップ 11では、隣り合わない一対の辺のそれぞれに沿って電極 13と電極 14 とが交互に形成されている。電極 8, 13が、それぞれが属する半導体チップ 5, 11の 回路 6, 12に接続しないダミー電極である。 FIG. 3 shows a first example of the semiconductor device having the cross section shown in FIG. 1, and shows a state before the second-layer semiconductor chip 11 is mounted. The conductive protrusions (7a, 8a, 13a, 14a) are not shown. However, the conductive protrusions (7a, 8a, 13a, 14a) are not essential. [0031] The semiconductor chip 5 and the semiconductor chip 11 have the same structure. In the semiconductor chip 5, the electrodes 7 and 8 are alternately formed along a pair of non-adjacent sides. In the semiconductor chip 11, the electrodes 13 and 14 are formed along a pair of non-adjacent sides. And are formed alternately. The electrodes 8 and 13 are dummy electrodes that are not connected to the circuits 6 and 12 of the semiconductor chips 5 and 11 to which they belong, respectively.
[0032] 半導体チップ 11を図示した状態から表裏を反転させて実装すると、図 1に示したよ うな、半導体チップ 5の電極 8が半導体チップ 11の電極 14に接触し、半導体チップ 5 の電極 7が半導体チップ 11の電極 13に接触する状態となり、電極 8,電極 13がダミ 一電極であることから、 1層目の半導体チップ 5の回路 6と 2層目の半導体チップ 11の 回路 12とがプリント配線基板 1に対して完全に独立した接続状態となる。  When the semiconductor chip 11 is mounted upside down from the illustrated state, the electrode 8 of the semiconductor chip 5 comes into contact with the electrode 14 of the semiconductor chip 11 and the electrode 7 of the semiconductor chip 5 is connected as shown in FIG. Since it is in contact with the electrode 13 of the semiconductor chip 11 and the electrodes 8 and 13 are single electrodes, the circuit 6 of the first semiconductor chip 5 and the circuit 12 of the second semiconductor chip 11 are printed. It becomes a completely independent connection state with respect to the wiring board 1.
[0033] 図 4は、図 1で示される断面を有した半導体装置の第 2例であって、 2層目の半導体 チップ 11を実装する前の状態を示す。導電性突起（7a, 8a, 13a, 14a)の図示は省 略している。  FIG. 4 is a second example of the semiconductor device having the cross section shown in FIG. 1, and shows a state before the second-layer semiconductor chip 11 is mounted. The conductive protrusions (7a, 8a, 13a, 14a) are not shown.
[0034] 半導体チップ 5と半導体チップ 11とは同一の構造を有している。半導体チップ 5で は、隣り合わない一対の辺のそれぞれに沿って電極 7が形成され、もう一対の辺のそ れぞれに沿って電極 8が形成されている。半導体チップ 11では、隣り合わない一対 の辺のそれぞれに沿って電極 13が形成され、もう一対の辺のそれぞれに沿って電極 14が形成されている。電極 8, 13が、それぞれが属する半導体チップ 5, 11の回路 6 , 12に接続しないダミー電極である。  The semiconductor chip 5 and the semiconductor chip 11 have the same structure. In the semiconductor chip 5, an electrode 7 is formed along each of a pair of sides that are not adjacent to each other, and an electrode 8 is formed along each of the other pair of sides. In the semiconductor chip 11, an electrode 13 is formed along each of a pair of sides that are not adjacent to each other, and an electrode 14 is formed along each of the other pair of sides. The electrodes 8 and 13 are dummy electrodes that are not connected to the circuits 6 and 12 of the semiconductor chips 5 and 11 to which they belong, respectively.
[0035] 半導体チップ 11を図示した状態から表裏を反転させて実装すると、図 1に示したよ うな、半導体チップ 5の電極 8が半導体チップ 11の電極 14に接触し、半導体チップ 5 の電極 7が半導体チップ 11の電極 13に接触する状態となり、電極 8,電極 13がダミ 一電極であることから、 1層目の半導体チップ 5の回路 6と 2層目の半導体チップ 11の 回路 12とがプリント配線基板 1に対して完全に独立した接続状態となる。  When the semiconductor chip 11 is mounted upside down from the illustrated state, the electrode 8 of the semiconductor chip 5 comes into contact with the electrode 14 of the semiconductor chip 11 and the electrode 7 of the semiconductor chip 5 is connected as shown in FIG. Since it is in contact with the electrode 13 of the semiconductor chip 11 and the electrodes 8 and 13 are single electrodes, the circuit 6 of the first semiconductor chip 5 and the circuit 12 of the second semiconductor chip 11 are printed. It becomes a completely independent connection state with respect to the wiring board 1.
[0036] なお図 1から図 4に示した半導体装置では、 1対の半導体チップ 5, 11を積層した 構造について説明した力 図 5に示したように、もう 1対の半導体チップ 5, 11を積層 した構造や、さらに多段に積層した構造も可能である。  In the semiconductor device shown in FIG. 1 to FIG. 4, the force for explaining the structure in which the pair of semiconductor chips 5 and 11 are stacked, as shown in FIG. Layered structures and multi-layered structures are also possible.
[0037] また図 1から図 4に示した半導体装置では、ダミー電極と回路接続電極とを 1個ずつ 交互にあるいは 1辺ずつ交互に配置した力 一部領域にダミー電極を配置して、その 領域でのみ 2つの半導体チップを独立して配線し、他の領域では同一信号を流す回 路 (信号ライン)どうし互いに導通させてもょ 、。 [0037] Also, in the semiconductor device shown in FIGS. 1 to 4, one dummy electrode and one circuit connection electrode are provided. A force that alternately or alternately arranges one side at a time A dummy electrode is placed in a part of the area, two semiconductor chips are wired independently only in that area, and a circuit that passes the same signal in other areas (signal line) ) Let's make each other conductive.
[0038] たとえば半導体メモリでは、バスライン (アドレス及びデータ）のように上下の半導体 チップで接続できる信号ラインもある力 チップィネーブルピンのように上下の半導体 チップで接続できな ヽ信号ラインが存在し、その場合は各信号ラインを独立して配線 する必要があるので、上記した構造が好都合である。  [0038] For example, in a semiconductor memory, there are signal lines that can be connected by upper and lower semiconductor chips such as bus lines (address and data). There are signal lines that cannot be connected by upper and lower semiconductor chips such as chip enable pins. In this case, however, the above-described structure is advantageous because each signal line needs to be wired independently.
[0039] 図 6に示す半導体装置は、 2層の半導体チップ 101, 102を電極形成面どうし対向 させて、プリント配線基板 103 (以下、単に配線基板 103という）の両面露出した導体 パターン 104の両側に配置し、それぞれの半導体チップ 101, 102のバンプ電極 10 5, 106 (以下、単に電極 105, 106という）を導体パターン 104の対向面に接合させ た積層構造である。図中の 101c, 102cは電極パッドである。  The semiconductor device shown in FIG. 6 has two layers of semiconductor patterns 101 and 102 facing each other on the electrode formation surface, and both sides of a conductive pattern 104 exposed on both sides of a printed wiring board 103 (hereinafter simply referred to as wiring board 103). The bump electrodes 105 and 106 (hereinafter simply referred to as electrodes 105 and 106) of the semiconductor chips 101 and 102 are bonded to the opposing surface of the conductor pattern 104, respectively. 101c and 102c in the figure are electrode pads.
[0040] 詳細には、図 7にも示すように、配線基板 103には矩形の開口 103aが形成されて おり、中間配線層の一部である複数の導体パターン 104が、開口 103aに臨んだ一 対の対辺のそれぞれに沿って適当
Figure imgf000010_0001
、る。各列の導体パターン 104は、 開口 103aの周囲領域では上下の表面配線層 107,絶縁層 107aに挟まれて基板厚 み方向における中央部にあり、先端どうしが対向する向きに延びたフライングリード構 造である。 Specifically, as shown in FIG. 7, a rectangular opening 103a is formed in the wiring board 103, and a plurality of conductor patterns 104 that are part of the intermediate wiring layer face the opening 103a. Appropriate along each of a pair of opposite sides
Figure imgf000010_0001
RU The conductor pattern 104 in each row is located in the center of the substrate thickness direction between the upper and lower surface wiring layers 107 and the insulating layer 107a in the region around the opening 103a, and the flying lead structure extending in the direction in which the tips face each other. It is made.
[0041] 半導体チップ 101, 102は、配線基板 103の開口 103aよりも外形寸法が小さく形 成されており、それぞれの一対の対辺に沿って複数の電極 105, 106力 互いに対 向し且つ導体パターン 104に対向するように形成されていて、各導体パターン 104を 互いの電極 105, 106間に挟んで実装されている。電極 105と導体パターン 104と電 極 106との接合並びにその周囲の榭脂封止は異方性導電榭脂 108によって行われ ている。  [0041] The semiconductor chips 101, 102 are formed to have an outer dimension smaller than the opening 103a of the wiring board 103, and a plurality of electrodes 105, 106 are opposed to each other along each pair of opposite sides and are conductive patterns. The conductive pattern 104 is formed so as to be opposed to the conductive pattern 104 and sandwiched between the electrodes 105 and 106. Bonding of the electrode 105, the conductor pattern 104, and the electrode 106 and sealing of the surrounding resin are performed by an anisotropic conductive resin 108.
[0042] 半導体チップ 101においては、一方の辺に沿って並んだ電極 105aはチップ内部 回路 101aに回路 101bを介して電気的に接続されている力 もう一方の辺に沿って 並んだ電極 105bはチップ内部回路 101aとは電気的に接続されていないダミー電極 (見せかけの電極）である。半導体チップ 102においては、一方の辺に沿って並んだ 電極 106aはチップ内部回路 102aに回路 102bを介して電気的に接続されているが 、もう一方の辺に沿って並んだ電極 106bはチップ内部回路 102aとは電気的に接続 されて!/ヽな ヽダミー電極である。 In the semiconductor chip 101, the electrodes 105a arranged along one side are electrically connected to the chip internal circuit 101a via the circuit 101b. The electrodes 105b arranged along the other side are The chip internal circuit 101a is a dummy electrode (fake electrode) that is not electrically connected. In the semiconductor chip 102, they are arranged along one side. The electrode 106a is electrically connected to the chip internal circuit 102a via the circuit 102b. However, the electrode 106b arranged along the other side is electrically connected to the chip internal circuit 102a! It is a dummy electrode.
[0043] このため、半導体チップ 101のチップ内部回路 101aは電極 105aを通して所定の 導体パターン 104に電気的に接続される一方で、半導体チップ 102のチップ内部回 路 102aは電極 106aを通して所定の導体パターン 104に電気的に接続されている。 つまり、積層実装された半導体チップ 101 , 102のそれぞれの内部回路 101a, 102 aは各電極 105a, 106aを通してプリント配線基板 101に対して独立して電気的に接 続されている。 [0043] Therefore, the chip internal circuit 101a of the semiconductor chip 101 is electrically connected to the predetermined conductor pattern 104 through the electrode 105a, while the chip internal circuit 102a of the semiconductor chip 102 is electrically connected to the predetermined conductor pattern 104 through the electrode 106a. 104 is electrically connected. That is, the internal circuits 101a and 102a of the semiconductor chips 101 and 102 mounted in a stacked manner are electrically connected independently to the printed wiring board 101 through the electrodes 105a and 106a.
[0044] この半導体装置を製造する際には、図 8 (a)に示すように、配線基板 103の開口 10 3aとほぼ同等サイズのシート状異方性導電榭脂 108を導体パターン 104の両側に貼 り付け、図 8 (b)に示すように、異方性導電榭脂 108の両表面に半導体チップ 101, 1 02を仮置きし、図 8 (c)に示すように、半導体チップ 101, 102を両側から加圧して同 時に導体パターン 104に圧着させる。  When manufacturing this semiconductor device, as shown in FIG. 8 (a), as shown in FIG. 8 (a), a sheet-like anisotropic conductive resin 108 having a size substantially equal to the opening 103 3 a of the wiring substrate 103 is formed on both sides of the conductor pattern 104. As shown in FIG. 8 (b), the semiconductor chips 101, 102 are temporarily placed on both surfaces of the anisotropic conductive resin 108, and as shown in FIG. , 102 are pressed from both sides and pressed against the conductor pattern 104 at the same time.
[0045] 完成品としての半導体装置の厚みは、半導体チップ 101のチップ厚みおよび電極 厚み、半導体チップ 102のチップ厚みおよび電極厚み、導体パターン 104の厚みの 和となる。半導体チップ 101, 102の電極 105, 106の厚み力 S小さいときには、図示し たように、チップ部分が配線基板 103の開口 103aに入り込む。したがって、配線基 板の片面に半導体チップを積層する従来の半導体装置と比べて大幅に厚みを低減 できる。この構造は、半導体装置全体の厚みを一定値より抑えることが要求される場 合に、より多数の半導体チップを積層できるため非常に有利である。  [0045] The thickness of the semiconductor device as a finished product is the sum of the chip thickness and electrode thickness of the semiconductor chip 101, the chip thickness and electrode thickness of the semiconductor chip 102, and the thickness of the conductor pattern 104. When the thickness force S of the electrodes 105, 106 of the semiconductor chips 101, 102 is small, the chip portion enters the opening 103a of the wiring substrate 103 as shown in the figure. Therefore, the thickness can be greatly reduced as compared with a conventional semiconductor device in which a semiconductor chip is stacked on one side of a wiring board. This structure is very advantageous because a larger number of semiconductor chips can be stacked when the thickness of the entire semiconductor device is required to be kept below a certain value.
[0046] 図 9に示すような、両面露出した導体パターン 104が並んだ開口 103a力並列に 2 個設けられた配線基板 103を用いても、同様の積層実装構造を実現できる。  A similar stacked mounting structure can be realized by using two wiring boards 103 provided in parallel with the opening 103a in which the conductive patterns 104 exposed on both sides are arranged as shown in FIG.
[0047] 配線基板 103としては、銅箔を中間配線層として両側を PETやポリイミドなどの榭 脂絶縁層で挟み、その榭脂絶縁層の一部を窓抜きしたフレキシブルプリント配線基 板が厚みが小さいため好適に使用できる。し力 両面露出した導体パターンを備え た配線基板であれば、望ましくは導体パターンを基板厚み方向における中央部に備 えた薄型の配線基板であれば、材料や構造に関わらず使用可能である。開口 103a の周囲は、各図に示したように上下に表面配線層 107を備えた 3層構造であってもよ いし、片側に表面配線層 107を備えた 2層構造であってもよいし、中間配線層の片面 あるいは両面が露出された部分が他にあってもょ 、。 [0047] As the wiring substrate 103, a flexible printed wiring board in which copper foil is used as an intermediate wiring layer, both sides are sandwiched between resin insulation layers such as PET and polyimide, and a part of the resin insulation layer is removed from the window has a thickness. Since it is small, it can be suitably used. As long as the wiring board has a conductive pattern exposed on both sides, it can be used regardless of the material and structure as long as the wiring board is preferably a thin wiring board having a conductive pattern at the center in the thickness direction of the board. Opening 103a As shown in each figure, the periphery of the substrate may have a three-layer structure with a surface wiring layer 107 above and below, a two-layer structure with a surface wiring layer 107 on one side, or an intermediate Even if there is another part where one side or both sides of the wiring layer are exposed.
[0048] 半導体チップについても、図 10に示すように、半導体チップ 101に、チップ内部回 路 101aに電気的に接続した電極 105aとダミー電極 105bとが一対の対辺のそれぞ れに沿って 1個ずつ交互に形成されたものを用い、また半導体チップ 102に、チップ 内部回路 102aに電気的に接続した電極 106aとダミー電極 106bとが一対の対辺の それぞれに沿って 1個ずつ交互に形成されたものを用いることも可能である。  Also for the semiconductor chip, as shown in FIG. 10, an electrode 105a and a dummy electrode 105b electrically connected to the chip internal circuit 101a are connected to the semiconductor chip 101 along each of a pair of opposite sides. The electrodes 106a and the dummy electrodes 106b that are electrically connected to the chip internal circuit 102a are alternately formed on the semiconductor chip 102 one by one along each pair of opposite sides. It is also possible to use one.
[0049] 図 11に示す半導体装置では、配線基板 103として、両面露出した複数の導体バタ ーン 104が矩形の開口 103aに臨んだ 4辺のそれぞれに沿って配列されたものが用 いられている。また半導体チップ 101, 102として、それぞれの電極 105, 106が導体 パターン 104に対向するように且つ互いに対向するように、 4辺のそれぞれに沿って 形成されたものが用いられている。半導体チップ 101においては、一対の対辺のそ れぞれに沿って、内部回路 101aに電気的に接続した電極 105aが形成され、もう一 対の対辺に沿ってダミー電極 105bが形成されている。半導体チップ 102においては 、一対の対辺のそれぞれに沿って、内部回路 102aに電気的に接続した電極 106a が形成され、もう一対の対辺に沿ってダミー電極 106bが形成されている。  In the semiconductor device shown in FIG. 11, a wiring board 103 in which a plurality of conductive patterns 104 exposed on both sides are arranged along each of the four sides facing the rectangular opening 103a is used. Yes. As the semiconductor chips 101 and 102, those formed along the four sides so that the electrodes 105 and 106 face the conductor pattern 104 and face each other are used. In the semiconductor chip 101, an electrode 105a electrically connected to the internal circuit 101a is formed along each of the pair of opposite sides, and a dummy electrode 105b is formed along the other pair of opposite sides. In the semiconductor chip 102, an electrode 106a electrically connected to the internal circuit 102a is formed along each of the pair of opposite sides, and a dummy electrode 106b is formed along the other pair of opposite sides.
[0050] 以上説明した各半導体装置では、第 1層と第 2層の半導体チップにそれぞれの内 部回路に電気的に接続した電極とダミー電極とを 1個ずつ交互にあるいは 1辺ずつ 交互に配置することで、導体パターンの両側に接触する 2電極の内の一方をダミー 電極として、各半導体チップの全領域の内部回路をそれぞれ、プリント配線基板に対 して独立して接続したが、この構成を、一部領域にのみ適用してもよい。つまり、一部 領域でのみ第 1層と第 2層の半導体チップを独立して配線し、他の領域では第 1層と 第 2層の半導体チップで同一信号を流す回路 (信号ライン)どうしが互いに導通する ように、内部回路に接続した電極とダミー電極とを配置してもよ!/、。  [0050] In each of the semiconductor devices described above, the electrodes electrically connected to the internal circuits of the first and second layer semiconductor chips and the dummy electrodes are alternately arranged one by one or alternately by one side. By arranging one of the two electrodes in contact with both sides of the conductor pattern as a dummy electrode, the internal circuits in the entire area of each semiconductor chip were independently connected to the printed wiring board. The configuration may be applied only to some areas. In other words, circuits (signal lines) that route the first and second layer semiconductor chips independently only in some areas and flow the same signal between the first and second layer semiconductor chips in other areas. An electrode connected to the internal circuit and a dummy electrode may be arranged so that they are electrically connected to each other! /.
[0051] たとえば半導体メモリでは、バスライン (アドレス及びデータ）のように上下の半導体 チップで接続できる信号ラインもある力 チップィネーブルピンのように上下の半導体 チップで接続できな ヽ信号ラインが存在し、その場合は各信号ラインを独立して配線 する必要があるので、上記した構造が好都合である。ただしダミー電極を全く設けな い場合も、チップ部分が配線基板 103の開口 103aに入り込むことで装置厚みを低 減できるので、そのような構造も本発明に含まれる。 [0051] For example, in a semiconductor memory, there are signal lines that can be connected by upper and lower semiconductor chips such as bus lines (address and data). There are signal lines that cannot be connected by upper and lower semiconductor chips such as chip enable pins. In that case, wire each signal line independently The structure described above is advantageous. However, even when no dummy electrode is provided, the thickness of the device can be reduced by the chip portion entering the opening 103a of the wiring board 103, and such a structure is also included in the present invention.
[0052] 以下、特に断らない場合も、 1つの導体パターンの両側に第 1層と第 2層の半導体 チップの電極が接触していれば、そしてそのような電極が複数組あれば、その内の少 なくとも一部は、一方がダミー電極である。  [0052] Hereinafter, unless otherwise specified, if the electrodes of the first and second semiconductor chips are in contact with both sides of one conductor pattern, and if there are a plurality of such electrodes, At least a part of this is a dummy electrode.
[0053] 図 12に示す半導体装置では、配線基板 103の 2個の開口 103aごとに半導体チッ プ 101, 102が積層実装されている。開口 103aにおける導体パターン 104の配列は 、図 7に示したようなものであってもよいし、図 11に示したようなものであってもよい。こ の半導体装置でも、図 6に示した半導体装置と同等の厚みを実現できる。  In the semiconductor device shown in FIG. 12, semiconductor chips 101 and 102 are stacked and mounted in each of the two openings 103a of the wiring board 103. The arrangement of the conductor patterns 104 in the openings 103a may be as shown in FIG. 7 or as shown in FIG. This semiconductor device can achieve the same thickness as the semiconductor device shown in FIG.
[0054] 図 13 (a) , (b)に示す半導体装置では、配線基板 103として、両面露出した複数の 導体パターン 104が矩形の開口 103aに臨んだ 2対の対辺のそれぞれに沿って配列 されたものが用いられて 、る。  In the semiconductor device shown in FIGS. 13 (a) and 13 (b), as the wiring substrate 103, a plurality of conductor patterns 104 exposed on both sides are arranged along each of two pairs of opposite sides facing the rectangular opening 103a. It is used.
[0055] 導体パターン 104の片側に配置された半導体チップ 111には、各導体パターン 10 4に対向するように四周の各辺に沿って複数の電極 105 (105a, 105b)が形成され て 、る（図 13 (a)にお!/ヽては電極 105の一部の図示を省略して!/、る）。導体パターン 104のもう片側には、半導体チップ 111の 2分の 1程度のチップサイズの半導体チッ プ 112, 113が並列に配置されている。半導体チップ 112, 113にはそれぞれ、半導 体チップ 111の電極 105に対向するように、 3辺に沿って複数の電極 106 (106a, 1 06b)が形成されている。これら半導体チップ 111と半導体チップ 112, 113とは、互 いに対向する電極 105,電極 106の間に導体パターン 104を挟んでいる。この半導 体装置でも図 6に示した半導体装置と同等の厚みを実現できる。  A plurality of electrodes 105 (105a, 105b) are formed on each side of the four circumferences of the semiconductor chip 111 disposed on one side of the conductor pattern 104 so as to face each conductor pattern 104. (In FIG. 13 (a), part of the electrode 105 is omitted!). On the other side of the conductor pattern 104, semiconductor chips 112 and 113 each having a chip size about one-half of the semiconductor chip 111 are arranged in parallel. A plurality of electrodes 106 (106a, 106b) are formed along the three sides of the semiconductor chips 112, 113 so as to face the electrodes 105 of the semiconductor chip 111, respectively. The semiconductor chip 111 and the semiconductor chips 112 and 113 sandwich the conductor pattern 104 between the electrodes 105 and 106 facing each other. This semiconductor device can achieve the same thickness as the semiconductor device shown in FIG.
[0056] 図 14に示す半導体装置では、配線基板 103として、両面露出した複数の導体バタ ーン 104が、矩形の開口 103aに臨んだ 1対の対辺のそれぞれに沿って、 2列に配列 されたものが用いられている（図 7と同様の配線基板)。  In the semiconductor device shown in FIG. 14, a plurality of conductor patterns 104 exposed on both sides are arranged in two rows as a wiring board 103 along each of a pair of opposite sides facing the rectangular opening 103a. (The same wiring board as in Fig. 7).
[0057] 導体パターン 104の片側に配置された半導体チップ 121には、一方の列の導体パ ターン 104のそれぞれに対向する複数の電極 105が形成されて!、る。導体パターン 104のもう片側に配置された半導体チップ 122には、他方の列の導体パターン 104 のそれぞれに対向する複数の電極 106が形成されている。これら半導体チップ 121 , 122は、一方の列の導体パターン 104を電極 105と対向するチップの絶縁表面と の間に挟んで、また他方の列の導体パターン 104を電極 106と対向するチップの絶 縁表面との間に挟んで積層されている。 A plurality of electrodes 105 facing each of the conductor patterns 104 in one row are formed on the semiconductor chip 121 arranged on one side of the conductor pattern 104. The semiconductor chip 122 arranged on the other side of the conductor pattern 104 has a conductor pattern 104 in the other row. A plurality of electrodes 106 are formed to face each of the electrodes. These semiconductor chips 121 and 122 are formed by sandwiching the conductive pattern 104 in one row between the electrode 105 and the insulating surface of the chip facing the other side, and the insulating pattern of the chip facing the electrode 106 in the other row. They are stacked between the surface.
[0058] このような積層構造によれば、半導体装置の厚みは実質上、半導体チップ 121の チップと、電極 105あるいは電極 106と、導体パターン 104と、半導体チップ 122の チップの厚みの和となる。図 6から図 13の各半導体装置に比べて、ダミー電極を対 向させない分だけ、更なる低背化が実現できる。  According to such a laminated structure, the thickness of the semiconductor device is substantially the sum of the thickness of the chip of the semiconductor chip 121, the electrode 105 or the electrode 106, the conductor pattern 104, and the chip of the semiconductor chip 122. . Compared to the semiconductor devices shown in FIGS. 6 to 13, a further reduction in height can be realized by not providing the dummy electrodes to face each other.
[0059] 図 15に示す半導体装置では、配線基板 103として、両面露出した複数の導体バタ ーン 104が、矩形の開口 103aに臨んだ 1対の対辺のそれぞれに沿って、 2列に配列 されたものが用いられている（図 7と同様の配線基板)。  In the semiconductor device shown in FIG. 15, a plurality of conductive patterns 104 exposed on both sides are arranged in two rows as a wiring board 103 along each of a pair of opposite sides facing the rectangular opening 103a. (The same wiring board as in Fig. 7).
[0060] 導体パターン 104の片側に配置された半導体チップ 131には、一方の列の導体パ ターン 104のそれぞれに対向するように複数の電極 105が外周縁近傍に形成される とともに、他方の列の導体パターン 104のそれぞれに対向するように複数の電極 105 が外周縁よりやや内側に形成されている。導体パターン 104のもう片側に配置された 半導体チップ 132には、他方の列の導体パターン 104のそれぞれに対向するように 複数の電極 106が外周縁近傍に形成されるとともに、一方の列の導体パターン 104 のそれぞれに対向するように複数の電極 106が外周縁よりやや内側に形成されてい る。各列の導体パターン 104に対向する電極 105と電極 106は、互いに対向すること なく導体パターン 104の長手方向に並ぶように、位置設定されている。これら半導体 チップ 131, 132力 各列の導体パターン 104をその長手方向に並んだ電極 105と 電極 106とによって対向するチップの絶縁表面との間に挟んで積層されている。  In the semiconductor chip 131 disposed on one side of the conductor pattern 104, a plurality of electrodes 105 are formed in the vicinity of the outer peripheral edge so as to face each of the conductor patterns 104 in one row, and the other row A plurality of electrodes 105 are formed slightly inside the outer peripheral edge so as to face each of the conductor patterns 104. In the semiconductor chip 132 arranged on the other side of the conductor pattern 104, a plurality of electrodes 106 are formed in the vicinity of the outer periphery so as to face each of the conductor patterns 104 in the other row, and the conductor pattern in one row A plurality of electrodes 106 are formed slightly inside the outer peripheral edge so as to face each of 104. The electrodes 105 and 106 facing the conductor pattern 104 in each row are positioned so as to be aligned in the longitudinal direction of the conductor pattern 104 without facing each other. These semiconductor chips 131 and 132 are laminated such that the conductor patterns 104 in each row are sandwiched between the insulating surfaces of the opposing chips by the electrodes 105 and 106 arranged in the longitudinal direction.
[0061] このような積層構造によっても、半導体装置の厚みは実質上、半導体チップ 131の チップと、電極 105あるいは電極 106と、導体パターン 104と、半導体チップ 132の チップの厚みの和となる。図 6から図 13の半導体装置に比べて、ダミー電極を対向さ せない分だけ、更なる低背化が実現できる。図 14の半導体装置に比べて、電極数が 多 、半導体チップに適した構造である。  Even with such a stacked structure, the thickness of the semiconductor device is substantially the sum of the thickness of the chip of the semiconductor chip 131, the electrode 105 or the electrode 106, the conductor pattern 104, and the chip of the semiconductor chip 132. Compared to the semiconductor devices in FIGS. 6 to 13, a further reduction in height can be realized by the amount of dummy electrodes that do not face each other. Compared to the semiconductor device in FIG. 14, it has a larger number of electrodes and is suitable for a semiconductor chip.
[0062] 図 16に示す半導体装置では、配線基板 103として、両面露出した複数の導体バタ ーン 104が矩形の開口 103aに臨んだ 2対の対辺のそれぞれに沿って配列されたも のが用いられて 、る（図 11と同様の配線基板)。 In the semiconductor device shown in FIG. 16, a plurality of conductor patterns exposed on both sides are used as the wiring substrate 103. An array 104 is used which is arranged along each of two pairs of opposite sides facing the rectangular opening 103a (a wiring board similar to FIG. 11).
[0063] 導体パターン 104の片側に配置された半導体チップ 141には、各導体パターン 10 4に対向するように四周の各辺に沿って複数の電極 105が形成されている（電極 105 の一部の図示を省略している)。導体パターン 104のもう片側には、半導体チップ 14 1の 2分の 1よりもやや小さい半導体チップ 142, 143が並列に配置されている。半導 体チップ 142, 143にはそれぞれ、各導体パターン 104に対向するように 3辺に沿つ て複数の電極 106が形成されている。各列の導体パターン 104に対向する電極 105 と電極 106は、互いに対向することなく導体パターン 104の長手方向に並ぶように位 置設定されている。これら半導体チップ 142, 143力 その電極 106で導体パターン 104の端部を対向する半導体チップ 141の絶縁表面との間に挟んで積層されており 、半導体チップ 141の電極 105は半導体チップ 142, 143よりも外周側で導体パター ン 104に接続している。 A plurality of electrodes 105 are formed along each side of the four circumferences of the semiconductor chip 141 arranged on one side of the conductor pattern 104 so as to face each conductor pattern 104 (part of the electrode 105). Is omitted). On the other side of the conductor pattern 104, semiconductor chips 142 and 143 that are slightly smaller than one half of the semiconductor chip 14 1 are arranged in parallel. A plurality of electrodes 106 are formed along the three sides of the semiconductor chips 142 and 143 so as to face the conductor patterns 104, respectively. The electrodes 105 and 106 facing the conductor pattern 104 in each row are positioned so as to be aligned in the longitudinal direction of the conductor pattern 104 without facing each other. These semiconductor chips 142 and 143 are stacked such that the end of the conductor pattern 104 is sandwiched between the electrodes 106 and the insulating surface of the semiconductor chip 141 facing each other. The electrode 105 of the semiconductor chip 141 is formed by the semiconductor chips 142 and 143. Is also connected to the conductor pattern 104 on the outer peripheral side.
[0064] このような積層構造によっても、半導体装置の厚みは実質上、半導体チップ 141の チップ厚みと、電極 105あるいは電極 106の厚みと、導体パターン 104の厚みと、半 導体チップ 142あるいは半導体チップ 143のチップ厚みとの和となる。図 6から図 13 の半導体装置に比べて、ダミー電極を対向させない分だけ、更なる低背化が実現で きる。図 14の半導体装置に比べて、電極数が多い半導体チップや、より多いチップ 数に適した構造である。  [0064] Even with such a laminated structure, the thickness of the semiconductor device is substantially the same as that of the semiconductor chip 141, the thickness of the electrode 105 or 106, the thickness of the conductor pattern 104, the semiconductor chip 142 or the semiconductor chip. It is the sum of the chip thickness of 143. Compared with the semiconductor devices of FIGS. 6 to 13, a further reduction in height can be achieved by not making the dummy electrodes face each other. Compared to the semiconductor device in FIG. 14, the structure is suitable for a semiconductor chip with a larger number of electrodes and a larger number of chips.
[0065] 以上のような半導体装置を 1ユニットとして、さらに積層して半導体装置 (以下、半導 体装置モジュールという）を構成してもよい。先に図 6に示した半導体装置 (以下、半 導体装置ユニット U1という）と、図 12に示した半導体装置 (以下、半導体装置ュニッ ト U2という）を例に挙げて説明する。  [0065] A semiconductor device (hereinafter referred to as a semiconductor device module) may be configured by stacking the semiconductor devices as described above as one unit. The semiconductor device shown in FIG. 6 (hereinafter referred to as semiconductor device unit U1) and the semiconductor device shown in FIG. 12 (hereinafter referred to as semiconductor device unit U2) will be described as examples.
[0066] 図 17に示した半導体装置モジュール Mlは、半導体装置ユニット U1を用い、図 1 の構造を組み合わせて、 4層の積層構造を実現している。  The semiconductor device module Ml shown in FIG. 17 uses a semiconductor device unit U1 and combines the structures shown in FIG. 1 to realize a four-layer stacked structure.
[0067] すなわち、半導体装置ユニット U1の半導体チップ 101の上に、 3層目の半導体チ ップ 151をその回路形成面に背反する背面においてボンディングシート 152で固定 し、回路形成面に設けられた電極 153を半導体装置ユニット U1のプリント配線基板 1 03に導電性ワイヤ 154で電気的に接続させ、この半導体チップ 151の上に 4層目の 半導体チップ 155を回路形成面同士を対向させて電極 156で接続させて実装し、榭 脂 157で封止している。 That is, the third semiconductor chip 151 is fixed on the semiconductor chip 101 of the semiconductor device unit U1 with the bonding sheet 152 on the back surface opposite to the circuit formation surface, and provided on the circuit formation surface. Electrode 153 printed circuit board for semiconductor device unit U1 1 03 is electrically connected with a conductive wire 154, and a fourth-layer semiconductor chip 155 is mounted on the semiconductor chip 151 with the circuit forming surfaces facing each other and connected with an electrode 156, and sealed with a resin 157. It has stopped.
[0068] 図 18に示した半導体装置モジュール M2は、図 17に示した半導体装置モジュール The semiconductor device module M2 shown in FIG. 18 is the same as the semiconductor device module shown in FIG.
Mlを 2段に積層し、対面したプリント配線基板 103どうしをボンディングシート 158で 接合して、 8層の積層構造を実現している。 Ml is laminated in two stages, and the printed wiring boards 103 facing each other are joined together with a bonding sheet 158 to realize an eight-layer laminated structure.
[0069] 図 19に示した半導体装置モジュール M3は、図 18に示した半導体装置モジュールThe semiconductor device module M3 shown in FIG. 19 is the same as the semiconductor device module shown in FIG.
M2を更に 2段に積層して、 16層の積層構造を実現している。半導体装置モジユー ル M2どうしの半導体チップが接触しないように、対面したプリント配線基板 103間に 金属ボール 159を接着材 160を用いて介装している。 M2 is further stacked in two layers to achieve a 16-layer stack structure. A metal ball 159 is interposed between the facing printed wiring boards 103 using an adhesive 160 so that the semiconductor chips of the semiconductor device module M2 do not contact each other.
[0070] 図 20に示した半導体装置モジュール M4は、半導体装置ユニット U1を 8段に積層 し、対面したプリント配線基板 103どうしをボンディングシート 158で接合して、 16層 の積層構造を実現している。 In the semiconductor device module M4 shown in FIG. 20, the semiconductor device units U1 are stacked in eight stages, and the printed wiring boards 103 facing each other are bonded together with a bonding sheet 158 to realize a 16-layer stacked structure. Yes.
[0071] 図 21に示した半導体装置モジュール M5は、半導体装置ユニット U2を 8段に積層 し、対面したプリント配線基板 103どうしをボンディングシート 158で接合して、 16層 の積層構造を実現している。 In the semiconductor device module M5 shown in FIG. 21, the semiconductor device unit U2 is stacked in eight stages, and the printed wiring boards 103 facing each other are bonded together with a bonding sheet 158 to realize a stacked structure of 16 layers. Yes.
[0072] 図 22に示した半導体装置モジュール M6は、半導体装置ユニット U2を用い、図 1 の構造を組み合わせて、 16層の積層構造を実現している。対面したプリント配線基 板 103間には金属ボール 159を接着材 160を用いて介装している。 The semiconductor device module M6 shown in FIG. 22 uses a semiconductor device unit U2 and realizes a 16-layer stacked structure by combining the structures shown in FIG. A metal ball 159 is interposed between the facing printed wiring boards 103 using an adhesive 160.
[0073] 16層の半導体チップを積層した、図 20, 21の半導体装置モジュールのそれぞれ については、厚み 30 μ mの ICチップを用いて総厚 1035 μ m、 1065 μ mを実現して いる。 [0073] Each of the semiconductor device modules in FIGS. 20 and 21 in which 16 layers of semiconductor chips are stacked has a total thickness of 1035 μm and 1065 μm using an IC chip with a thickness of 30 μm.
[0074] 以上説明したように、本発明によれば、配線基板の片側に 2層の半導体チップを電 極どうし接触する状態で積層する構造の半導体装置において、ダミー電極を設ける ことにより、 2層の半導体チップの固定構造は確保しながら、各半導体チップに少なく とも 1つ形成される内部回路をそれぞれ独立して、対向する半導体チップの内部回 路カゝら分離して、配線基板に電気的に接続することが可能となる。  As described above, according to the present invention, in a semiconductor device having a structure in which two layers of semiconductor chips are stacked on one side of a wiring board in a state where the electrodes are in contact with each other, by providing a dummy electrode, While securing the fixing structure of the semiconductor chip, at least one internal circuit formed in each semiconductor chip is independently separated from the internal circuit cover of the opposing semiconductor chip and electrically connected to the wiring board. It becomes possible to connect to.
[0075] 2層の半導体チップを配線基板の両側に積層する構造の半導体装置では、中間配 線層の一部が両面露出した導体部 (導体パターン）に対して半導体チップを接続す ることにより、各層の半導体チップの少なくとも電極を配線基板の表面よりも内側へ入 り込ませて、実装後の厚みを薄くすることができる。 [0075] In a semiconductor device having a structure in which two layers of semiconductor chips are stacked on both sides of a wiring board, an intermediate arrangement is used. By connecting a semiconductor chip to a conductor part (conductor pattern) with part of the wire layer exposed on both sides, at least the electrodes of the semiconductor chip in each layer are inserted inside the surface of the wiring board and mounted. Later thickness can be reduced.
[0076] 2層の半導体チップを配線基板の両側に積層する構造の半導体装置で、両面露 出した導体部を 2層の半導体チップの電極間に挟む場合も、ダミー電極を設けること により、電極どうし対向する構造でありながら、各半導体チップの内部回路をそれぞ れ独立して、対向する半導体チップから分離して、配線基板に電気的に接続させる ことが可能となる。  [0076] In a semiconductor device having a structure in which two layers of semiconductor chips are stacked on both sides of a wiring board, a dummy electrode is also provided when a conductor portion exposed on both sides is sandwiched between electrodes of two layers of semiconductor chips. Although the structures are opposed to each other, the internal circuits of the respective semiconductor chips can be independently separated from the opposed semiconductor chips and electrically connected to the wiring board.
[0077] 2層の半導体チップを互いの電極と絶縁部との間に導体部を挟んで実装する場合 には、電極どうし対向する構造よりも実装後の厚みが薄くなり、且つ、各半導体チップ の内部回路をそれぞれ独立して、対向する半導体チップ力も分離して、配線基板に 電気的に接続することが可能である。  [0077] When a two-layer semiconductor chip is mounted with the conductor portion sandwiched between the electrodes and the insulating portion, the thickness after mounting becomes thinner than the structure in which the electrodes face each other, and each semiconductor chip These internal circuits can be electrically connected to the wiring board by separating the opposing semiconductor chip forces independently.
[0078] 2層の半導体チップの電極を各導体部に対応して互いに対向しないように設け、一 方あるいは双方の電極と絶縁部との間に導体部を挟んで実装する場合も、ダミー電 極を設けることにより、電極どうし対向する構造よりも実装後の厚みが薄くなるだけで なぐ各半導体チップの内部回路をそれぞれ独立して、対向する半導体チップから 分離して、配線基板に電気的に接続することができる。この構造は、電極数の多い半 導体チップに適して!/、る。  In the case where the electrodes of the two-layer semiconductor chip are provided so as not to oppose each other corresponding to each conductor portion, and when mounting the conductor portion between one or both electrodes and the insulating portion, the dummy electric current is also provided. By providing the poles, the internal circuit of each semiconductor chip can be separated from the opposing semiconductor chip independently, and the wiring board is electrically separated by simply reducing the thickness after mounting compared to the structure where the electrodes face each other. Can be connected. This structure is suitable for semiconductor chips with many electrodes!
[0079] 導体部について特に断わらな力つた上記各半導体装置においても、導体部が配線 基板の中間配線層の一部であれば、各半導体チップの少なくとも電極が配線基板の 表面よりも内側へ入り込むので、実装後の厚みが薄くなる。また両面露出した導体部 が配線基板の単一の開口内にあれば、チップ部分も配線基板の表面よりも内側へ入 り込むので、実装後の厚みがさらに薄くなる。  [0079] Even in each of the semiconductor devices described above that has a particularly strong force with respect to the conductor portion, if the conductor portion is part of the intermediate wiring layer of the wiring board, at least the electrodes of each semiconductor chip enter inside the surface of the wiring board. Therefore, the thickness after mounting becomes thin. Further, if the conductor part exposed on both sides is in a single opening of the wiring board, the chip part also enters inward from the surface of the wiring board, so that the thickness after mounting is further reduced.
[0080] 2層の半導体チップを配線基板の両側に積層するには、配線基板との間に導電性 榭脂を介在させておき、両側から加圧してそれぞれの電極を導体部に圧着させるだ けでよぐ容易にかつ安価に実装できる。  [0080] In order to stack two layers of semiconductor chips on both sides of a wiring board, a conductive resin is interposed between the two wiring boards and pressure is applied from both sides to press the respective electrodes to the conductor portion. It can be mounted easily and inexpensively.
産業上の利用可能性  Industrial applicability
[0081] 本発明の半導体装置は、 2層の半導体チップを配線基板に積層して独立して電気 的に接続し得たものであり、薄型化も実現できるので、半導体メモリを積層実装する 場合などに有用である。 [0081] The semiconductor device of the present invention has a two-layer semiconductor chip stacked on a wiring board and is electrically connected independently. This is useful for the case where semiconductor memories are stacked and mounted.

Claims

請求の範囲 The scope of the claims
[1] 複数の半導体チップが配線基板上に積層された半導体装置であって、  [1] A semiconductor device in which a plurality of semiconductor chips are stacked on a wiring board,
前記配線基板の一方の面に 2層の半導体チップが互いの複数の電極どうし接触す る状態で積層され、 Vヽずれかの半導体チップの電極が導電性ワイヤを介して配線基 板の導体部に電気的に接続され、互いに接触した複数組の電極の内の少なくとも一 部は、一方の電極が、当該電極が属する半導体チップの内部回路に電気的に接続 しな 、ダミー電極として形成されて 、ることを特徴とする半導体装置。  A two-layer semiconductor chip is stacked on one surface of the wiring board in a state where the plurality of electrodes are in contact with each other, and the electrodes of any one of the V semiconductor chips are connected to the conductor portion of the wiring board via conductive wires. At least some of the plurality of sets of electrodes that are electrically connected to and in contact with each other are formed as dummy electrodes, with one electrode not electrically connected to the internal circuit of the semiconductor chip to which the electrode belongs. A semiconductor device characterized by the above.
[2] 複数の半導体チップを配線基板上に積層して半導体装置を製造する際に、  [2] When manufacturing a semiconductor device by stacking a plurality of semiconductor chips on a wiring board,
積層される 2層の半導体チップの内の少なくとも一方に、内部回路に電気的に接続 しな 、ダミー電極を含んだ複数の電極を有した半導体チップを用い、前記配線基板 の一方の面に第 1層の半導体チップを電極形成面を上にして搭載し、前記第 1層の 半導体チップの各電極と配線基板の導体部とを導電性ワイヤを介して電気的に接続 し、前記第 1層の半導体チップ上に第 2層の半導体チップを、互いの複数の電極どう し接触するように、かつ前記ダミー電極と内部回路に電気的に接続した電極とが対 向するように実装することを特徴とする半導体装置の製造方法。  A semiconductor chip having a plurality of electrodes including dummy electrodes that are not electrically connected to the internal circuit is used as at least one of the two-layer semiconductor chips to be stacked. A first layer semiconductor chip is mounted with the electrode formation surface facing upward, and each electrode of the first layer semiconductor chip and a conductor portion of the wiring board are electrically connected via a conductive wire, and the first layer The second-layer semiconductor chip is mounted on the semiconductor chip such that the plurality of electrodes are in contact with each other and the dummy electrode and the electrode electrically connected to the internal circuit are opposed to each other. A method of manufacturing a semiconductor device.
[3] 複数の半導体チップが配線基板上に積層された半導体装置であって、  [3] A semiconductor device in which a plurality of semiconductor chips are stacked on a wiring board,
配線基板の一部に両面露出した複数の導体部が形成され、前記複数の導体部の 両側に 2層の半導体チップが電極形成面どうし対向して積層され、各導体部の少なく とも片面に、対向する半導体チップの電極が接合されていることを特徴とする半導体 装置。  A plurality of conductor portions exposed on both sides are formed on a part of the wiring board, and two layers of semiconductor chips are stacked on both sides of the plurality of conductor portions so as to face each other, and at least one side of each conductor portion is A semiconductor device, wherein electrodes of opposing semiconductor chips are joined.
[4] 複数の半導体チップが配線基板上に積層された半導体装置であって、  [4] A semiconductor device in which a plurality of semiconductor chips are stacked on a wiring board,
配線基板の一部に両面露出した複数の導体部が形成され、前記複数の導体部の 両側に 2層の半導体チップが電極形成面どうし対向して積層され、前記 2層の半導 体チップは、複数の電極をそれぞれ有し、互いの電極の間に前記導体部を挟み、前 記複数の導体部を挟んだ複数組の電極の内の少なくとも一部は、一方の電極が、当 該電極が属する半導体チップの内部回路に電気的に接続しないダミー電極として形 成されて！/ヽることを特徴とする半導体装置。  A plurality of conductor portions exposed on both sides are formed on a part of the wiring board, and two layers of semiconductor chips are stacked on both sides of the plurality of conductor portions so as to face each other, and the two-layer semiconductor chip is Each electrode has a plurality of electrodes, the conductor portion is sandwiched between the electrodes, and at least a part of the plurality of sets of electrodes sandwiching the plurality of conductor portions has one electrode corresponding to the electrode. Is formed as a dummy electrode that is not electrically connected to the internal circuit of the semiconductor chip to which it belongs! / Semiconductor device characterized by being beaten.
[5] 複数の半導体チップが配線基板上に積層された半導体装置であって、 配線基板の一部に両面露出した複数の導体部が並列に形成され、前記複数の導 体部の両側に 2層の半導体チップが電極形成面どうし対向して積層され、前記 2層の 半導体チップは、一方の列の導体部に対向する複数の電極と他方の列の導体部に 対向する絶縁部とをそれぞれ有し、互いの電極と絶縁部との間に導体部を挟んでい ることを特徴とする半導体装置。 [5] A semiconductor device in which a plurality of semiconductor chips are stacked on a wiring board, A plurality of conductor portions exposed on both sides of a part of the wiring board are formed in parallel, and two layers of semiconductor chips are stacked on both sides of the plurality of conductor portions so as to face each other on the electrode forming surface. Each has a plurality of electrodes facing the conductor portion of one row and an insulating portion facing the conductor portion of the other row, and the conductor portion is sandwiched between the electrodes and the insulating portion. A semiconductor device characterized by the above.
[6] 複数の半導体チップが配線基板上に積層された半導体装置であって、  [6] A semiconductor device in which a plurality of semiconductor chips are stacked on a wiring board,
配線基板の一部に両面露出した複数の導体部が並列に形成され、前記複数の導 体部の両側に 2層の半導体チップが電極形成面どうし対向して積層され、前記 2層の 半導体チップは、各列の導体部に対向する複数の電極と絶縁部とを各導体部に対 応してそれぞれ有し、互いの電極と絶縁部との間に導体部を挟み、前記複数の導体 部に両側力も接触した複数組の電極の内の少なくとも一部は、一方の電極が、当該 電極が属する半導体チップの内部回路に電気的に接続しないダミー電極として形成 されて ヽることを特徴とする半導体装置。  A plurality of conductor portions exposed on both sides of a part of the wiring board are formed in parallel, and two layers of semiconductor chips are stacked on both sides of the plurality of conductor portions so as to face each other on the electrode forming surface. Each having a plurality of electrodes and insulating portions facing the conductor portions of each row corresponding to the respective conductor portions, and sandwiching the conductor portions between the respective electrodes and the insulating portions, the plurality of conductor portions At least a part of the plurality of sets of electrodes in contact with both side forces is formed as a dummy electrode in which one electrode is not electrically connected to the internal circuit of the semiconductor chip to which the electrode belongs. Semiconductor device.
[7] 複数の半導体チップが配線基板上に積層された半導体装置であって、  [7] A semiconductor device in which a plurality of semiconductor chips are stacked on a wiring board,
配線基板の一部に両面露出した複数の導体部が並列に形成され、前記複数の導 体部の両側に 2層の半導体チップが電極形成面どうし対向して積層され、第 1層の半 導体チップは、各列の導体部に対向する複数の電極と絶縁部とを各導体部に対応し て有し、第 2層の半導体チップは、前記第 1層の半導体チップの絶縁部に対向する 複数の電極を有し、前記第 1層および第 2層の半導体チップが互いに対向する電極 と絶縁部との間に導体部を挟み、かつ第 1層の半導体チップの電極が導体部に接合 し、前記複数の導体部に両側から接触した複数組の電極の内の少なくとも一部は、 一方の電極が、当該電極が属する半導体チップの内部回路に電気的に接続しな 、 ダミー電極として形成されていることを特徴とする半導体装置。  A plurality of conductor portions exposed on both sides of a part of the wiring board are formed in parallel, and two layers of semiconductor chips are laminated on both sides of the plurality of conductor portions so as to face each other on the electrode forming surface, so that the first layer semiconductor The chip has a plurality of electrodes opposed to the conductor portions of each row and an insulating portion corresponding to each conductor portion, and the second layer semiconductor chip faces the insulating portion of the first layer semiconductor chip. The first and second layer semiconductor chips have a plurality of electrodes, the conductor portion is sandwiched between the electrodes facing each other and the insulating portion, and the electrodes of the first layer semiconductor chip are joined to the conductor portion. In addition, at least a part of the plurality of sets of electrodes in contact with the plurality of conductor portions from both sides is formed as a dummy electrode, with one electrode not being electrically connected to the internal circuit of the semiconductor chip to which the electrode belongs. A semiconductor device characterized by that.
[8] 両面露出した複数の導体部が配線基板の中間配線層の一部である請求項 3〜請 求項 7の 、ずれかに記載の半導体装置。  [8] The semiconductor device according to any one of [3] to [7], wherein the plurality of conductor portions exposed on both sides are part of the intermediate wiring layer of the wiring board.
[9] 両面露出した複数の導体部が配線基板に形成された単一の開口内にある請求項 3〜請求項 7の 、ずれかに記載の半導体装置。  [9] The semiconductor device according to any one of [3] to [7], wherein the plurality of conductor portions exposed on both sides are in a single opening formed in the wiring board.
[10] 単一の半導体チップに対して複数の半導体チップが並列に積層されている請求項 3〜請求項 7の 、ずれかに記載の半導体装置。 [10] The plurality of semiconductor chips are stacked in parallel with respect to the single semiconductor chip. The semiconductor device according to any one of claims 3 to 7.
[11] 請求項 3〜請求項 7のいずれかに記載の半導体装置の製造方法であって、 [11] A method of manufacturing a semiconductor device according to any one of claims 3 to 7,
配線基板に両面露出した複数の導体部の両側に導電性榭脂層を介して 2層の半 導体チップを電極形成面どうし対向させて配置し、前記 2層の半導体チップを両側か ら加圧してそれぞれの電極を前記導体部に圧着させる  Two layers of semiconductor chips are placed opposite to each other on both sides of a plurality of conductors exposed on both sides of the wiring board via conductive resin layers, and the two layers of semiconductor chips are pressed from both sides. And crimp each electrode to the conductor
ことを特徴とする半導体装置の製造方法。  A method of manufacturing a semiconductor device.
[12] 半導体チップ力メモリ ICチップである請求項 1、請求項 3〜請求項 7のいずれかに 記載の半導体装置。 12. A semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor chip force memory IC chip.
[13] 請求項 1、請求項 3〜請求項 7のいずれかに記載の半導体装置を複数段に積層し てなる半導体装置モジュール。  [13] A semiconductor device module comprising the semiconductor device according to any one of claims 1 and 3 to 7 stacked in a plurality of stages.
PCT/JP2005/016267 2004-09-14 2005-09-05 Semiconductor device and method for manufacturing the same WO2006030662A1 (en)

Applications Claiming Priority (4)

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JP2004-266186 2004-09-14
JP2004266186A JP2006086145A (en) 2004-09-14 2004-09-14 Semiconductor device and method of mounting semiconductor chip
JP2004-353465 2004-12-07
JP2004353465A JP4578220B2 (en) 2004-12-07 2004-12-07 Semiconductor device

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08125112A (en) * 1994-10-26 1996-05-17 Hitachi Ltd Semiconductor device and production thereof
JP2001085605A (en) * 1999-09-14 2001-03-30 Toshiba Corp Semiconductor device and manufacturing method thereof
JP2002359346A (en) * 2001-05-30 2002-12-13 Sharp Corp Semiconductor device and method of stacking semiconductor chips
JP2004031563A (en) * 2002-06-25 2004-01-29 Renesas Technology Corp Semiconductor device and its manufacturing method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08125112A (en) * 1994-10-26 1996-05-17 Hitachi Ltd Semiconductor device and production thereof
JP2001085605A (en) * 1999-09-14 2001-03-30 Toshiba Corp Semiconductor device and manufacturing method thereof
JP2002359346A (en) * 2001-05-30 2002-12-13 Sharp Corp Semiconductor device and method of stacking semiconductor chips
JP2004031563A (en) * 2002-06-25 2004-01-29 Renesas Technology Corp Semiconductor device and its manufacturing method

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