WO2006012771A1 - Unite de commande hdlc multi-canal - Google Patents

Unite de commande hdlc multi-canal Download PDF

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Publication number
WO2006012771A1
WO2006012771A1 PCT/CN2004/000889 CN2004000889W WO2006012771A1 WO 2006012771 A1 WO2006012771 A1 WO 2006012771A1 CN 2004000889 W CN2004000889 W CN 2004000889W WO 2006012771 A1 WO2006012771 A1 WO 2006012771A1
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WO
WIPO (PCT)
Prior art keywords
channel
data
receiving
buffer
sending
Prior art date
Application number
PCT/CN2004/000889
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English (en)
Chinese (zh)
Inventor
Jiajin Chen
Zong Zhao
Gangyue He
Xu Chen
Jian He
Jian Wang
Original Assignee
Zte Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zte Corporation filed Critical Zte Corporation
Priority to PCT/CN2004/000889 priority Critical patent/WO2006012771A1/fr
Priority to CNB2004800436602A priority patent/CN100446578C/zh
Publication of WO2006012771A1 publication Critical patent/WO2006012771A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/14—Multichannel or multilink protocols

Definitions

  • the present invention relates to the field of T1/E1 communications, and in particular to a multi-channel advanced data link (HDLC) controller.
  • HDLC high-channel advanced data link
  • the controllers using the multi-channel HDLC mainly have the following two types.
  • One is a multi-channel HDLC controller of the type Conexant CN8472/8474, which uses a non-RISC (reduced instruction set computer structure), full circuit implementation, a total of 128 channels, the 128 channel HDLC is processed by the serial port interface, bit (bit) Level processing, interrupt processing controller, DMA controller, PCI (peripheral component expansion interface) bus interface.
  • bit (bit) Level processing bit (bit) Level processing
  • interrupt processing controller DMA controller
  • PCI peripheral component expansion interface
  • the multi-channel HDLC controller has the following two problems: First, a large amount of hardware resources are required for storing temporary parameters, and a lot of temporary parameters are required in the working process of the controller, including: receiving temporary loop redundancy for each channel Remainder code CRC (32 bits), receive temporary buffer pointer for each channel (32 bits), available length of receive temporary buffer for each channel (14 bits), transmit temporary cyclic redundancy for each channel Code CRC (32 bits), send temporary buffer pointer (32 bits) per channel, transmit temporary buffer available length (14 bits) per channel; then for 128 such channels, internal hardware needs There are (32+32+14+32+32+14) times 128 (channels) of RAM to store these temporary parameters. The above are the temporary parameters necessary for the HDLC controller to work.
  • the HDLC controller uses ping-pong FIFO to implement data transfer.
  • the receive FIFO and transmit FIFO are shown in Figure 1 and Figure 2.
  • the FIFO is divided into two equal-space RAM structures. The data is first written to one of the RAMs. When the write is full, it is switched to another RAM structure to operate. The interrupt is given to the DMA controller, and the DMA controller will fetch its data. After such a ping-pong FIFO-side is occupied by the write data port, the read data port can only access the other half of the FIFO, or wait for the port to be released before being accessed, thereby causing waste of resources.
  • the second is the MPC8260 communication processor produced by Motorola, USA. As shown in Figure 3, there are two 128-channel HDLC communication interfaces inside. The disadvantage of this solution is that its multi-channel HDLC cannot operate independently. There is a RISC for implementing the same configuration and control of multi-channel HDLC, data organization and data scheduling, and controlling other peripherals to achieve the same functionality as the Conexant CN8472/8474 multi-channel HDLC controller. Therefore, the communication processor requires a RISC module on the hardware, and the module has a corresponding interface to the multi-channel HDLC and other peripherals to facilitate control of the RISC module; it is also necessary to write code for the RISC module. This design is complex and requires a long design cycle.
  • the technical problem to be solved by the present invention is to provide a multi-channel advanced data link controller, which solves the disadvantages of large hardware resources consumption, insufficient use of FIFO resources, and difficulty in implementation in the prior art, and uses external resources to implement internal operations. .
  • the multi-channel advanced data link controller of the present invention comprises a time division multiplexed data receiving processing module, a receiving channel processor, a receiving monitor, a receiving buffer, a receiving engine, a sending engine, a sending buffer, a sending monitor, and a sending Channel processor, time division multiplexed data transmission processing module, and AHB bus interface;
  • the time division multiplexed data receiving processing module is configured to receive data from a serial interface, and convert the data into 8-bit parallel data, and output the data to the receiving channel processor;
  • the receiving channel processor is configured to remove, by the channel number, the zero inserted in the received data, and output the result to the receiving monitor;
  • the receiving monitor is configured to store data into the receiving buffer by channel number, monitor the capacity of the receiving buffer, and send a data request to the receiving and receiving;
  • the receiving buffer is configured to temporarily store the received data
  • the receiving engine is configured to perform cyclic redundancy check processing on the data, perform read and write operations on the buffer descriptor, and perform data transfer according to the requirements of the buffer descriptor, and then write the corresponding interrupt into the memory.
  • the sending engine is configured to perform read and write operations on the buffer descriptor, perform data transfer according to the requirements of the buffer descriptor, perform cyclic redundancy check processing, and write the corresponding interrupt into the memory;
  • the sending buffer is configured to temporarily store and send data
  • the sending monitor is configured to read data from the sending buffer and transmit the data to the sending channel processor according to an application of the sending channel processor, and according to the capacity of the sending buffer, Transmitting engine application data;
  • the sending channel processor is configured to perform a zero insertion operation on the data transmitted by the sending monitor by using a channel as a number;
  • the time division multiplexed data transmission processing module is configured to read a channel number from a slot number, and read channel data according to the channel number, and convert 8-bit parallel data into serial data output;
  • the AHB bus interface is coupled to the receiving engine and the transmitting engine for converting internal bus behavior to AHB bus behavior.
  • the invention adopts a non-RISC design and a full circuit implementation, does not need to adopt a universal RISC, and sets a special interface for the HDLC, and has a low design difficulty; the present invention stores the temporary parameters required for the operation of the multi-channel HDLC controller in the memory, thereby saving
  • the hardware resources of the multi-channel HDLC controller itself, the hardware resources saved are (( 32+32+14 ) (number of bits in the transmission part) + ( 32+32+14 ) (number of bits in the receiving part)) *128 (pass At the same time, the system only needs to allocate a memory space when using the multi-channel HDLC controller.
  • the receiving buffer and the transmitting buffer adopt a FIFO structure, and the read and write operations can be simultaneously operated.
  • the space size of the FIFO is dynamically allocated, and the number of timeslots is allocated, and the FIFO space is allocated more and occupied. A channel with a small number of time slots allocates less FIFO space.
  • FIG. 1 is a schematic diagram of a receiving FIFO of a Conexant CN8472/8474 multi-channel HDLC controller in the prior art
  • FIG. 2 is a schematic diagram of a transmit FIFO of a Conexant CN8472/8474 multi-channel HDLC controller in the prior art
  • FIG. 3 is a schematic diagram of a multi-channel HDLC structure of a Motorola MPC 8260 in the prior art; and FIG. 4 is a schematic structural view of a multi-channel HDLC controller of the present invention.
  • FIG. 1 to FIG. 3 are described in the background art, and are not described herein again.
  • the multi-channel HDLC controller of the present invention organizes data in a multi-channel HDLC manner and then passes
  • the time division multiplexing (TDM) interface transmits data and is connected to the system memory using the HDLC controller through the AHB (AMBA) bus interface.
  • AHB AHB
  • the temporary parameters required for the operation of some HDLC controllers are placed in the HDLC controller. In addition, these parameters are called externally by internal logic.
  • the multi-channel HDLC controller of the present invention includes: a time division multiplexing data receiving processing module, a receiving channel processor, a receiving monitor, a receiving buffer, a receiving engine, a sending engine, a sending buffer, a sending monitor, The transmit channel processor, the time division multiplexed data transmission processing module, and the AHB bus interface.
  • the various components of a multi-channel HDLC controller are described below in terms of both received data and transmitted data.
  • time-division multiplexed data receiving and processing module After the time-division multiplexed data receiving and processing module receives data from the TDM serial interface, since the subsequent data processing is in units of bytes, it is necessary to convert the data from the serial data into 8-bit parallel data and output it to the receiving channel processor. .
  • TDM is numbered in time slots, and subsequent processing is numbered by channel number, so the processing of 4 bar TDM is also required to be separated from the subsequent process of channel numbering.
  • the receiving channel processor After receiving the parallel data transmitted by the processing module, the receiving channel processor processes the channel number as the number. Although these parallel data are in units of bytes, the zero insertion operation has actually been performed, so the receiving channel processor needs to remove the zeros inserted in the data, so that the subsequent functional modules can actually operate in the smallest unit of bytes. .
  • the data after the divide-by-zero operation is transferred to the receive monitor.
  • the receiving monitor stores the received data in the receiving buffer by channel, and monitors the capacity of the receiving buffer. When it reaches the threshold, it generates a corresponding data transmission request to the receiving engine, and the threshold is generally 4 Bytes or 16 bytes or one frame ends. To increase bus utilization, data is typically sent out when it accumulates to one word (4 bytes).
  • the receiving buffer temporarily stores the data transmitted from the receiving monitor, and accumulates 4 bytes for the receiving engine.
  • the above data The capacity of this buffer is dynamically assignable and can be adjusted according to the actual situation.
  • the buffer can be implemented in FIFO.
  • some information required for the operation of the HDLC controller can be stored in the memory, such as temporarily receiving the cyclic redundancy check code CRC (32 bits), the receive buffer temporary pointer (32 bits), Receive buffer temporary usable length (14 bits) and some control status information of the channel.
  • CRC cyclic redundancy check code
  • the receive buffer temporary pointer 32 bits
  • Receive buffer temporary usable length 14 bits
  • some control status information of the channel can be stored in the memory, such as temporarily receiving the cyclic redundancy check code CRC (32 bits), the receive buffer temporary pointer (32 bits), Receive buffer temporary usable length (14 bits) and some control status information of the channel.
  • the receiving engine After receiving the data request from the receiving monitor, the receiving engine operates in two phases: If the receiving engine finds that the received data is the beginning of a frame, or there is no valid buffer descriptor (buffer descr i Ptor (abbreviated as BD), the receiving engine reads the BD from the specified channel BD table of the memory through the AHB bus interface, obtains the parameters on the BD, starts to carry the data according to the address given by the BD, and confirms whether the length of the BD is sufficient.
  • buffer descr i Ptor abbreviated as BD
  • Temporary As a temporary CRC (32-bit) in the parameter table, save the current address to the specified channel (temporary) As a temporary pointer (32 bits) of the receive buffer, the length of the data that can be transferred at that time is stored in the specified channel (temporary) parameter table as the temporary usable length of the receive buffer (14 bits), and other Parameters. Then exit this channel operation.
  • the receiving engine reads the received temporary CRC (32 bits) from the specified channel (temporary) parameter table of the memory through the AHB bus interface.
  • the engine will be used as the initial value of the CRC for the CRC operation), the receive buffer temporary pointer (32 bits) (the receiving engine uses this pointer as the starting point of the address for data transfer), and the receive buffer is temporarily available (14 bits).
  • Control information such as (receiving engine for length control), and then start receiving buffer
  • the data transmitted by the device is subjected to CRC processing, and data is carried at the same time, and it is confirmed whether the length of the BD is sufficient to carry the amount of data transmitted: if the length of the BD is insufficient or just satisfied, or the length of the BD exceeds the data transmission amount However, in the data transmission, if there is a message ending in the data, the status is written back to the BD after the data transfer is completed, and the BD is closed at the same time, if the BD length exceeds the magnitude of the data transmission, and the data is transmitted.
  • the current CRC value is stored in the specified channel (temporary) parameter table as a temporary CRC (32-bit), and the current address is stored in the designated channel ( Temporary) parameter table as a temporary pointer of the receive buffer (32 bits), the length of the data that can be transferred at that time is stored in the specified channel (temporary) parameter table as the temporary usable length of the receive buffer (14 bits), There are other parameters. Then exit the operation of this channel.
  • the AHB bus interface acts as a connection between the multi-channel HDLC controller and the AHB bus to convert the HDLC internal bus behavior to the standard AHB bus behavior.
  • the sending engine After receiving the application sent by the sending monitor, the sending engine will also have two phases of operation, which is similar to the receiving, except that the flow of data is opposite to the receiving. Similarly, in order to save the hardware resources of the HDLC controller, the HDLC controller works. Some of the required information is stored in the memory, such as the cyclic redundancy code CRC (32 bits), the send buffer temporary pointer (32 bits), the send buffer temporary available length (14 bits), and the channel. Some control status information, after the end of each BD operation, will return the corresponding frame information back to the BD.
  • CRC cyclic redundancy code
  • the sending engine Since the sending engine is a batch of incoming data, and the sending channel only needs to read one byte at a time, it is necessary to temporarily store the bulk data transmitted by the sending engine.
  • the buffer is provided for the temporary storage space. Make the bus more efficient.
  • the transmit buffer is implemented in FIFO, and its capacity is dynamically assignable, which can be adjusted according to actual conditions.
  • the sending monitor reads data from the sending buffer according to the data request of the sending channel processor, and transmits the data to the sending channel processor; and applies data to the sending engine according to the free amount of the sending buffer at the time, and the application condition is the channel. It is enabled, and the transmit buffer has 4 bytes for this channel or more than 16 slots.
  • the transmit channel processor processes the data transmitted by the transmit monitor with the channel number.
  • the data sent from the monitor is in bytes, but it is not the final data format. It needs to be inserted before the data is sent.
  • the time division multiplexed data transmission processing module obtains data from the transmission channel processor, and then converts the data into serial data for transmission. Since the previous data processing is in units of bytes, the data needs to be converted from 8-bit parallel data to serial. Data, similar to reception, TDM is numbered in time slots, and subsequent processing is numbered by channel number, so it is also necessary to separate the time division multiplexed data transmission processing module from other channel numbered modules.
  • a multi-channel HDLC controller can support up to 32 channels, and four multi-channel HDLC controllers can support up to 128 channels.
  • the multi-channel HDLC controller of the invention can be used as a communication module of the S0C chip to realize the docking of the multi-channel HDLC and the system, and supports the BD mode, and can actively transfer the data to the user-specified memory space.
  • the multi-channel HDLC controller must have a separate AHB s lave port, which can be considered as part of the AHB bus interface for the system to configure the HDLC controller.
  • the multi-channel HDLC controller must also be an AHB Mas ter. It can be regarded as part of the AHB bus interface, and can actively perform data transfer according to the requirements of the BD, and identify the state of the frame data on the BD after the data transfer is completed.
  • the multi-channel HDLC controller uses the standard AHB bus interface.
  • the AHB bus interface is the most common in the S0C chip, which makes the HDLC controller a standard module and easy to port to other S0Cs. In the chip.
  • the S0C chip is actually a multi-layer AHB bus system. At the same time, as long as different AHB Mas ters access different AHB Slave spaces, the operation of each AHB Mas ter will not be affected. At the same time, there are multiple memories in the S0C chip. Space, where SRAM space and SDRAM space can be used to store information about the operation of the HDLC controller.
  • each channel receives a temporary CRC (32 bits), sends a temporary CRC (32 bits), receives a buffer temporary pointer (32 bits), sends a buffer temporary pointer (32 bits), receives a buffer temporarily Available length (14 bits), send buffer temporarily available length (14 bits) and other information.
  • the SDRAM space has a larger capacity than the SRAM space and is used to store the BD table for each channel and the buffer pointed to by the BD table.

Abstract

L'unité de commande HDLC multi-canal de la présente invention s'utilise pour réaliser une liaison bout à bout entre la commande de liaison de données à haut niveau (HDLC) multi-canal et le système, agencer les données selon HDLC multi-canal, puis pour transmettre les données par l'interface de multiplexage temporel (TDM), et pour se connecter simultanément avec la mémoire du système qui utilise l'unité de commande HDLC via l'interface de bus AHB. Selon la présente invention, une partie des paramètres de temps que requiert l'unité de commande HDLC se trouve en dehors de cette dernière, ces paramètres étant appelés depuis l'extérieur par logique interne. De conception non RSIC, avec réalisation de tous les canaux, l'invention fait l'économie d'un RSIC général et permet d'établir une interface HDLC spéciale. Le montage ne pose pas de réelle difficulté. Avec cette invention, les paramètres dont l'unité de commande HDLC a besoin pour fonctionner sont stockés dans la mémoire, ce qui permet d'économiser les ressources matérielles de l'unité de commande elle-même. De plus, tous les canaux intervenant dans l'émission et la réception des données multi-canal par l'unité de commande HDLC partagent le même ensemble de logique de commande, ce qui permet là encore d'économiser de nombreuses ressources matérielles.
PCT/CN2004/000889 2004-08-02 2004-08-02 Unite de commande hdlc multi-canal WO2006012771A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2004/000889 WO2006012771A1 (fr) 2004-08-02 2004-08-02 Unite de commande hdlc multi-canal
CNB2004800436602A CN100446578C (zh) 2004-08-02 2004-08-02 一种多通道高级数据链路控制器

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Application Number Priority Date Filing Date Title
PCT/CN2004/000889 WO2006012771A1 (fr) 2004-08-02 2004-08-02 Unite de commande hdlc multi-canal

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Cited By (3)

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Publication number Priority date Publication date Assignee Title
WO2012155703A1 (fr) * 2011-09-16 2012-11-22 中兴通讯股份有限公司 Procédé d'auto-négociation de paramètres de liaison, terminal et système basés sur le protocole de commande de liaison de données de haut niveau (hdlc)
CN103118005A (zh) * 2013-01-04 2013-05-22 中国兵器工业集团第二一四研究所苏州研发中心 Hdlc协议控制器
CN110134365A (zh) * 2019-05-21 2019-08-16 合肥工业大学 一种多通道并行读出fifo的方法及装置

Families Citing this family (2)

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DE102013227059A1 (de) * 2013-12-23 2015-06-25 Robert Bosch Gmbh Verfahren zur deterministischen datenübertragung in einem bussystem und bussystem
CN111343106B (zh) * 2020-02-25 2023-03-24 母国标 多路中频数字信号处理装置和方法

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WO2003005794A1 (fr) * 2001-07-12 2003-01-23 Telefonaktiebolaget Lm Ericsson Controleur hdlc multicanal

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US7096261B2 (en) * 2001-03-12 2006-08-22 Qualcomm Incorporated Method and apparatus for providing multiple quality of service levels in a wireless packet data services connection
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CN1249876A (zh) * 1997-12-31 2000-04-05 阿尔卡塔尔公司 用户卡、用户连接单元、及可汇集因特网帧的交换中心
WO2003005794A1 (fr) * 2001-07-12 2003-01-23 Telefonaktiebolaget Lm Ericsson Controleur hdlc multicanal

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012155703A1 (fr) * 2011-09-16 2012-11-22 中兴通讯股份有限公司 Procédé d'auto-négociation de paramètres de liaison, terminal et système basés sur le protocole de commande de liaison de données de haut niveau (hdlc)
CN103118005A (zh) * 2013-01-04 2013-05-22 中国兵器工业集团第二一四研究所苏州研发中心 Hdlc协议控制器
CN110134365A (zh) * 2019-05-21 2019-08-16 合肥工业大学 一种多通道并行读出fifo的方法及装置
CN110134365B (zh) * 2019-05-21 2022-10-11 合肥工业大学 一种多通道并行读出fifo的方法及装置

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CN100446578C (zh) 2008-12-24

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