WO2006008721A2 - Interfaces d'emulation et de mise au point pour essais de circuits integres - Google Patents

Interfaces d'emulation et de mise au point pour essais de circuits integres Download PDF

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Publication number
WO2006008721A2
WO2006008721A2 PCT/IB2005/052372 IB2005052372W WO2006008721A2 WO 2006008721 A2 WO2006008721 A2 WO 2006008721A2 IB 2005052372 W IB2005052372 W IB 2005052372W WO 2006008721 A2 WO2006008721 A2 WO 2006008721A2
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WO
WIPO (PCT)
Prior art keywords
emulation
interface
jtag
software
instruction
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Application number
PCT/IB2005/052372
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English (en)
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WO2006008721A3 (fr
Inventor
Fabrizio Campanale
Jens Muttersbach
Andrea Foni
Original Assignee
Koninklijke Philips Electronics, N.V.
U.S. Philips Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics, N.V., U.S. Philips Corporation filed Critical Koninklijke Philips Electronics, N.V.
Priority to EP05758728A priority Critical patent/EP1782204A2/fr
Priority to JP2007520966A priority patent/JP2008507025A/ja
Publication of WO2006008721A2 publication Critical patent/WO2006008721A2/fr
Publication of WO2006008721A3 publication Critical patent/WO2006008721A3/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3648—Software debugging using additional hardware
    • G06F11/3656—Software debugging using additional hardware using a specific debug interface

Definitions

  • the present invention relates to computer program emulation and debugging, and more particularly to circuits and methods for digitally interfacing with embedded asynchronous microcontrollers with standard Joint Test Action Group (JTAG) test access ports (TAP).
  • JTAG Joint Test Action Group
  • the input/output (I/O), memory, assembler, compiler, and graphical user interfaces of the ICE development system are all then available to the engineer so that the programs can be tested in the actual target hardware. All the I/O, program memory, data memory, CPU registers, and peripherals in the target system are accessible to and modifiable by the host development system.
  • Breakpoints allow program execution to be stopped when certain events occur, and are another important debugging resource. Being able to stop program executions at defined locations and conditions allows a full analysis of how the program got where it did and how it affected the target system. Emulators can also use breakpoints to implement single stepping that allows the engineer to execute the target program one instruction at a time.
  • ICE development systems and their supporting equipment and software are expensive. They are also highly specialized to the particular processors being used in each target embedded system, and adapters and special software must be purchased for each type.
  • dedicated on-chip logic is needed for interfacing to the external emulator. Usually it is an IP either provided by the emulator company or by the supplier of the embedded microprocessor. Such extra costs add to the IC development expense budget.
  • Emulators can be used to take control and test computer circuit boards their processor, memory, or bus interfaces. Once in control, the emulator loads and runs diagnostic tests to debug the target hardware and software. Test access on densely packed boards is no problem for a processor emulator, although the real processor must be socketed to allow its replacement. Emulators were used extensively in board development, but increasing processor speeds now have made them impractical.
  • ROM-memory emulators plug into the sockets to replace the boot ROM, and insert diagnostic program code for the processor's normal boot code.
  • Such socket interfaces are bi-directional so that the unit-under-test (UUT) can communicate with the tester. But ROM emulators are not able to diagnose the processor to boot ROM area. Product design circuit modifications need to be made if the ROM's are soldered- in.
  • Bus emulators can be connected to a bus slot or edge connector, giving test access to the various circuits and functions of the UUT via read/write bus cycles. They are useful for testing plug-in bus cards such as VME and PCI.
  • Bus emulators can be connected to a bus slot or edge connector, giving test access to the various circuits and functions of the UUT via read/write bus cycles. They are useful for testing plug-in bus cards such as VME and PCI.
  • JTAG Joint Test Action Group
  • a serial interface defined is known as the test access port (TAP). It uses five data and timing pins to access daisy-chained shift registers built into each component's I/O pins. Such allows a chain of JTAG-compliant components to be "boundary scanned" for errors.
  • the JTAG protocol has been expanded by microprocessor and digital signal processor (DSP) manufacturers to provide on-board debug facilities for hardware and software developers. Such helps overcome the typical 30-MHz speed barrier encountered by external emulators. Vendor-specific extensions to JTAG typically have 2-3 additional signal lines and an enhanced instruction set for controlling the processor core.
  • debug interface-enabled CPU's include Intel® Pentium® processors, Intel XScaleTM Microarchitecture Processors, MotorolaTM, IBM® PowerPCTM, AMD®, MIPS®, and ARM® processor families.
  • the IEEE also has published IEEE ISTO- 5001 for debug interfaces.
  • the debug interfaces have been given various trademark names, e.g., Motorola's background debug mode (BDM), AMD's hardware debug tool(HDT), and Motorola/IBM's common on-chip processor (COP).
  • BDM background debug mode
  • HDT hardware debug tool
  • COP Motorola/IBM's common on-chip processor
  • the BDM interface is similar to JTAG, but the signal lines and protocol differ.
  • Test and diagnostic equipment designed to use a processor's debug interface requires only about six to 10 test points on the UUT. Such access can be achieved in most board designs, either by placing an interposer between CPU 116 and the socket, using a very simple bed of nails when CPUs are soldered, or making use of the JTAG break-out header provided by some board manufacturers.
  • Any bus-architecture UUT can be divided into functional blocks such as bridges,
  • RAM random access memory
  • video controllers and I/O controllers.
  • I/O controllers Each functional block contains arrays of memory or I/O registers.
  • Test programs use the extended JTAG debug functions provided by processor manufacturers to sequentially access these registers, building up a complete test.
  • Low-level functions include stop/start the processor, read/write memory, read/write general-purpose registers, read/write I/O, breakpoints, single-step code, and code trace. Combinations of these functions accommodate downloading test code to a UUT, controlling and monitoring test code execution, and collecting test results from UUT memory.
  • the read/write functions can test RAM, which also verifies intermediate buses.
  • I/O controllers are tested either by looping the output back into the input, as in the case of network interface controllers, or generating/measuring signals with external devices attached to the board's connectors.
  • Some test systems include I/O emulation units, which avoid the need to attach real peripheral devices. More expense and complexity is encountered if the target device CPU is not a synchronous type. Specialized interfaces are needed to deal with asynchronously clocked embedded processors.
  • a target device integrated circuit embodiment of the present invention comprises an embedded asynchronous microcontroller and is fitted with a standard JTAG- TAP interface.
  • a JTAG-TAP port controller and emulation interface are able to intercept and substitute every instruction being fetched from a code memory.
  • An external emulation PC has the ability to inspect on-board data and code memories by instructing the embedded asynchronous microcontroller to read and write them to the
  • JTAG-TAP interface Single-stepping and breakpoint registers are provided for debugging and testing by the external emulation PC.
  • An advantage of the present invention is a circuit is provided with built-in emulation and debug capability.
  • a further advantage of the present invention is a method is provided for a target device to be tested in free running mode while watching for breakpoints the device performance is not hampered, or emulation code can be executed at less than full speed that interacts with a PC.
  • a still further advantage of the present invention is that a system is provided which has an inexpensive and industry standard JTAG serial interface.
  • FIG. 1 is a functional block diagram of an emulation system embodiment of the present invention.
  • Fig. 2 is a flowchart diagram of an emulation interface mode method embodiment of the present invention, and is useful in the system of Fig. 1.
  • Fig. 1 illustrates an emulation system embodiment of the present invention, and is referred to herein by the general reference numeral 100.
  • the emulation system 100 comprises an ordinary personal computer (PC) 102 connected to a target device 104 through a standardized 5-pin JTAG interface 106.
  • PC personal computer
  • a TCK/clock pin synchronizes the internal state machine operations.
  • a TMS/mode select pin is sampled at the rising edge of TCK to determine the next state.
  • a TDI/data-in pin is sampled at the rising edge of TCK and shifted into the target device 104's test or programming logic when the internal state machine is in the correct state.
  • a TDO/data-out pin represents the data shifted out of the target device 104's test or programming logic and is valid on the falling edge of TCK when the internal state machine is in the correct state.
  • a TRST/reset pin resets an internal state machine when driven low.
  • a software tool included and operating on the PC 102 is able to control the emulation behavior of the target device through the emulation hardware interface.
  • the debugging software defines various functions to interface the emulator software environment so it can interact with the target device. For example: read/write RAM
  • DATA, IDATA, XDATA read/write special function register (SFR); read/write program code; initialize, re-initialize, reset/stop target hardware; read/write program counter; get/set registers; STOP, single STEP and RUN target execution; and, set/clear breakpoints.
  • the target device 104 is a single-chip integrated circuit (IC) and includes a JTAG test access port (TAP) controller 108 connected to an emulation interface 110.
  • Program code from a code memory 112 can be substituted with debug code and register information from the emulation interface.
  • debug code and other control information is downloaded from the PC 102 through he JTAG TAP 106 and TAP controller 108.
  • a data memory 114 is connected through a private bus to an asynchronous microcontroller (CPU) 116.
  • CPU 116 can be an Intel type 80C51 microcomputer.
  • the emulation interface 110 includes a JTAG interface 118, a configuration (EMU_CFG) register 120, an emulation data register (EMU_DR) 122, a breakpoints (EMU_BP) register 124, an instruction register (EMU_IR) 126, a program counter (EMU_PC) register 128, and emulation (EMU) controller 130, and a bus multiplexer 132 to switch between emulation code or regular program code from the code memory 112.
  • the EMU_IR 126 contains the 8-bit instruction to be executed by CPU 116 when in EMU External Mode.
  • the EMU_PC register 128 stores a current 18-bit value of the code address when a STOP or a breakpoint occurs. It is used by the emulator to restore the system by forcing a jump to the program counter address.
  • the EMU breakpoints register 124 stores two 18-bit instruction addresses the operator wants the microcontroller 116 to break execution and halt.
  • the EMU DR 122 provides for external inspection by PC 102 of 8-bit data in memories 112 and 114.
  • the asynchronous microcontroller 116 is commanded to move data from the memories and internal registers into the EMU_DR register 122.
  • the EMU_DR 122 can be then read out though the JTAG interface 118.
  • Table I defines the nine bits used in the EMU_CFG register 120.
  • FIG. 2 represents an emulation- interface mode process, and is referred to herein by the general reference numeral 200.
  • the emulation can be controlled by PC 102, the various bits in EMU_CFG register 120 are writeable and readable by PC 102 and are inspected and partially modified by process 200.
  • Table I provides the program bit symbols used hereafter in describing process 200.
  • the process 200 begins at a new program instruction request, e.g., by CPU 116 through instruction start signal and code address bus.
  • a step 202 checks to see if the EMU ON flag (EMU CFG.l) is set, meaning the emulation mode is on. If it is, then a step 204 checks the DIR & Start_instr flag (EMU_CFG.5).
  • a step 206 copies the code address (code add) into the EMU_PC register 128, in effect an unconditional program jump for CPU 116.
  • a step 208 saves the CPU's interrupt enable bit.
  • a step 210 disables CPU interrupts and watch dog timer (WDT).
  • a step 214 loops until IR_V becomes true.
  • a step 216 sends the instruction register EMU_IR to CPU 116 for execution and then loops back to step 202.
  • step 218 allows a regular program instruction from code memory 112 top be routed through multiplexer 132 to CPU 116 for regular execution. In other words, a test for emulation mode is made every instruction cycle of CPU 116. The overhead connected with this can be very minimal in terms of propagation time, as the decision to do an emulation instruction can be implemented with hardware.
  • step 204 found that DIR & Start_instr flag was not true, a step 220 restores IEN.7 and disables the WDT.
  • a step 222 looks to see if single-stepping (STEP) is required (EMU_CFG.3). If yes, a step 224 sends a next instruction to CPU 116.
  • Embodiments of the present invention recognize that when real time debugging is not required it is possible to reduce the number of IC pads dedicated to emulation, and those pads can use an inexpensive serial interface.
  • the standard JTAG Test Access Port is already present in many modern IC devices for test purposes, and typically will not add any further costs to present designs in terms of silicon area, package, design.
  • Software running on PC 102 can control registers in the emulation interface through the JTAG interface, the register bits are used by the hardware to control various interactions with CPU 116.
  • Initialization IIT
  • RE-INIT re-initialization
  • target reset functions are called by the software tool on PC 102 when it is necessary to initialize or finalize the hardware target.
  • routines include any initialization of the PC-to-JTAG interface, as well as the initialization of the configuration registers of the emulation interface 110.
  • the EMU_reset command writes a "0" the EMU_CFG.NRST bit. Such forces a reset of the whole chip except the JTAG controller 108 and the emulation interface 110.
  • RUN, STOP and STEP emulation controls are included.
  • An EMU freeze mode is entered as soon the reset flag (NRST) is written again to "1" and the internal chip-reset sequence is completed, CPU 116 will try to start up again. But the emulation interface 110, finding the EMU ON and DIR bits equal to "1", will freeze CPU 116 at the instruction address 0x0000, just during the fetching phase, entering into the EMU freeze mode. In this phase, it is possible to reconfigure the registers of emulation interface 110, defining the breakpoints addresses, or the external instructions. It's also possible to modify the direction of the instructions after a current instruction has been executed.
  • the DIR bit is read for each current operation by emulation interface 110, and is processed again only at the beginning of the next new instruction.
  • An EMU external mode is entered when emulation software on PC 102 lets CPU 116 run and writes the EMU_CFG.IR_V bit to "1 ". Such will validate the content of instruction register 126 that is passed to CPU 116 to be executed (EMU Internal Mode).
  • emulation interface 110 will check the EMU-ON and DIR bits in EMU_CFG register 120. If the DIR bit is still at one, emulation interface 110 will automatically reset the DR_V bit to invalidate the instruction register and will enter in the EMU freeze mode.
  • the external emulator can synchronize its operations with the events within the target device 104. Polling the IR_V bit until it becomes "0", as in step 212, emulation PC 102 will know when CPU 116 is frozen. Setting the IR_V to "1 " will let CPU 116 have the current instruction via EMUJR register 126.
  • emulation interface 110 To prevent entering the interrupt state during the EMU External Mode, emulation interface 110 temporarily disables all the interrupts, and resets the global interrupt enable bit in an associated interrupt controller. Similarly any watch dog timer is inactivated while CPU 116 is in emulation mode.
  • the original value of the global interrupt enable bit is saved into the EMU CFG.IE bit and is restored into the interrupt controller every time EMU internal modes are entered.
  • the target device 104 will enter into either an EMU internal step mode or an EMU internal standard mode, depending on the value of the EMU CFG.STEP bit.
  • EMU internal step mode only one complete instruction is provided to CPU 116 from the internal memory.
  • the emulation interface 110 will then copy the code address bus value into the EMU-PC register, set the DI R bit to "1" for the next cycle, copy the global interrupt enable bit into EMU CFG.IE, and reset the STEP bit to 0
  • EMU internal standard mode the execution will run full speed from the internal memory until a STOP command is received. This is done by either writing "1" EMU CFG. STOP, or until a breakpoint is encountered.
  • the emulation interface 110 then copies the code address bus value into the EMU-PC register, sets the DIR bit to "1" for the next cycle, copies the global interrupt enable bit into EMU_CFG, and sets the EMU V.STOP V (stop valid bit) to "1", or setthe EMU V.BP1 V / BP2 V (breakpoints valid bit) to "1".
  • the emulation software tool on PC 102 preferably has only indirect read/write access into all of the data/code memory space via CPU 116.
  • a direct access of the emulation interface 110 to the code and data memories 112 and 114 is not desirable since CPU 116 is asynchronous, and multiplexed access of the memories would slow down process execution. It is possible while CPU 116 is in the emulation state to execute arbitrary code through the emulation interface.
  • Access to any kind of embedded memories uses CPU 116 to do the data shuttling, by running a routine to move the memory contents into the emulation hardware registers accessible from JTAG.

Abstract

L'invention concerne un circuit intégré de dispositif cible à microcommande asynchrone incorporée qui est équipé d'une interface JTAG-TAP standard. Sur le circuit intégré, une commande d'accès TAP et une interface d'émulation peuvent intercepter et remplacer chaque instruction extraite d'une mémoire de code. Un ordinateur personnel à émulation externe peut inspecter les données et les mémoires de code embarquées en chargeant la microcommande asynchrone incorporée de les lire et écrire à l'interface JTAG-TAP. L'invention concerne en outre des registres pas-à-pas et de point d'arrêt pour mise au point et essai par l'ordinateur à émulation externe.
PCT/IB2005/052372 2004-07-16 2005-07-16 Interfaces d'emulation et de mise au point pour essais de circuits integres WO2006008721A2 (fr)

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EP05758728A EP1782204A2 (fr) 2004-07-16 2005-07-16 Interfaces d'emulation et de mise au point pour essais de circuits integres
JP2007520966A JP2008507025A (ja) 2004-07-16 2005-07-16 集積回路テスト用エミュレーション及びデバッグインターフェイス

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US58856204P 2004-07-16 2004-07-16
US60/588,562 2004-07-16
US63211204P 2004-11-30 2004-11-30
US60/632,112 2004-11-30

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008019861A1 (de) * 2008-04-17 2009-10-29 Göpel electronic GmbH Verfahren zum Steuern von Anschlusspins eines emulationsfähigen Bausteins und Anordnung zur Durchführung des Verfahrens
JP2010507135A (ja) * 2006-03-08 2010-03-04 クゥアルコム・インコーポレイテッド Ｊｔａｇの電力崩壊のデバッグ
CN101814054A (zh) * 2010-03-23 2010-08-25 苏州国芯科技有限公司 一种用于调试微控制器的指令追踪控制器
CN104239176A (zh) * 2014-10-16 2014-12-24 成都傅立叶电子科技有限公司 基于互联网的多用户多目标远程jtag调试系统
CN105528270A (zh) * 2015-12-30 2016-04-27 东风商用车有限公司 一种jtag和bdm集成调试接口及其使用方法
CN111753475A (zh) * 2020-06-28 2020-10-09 福建工程学院 一种基于Cortex-M0+微控制器仿真MSI数字逻辑芯片的方法
CN111984521A (zh) * 2019-05-23 2020-11-24 核工业理化工程研究院 一种无需jtag介入的板级调试方法
JP2022036889A (ja) * 2020-08-31 2022-03-08 北京百度網訊科技有限公司 チップを検証する方法、装置、電子デバイス、コンピュータ可読記憶媒体及びコンピュータプログラム
CN117632611A (zh) * 2023-12-05 2024-03-01 北京中天星控科技开发有限公司 一种微处理器芯片的通用测试装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020065646A1 (en) * 2000-09-11 2002-05-30 Waldie Arthur H. Embedded debug system using an auxiliary instruction queue

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020065646A1 (en) * 2000-09-11 2002-05-30 Waldie Arthur H. Embedded debug system using an auxiliary instruction queue

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
BEEREL P A: "Asynchronous circuits: an increasingly practical design solution" QUALITY ELECTRONIC DESIGN, 2002. PROCEEDINGS. INTERNATIONAL SYMPOSIUM ON 18-21 MARCH 2002, PISCATAWAY, NJ, USA,IEEE, 18 March 2002 (2002-03-18), pages 367-372, XP010589388 ISBN: 0-7695-1561-4 *
GARSIDE J D ET AL: "AMULET3i-an asynchronous system-on-chip" ADVANCED RESEARCH IN ASYNCHRONOUS CIRCUITS AND SYSTEMS, 2000. (ASYNC 2000). PROCEEDINGS. SIXTH INTERNATIONAL SYMPOSIUM ON EILAT, ISRAEL 2-6 APRIL 2000, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 2 April 2000 (2000-04-02), pages 162-175, XP010377325 ISBN: 0-7695-0586-4 *

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010507135A (ja) * 2006-03-08 2010-03-04 クゥアルコム・インコーポレイテッド Ｊｔａｇの電力崩壊のデバッグ
DE102008019861A1 (de) * 2008-04-17 2009-10-29 Göpel electronic GmbH Verfahren zum Steuern von Anschlusspins eines emulationsfähigen Bausteins und Anordnung zur Durchführung des Verfahrens
EP2110749A3 (fr) * 2008-04-17 2012-06-27 Göpel electronic GmbH Procédé de commande de puces de connexion d'un module pouvant émulsifier et agencement destiné à l'exécution du procédé
CN101814054A (zh) * 2010-03-23 2010-08-25 苏州国芯科技有限公司 一种用于调试微控制器的指令追踪控制器
CN101814054B (zh) * 2010-03-23 2012-05-02 苏州国芯科技有限公司 一种用于调试微控制器的指令追踪控制器
CN104239176A (zh) * 2014-10-16 2014-12-24 成都傅立叶电子科技有限公司 基于互联网的多用户多目标远程jtag调试系统
CN105528270A (zh) * 2015-12-30 2016-04-27 东风商用车有限公司 一种jtag和bdm集成调试接口及其使用方法
CN111984521A (zh) * 2019-05-23 2020-11-24 核工业理化工程研究院 一种无需jtag介入的板级调试方法
CN111984521B (zh) * 2019-05-23 2022-11-29 核工业理化工程研究院 一种无需jtag介入的板级调试方法
CN111753475A (zh) * 2020-06-28 2020-10-09 福建工程学院 一种基于Cortex-M0+微控制器仿真MSI数字逻辑芯片的方法
CN111753475B (zh) * 2020-06-28 2022-06-28 福建工程学院 一种基于Cortex-M0+微控制器仿真MSI数字逻辑芯片的方法
JP2022036889A (ja) * 2020-08-31 2022-03-08 北京百度網訊科技有限公司 チップを検証する方法、装置、電子デバイス、コンピュータ可読記憶媒体及びコンピュータプログラム
CN117632611A (zh) * 2023-12-05 2024-03-01 北京中天星控科技开发有限公司 一种微处理器芯片的通用测试装置

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EP1782204A2 (fr) 2007-05-09
JP2008507025A (ja) 2008-03-06

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