WO2006008721A3 - Interfaces d'emulation et de mise au point pour essais de circuits integres - Google Patents

Interfaces d'emulation et de mise au point pour essais de circuits integres Download PDF

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Publication number
WO2006008721A3
WO2006008721A3 PCT/IB2005/052372 IB2005052372W WO2006008721A3 WO 2006008721 A3 WO2006008721 A3 WO 2006008721A3 IB 2005052372 W IB2005052372 W IB 2005052372W WO 2006008721 A3 WO2006008721 A3 WO 2006008721A3
Authority
WO
WIPO (PCT)
Prior art keywords
emulation
testing
integrated circuit
asynchronous microcontroller
microcontroller
Prior art date
Application number
PCT/IB2005/052372
Other languages
English (en)
Other versions
WO2006008721A2 (fr
Inventor
Fabrizio Campanale
Jens Muttersbach
Andrea Foni
Original Assignee
Koninkl Philips Electronics Nv
Philips Corp
Fabrizio Campanale
Jens Muttersbach
Andrea Foni
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Philips Corp, Fabrizio Campanale, Jens Muttersbach, Andrea Foni filed Critical Koninkl Philips Electronics Nv
Priority to EP05758728A priority Critical patent/EP1782204A2/fr
Priority to JP2007520966A priority patent/JP2008507025A/ja
Publication of WO2006008721A2 publication Critical patent/WO2006008721A2/fr
Publication of WO2006008721A3 publication Critical patent/WO2006008721A3/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3648—Software debugging using additional hardware
    • G06F11/3656—Software debugging using additional hardware using a specific debug interface

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Debugging And Monitoring (AREA)

Abstract

L'invention concerne un circuit intégré de dispositif cible à microcommande asynchrone incorporée qui est équipé d'une interface JTAG-TAP standard. Sur le circuit intégré, une commande d'accès TAP et une interface d'émulation peuvent intercepter et remplacer chaque instruction extraite d'une mémoire de code. Un ordinateur personnel à émulation externe peut inspecter les données et les mémoires de code embarquées en chargeant la microcommande asynchrone incorporée de les lire et écrire à l'interface JTAG-TAP. L'invention concerne en outre des registres pas-à-pas et de point d'arrêt pour mise au point et essai par l'ordinateur à émulation externe.
PCT/IB2005/052372 2004-07-16 2005-07-16 Interfaces d'emulation et de mise au point pour essais de circuits integres WO2006008721A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP05758728A EP1782204A2 (fr) 2004-07-16 2005-07-16 Interfaces d'emulation et de mise au point pour essais de circuits integres
JP2007520966A JP2008507025A (ja) 2004-07-16 2005-07-16 集積回路テスト用エミュレーション及びデバッグインターフェイス

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US58856204P 2004-07-16 2004-07-16
US60/588,562 2004-07-16
US63211204P 2004-11-30 2004-11-30
US60/632,112 2004-11-30

Publications (2)

Publication Number Publication Date
WO2006008721A2 WO2006008721A2 (fr) 2006-01-26
WO2006008721A3 true WO2006008721A3 (fr) 2006-12-21

Family

ID=35462490

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2005/052372 WO2006008721A2 (fr) 2004-07-16 2005-07-16 Interfaces d'emulation et de mise au point pour essais de circuits integres

Country Status (3)

Country Link
EP (1) EP1782204A2 (fr)
JP (1) JP2008507025A (fr)
WO (1) WO2006008721A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7263427B2 (ja) 2020-08-31 2023-04-24 ベイジン バイドゥ ネットコム サイエンス テクノロジー カンパニー リミテッド チップを検証する方法、装置、電子デバイス、コンピュータ可読記憶媒体及びコンピュータプログラム

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070214389A1 (en) * 2006-03-08 2007-09-13 Severson Matthew L JTAG power collapse debug
DE102008019861A1 (de) * 2008-04-17 2009-10-29 Göpel electronic GmbH Verfahren zum Steuern von Anschlusspins eines emulationsfähigen Bausteins und Anordnung zur Durchführung des Verfahrens
CN101814054B (zh) * 2010-03-23 2012-05-02 苏州国芯科技有限公司 一种用于调试微控制器的指令追踪控制器
CN104239176A (zh) * 2014-10-16 2014-12-24 成都傅立叶电子科技有限公司 基于互联网的多用户多目标远程jtag调试系统
CN105528270B (zh) * 2015-12-30 2018-03-30 东风商用车有限公司 一种jtag和bdm集成调试接口及其使用方法
CN111984521B (zh) * 2019-05-23 2022-11-29 核工业理化工程研究院 一种无需jtag介入的板级调试方法
CN111753475B (zh) * 2020-06-28 2022-06-28 福建工程学院 一种基于Cortex-M0+微控制器仿真MSI数字逻辑芯片的方法
CN117632611B (zh) * 2023-12-05 2024-05-14 北京中天星控科技开发有限公司 一种微处理器芯片的通用测试装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020065646A1 (en) * 2000-09-11 2002-05-30 Waldie Arthur H. Embedded debug system using an auxiliary instruction queue

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020065646A1 (en) * 2000-09-11 2002-05-30 Waldie Arthur H. Embedded debug system using an auxiliary instruction queue

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
BEEREL P A: "Asynchronous circuits: an increasingly practical design solution", QUALITY ELECTRONIC DESIGN, 2002. PROCEEDINGS. INTERNATIONAL SYMPOSIUM ON 18-21 MARCH 2002, PISCATAWAY, NJ, USA,IEEE, 18 March 2002 (2002-03-18), pages 367 - 372, XP010589388, ISBN: 0-7695-1561-4 *
GARSIDE J D ET AL: "AMULET3i-an asynchronous system-on-chip", ADVANCED RESEARCH IN ASYNCHRONOUS CIRCUITS AND SYSTEMS, 2000. (ASYNC 2000). PROCEEDINGS. SIXTH INTERNATIONAL SYMPOSIUM ON EILAT, ISRAEL 2-6 APRIL 2000, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 2 April 2000 (2000-04-02), pages 162 - 175, XP010377325, ISBN: 0-7695-0586-4 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7263427B2 (ja) 2020-08-31 2023-04-24 ベイジン バイドゥ ネットコム サイエンス テクノロジー カンパニー リミテッド チップを検証する方法、装置、電子デバイス、コンピュータ可読記憶媒体及びコンピュータプログラム

Also Published As

Publication number Publication date
EP1782204A2 (fr) 2007-05-09
WO2006008721A2 (fr) 2006-01-26
JP2008507025A (ja) 2008-03-06

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