WO2006007825A3 - Halbleiter und verfahren zu dessen herstellung - Google Patents

Halbleiter und verfahren zu dessen herstellung Download PDF

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Publication number
WO2006007825A3
WO2006007825A3 PCT/DE2005/001262 DE2005001262W WO2006007825A3 WO 2006007825 A3 WO2006007825 A3 WO 2006007825A3 DE 2005001262 W DE2005001262 W DE 2005001262W WO 2006007825 A3 WO2006007825 A3 WO 2006007825A3
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WIPO (PCT)
Prior art keywords
producing
semiconductor
same
areas
electrical contact
Prior art date
Application number
PCT/DE2005/001262
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English (en)
French (fr)
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WO2006007825A2 (de
Inventor
Xaver Schloegel
Ralf Otremba
Original Assignee
Infineon Technologies Ag
Xaver Schloegel
Ralf Otremba
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Publication date
Application filed by Infineon Technologies Ag, Xaver Schloegel, Ralf Otremba filed Critical Infineon Technologies Ag
Priority to US11/572,358 priority Critical patent/US20080185740A1/en
Publication of WO2006007825A2 publication Critical patent/WO2006007825A2/de
Publication of WO2006007825A3 publication Critical patent/WO2006007825A3/de

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    • H01L2224/48717—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
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    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • H01L2924/14—Integrated circuits
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    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/2076—Diameter ranges equal to or larger than 100 microns

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

Vorgeschlagen werden ein Halbleitermodul und ein Verfahren zu dessen Herstellung. Dabei ist es vorgesehen, dass ein Zwischenelement (50) ausgebildet ist oder wird, welches zur elektrischen Kontaktierung materiell zwischen einem vorgesehenen Kontaktbereich (30) und einem vorgesehenen Anschlussbereich (40) und in direktem materiellen und elektrischen Kontakt mit und zur Flächenanpassung zwischen diesen ausgebildet ist oder wird.
PCT/DE2005/001262 2004-07-19 2005-07-18 Halbleiter und verfahren zu dessen herstellung WO2006007825A2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/572,358 US20080185740A1 (en) 2004-07-19 2005-07-18 Semiconductor and Method For Producing the Same

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DE102004034821A DE102004034821A1 (de) 2004-07-19 2004-07-19 Halbleiter und Verfahren zu dessen Herstellung
DE102004034821.9 2004-07-19

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WO2006007825A2 WO2006007825A2 (de) 2006-01-26
WO2006007825A3 true WO2006007825A3 (de) 2006-06-01

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Publication number Priority date Publication date Assignee Title
DE102008001671A1 (de) * 2008-05-09 2009-11-12 Robert Bosch Gmbh Elektrische Bondverbindungsanordnung
DE102010038130B4 (de) * 2010-10-12 2012-04-19 Technische Universität Berlin Dickdraht-Bondanordnung und Verfahren zum Herstellen
JP6786054B2 (ja) 2017-12-18 2020-11-18 株式会社豊田中央研究所 メタンの製造装置及びそれを用いたメタンの製造方法

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US5874354A (en) * 1995-09-26 1999-02-23 Siemens Aktiengesellschaft Method for electrically connecting a semiconductor chip to at least one contact surface and smart card module and smart card produced by the method
JP2001068497A (ja) * 1999-08-26 2001-03-16 Denso Corp 半導体素子と回路基板との接続方法
US6380635B1 (en) * 1998-08-28 2002-04-30 Micron Technology, Inc. Apparatus and methods for coupling conductive leads of semiconductor assemblies
US6420256B1 (en) * 1997-04-22 2002-07-16 Micron Technology, Inc. Method of improving interconnect of semiconductor devices by using a flattened ball bond

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JP2852134B2 (ja) * 1991-02-20 1999-01-27 日本電気株式会社 バンプ形成方法
US6303977B1 (en) * 1998-12-03 2001-10-16 Texas Instruments Incorporated Fully hermetic semiconductor chip, including sealed edge sides
DE10048859B4 (de) * 2000-10-02 2005-12-15 Infineon Technologies Ag Druckkontaktanordnung sowie deren Verwendung
US6564449B1 (en) * 2000-11-07 2003-05-20 Advanced Semiconductor Engineering, Inc. Method of making wire connection in semiconductor device
DE10137872C1 (de) * 2001-08-02 2003-06-05 Infineon Technologies Ag Drahtbondkontakt
US7271497B2 (en) * 2003-03-10 2007-09-18 Fairchild Semiconductor Corporation Dual metal stud bumping for flip chip applications

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5874354A (en) * 1995-09-26 1999-02-23 Siemens Aktiengesellschaft Method for electrically connecting a semiconductor chip to at least one contact surface and smart card module and smart card produced by the method
US6420256B1 (en) * 1997-04-22 2002-07-16 Micron Technology, Inc. Method of improving interconnect of semiconductor devices by using a flattened ball bond
US6380635B1 (en) * 1998-08-28 2002-04-30 Micron Technology, Inc. Apparatus and methods for coupling conductive leads of semiconductor assemblies
JP2001068497A (ja) * 1999-08-26 2001-03-16 Denso Corp 半導体素子と回路基板との接続方法

Non-Patent Citations (1)

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Title
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 20 10 July 2001 (2001-07-10) *

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DE102004034821A1 (de) 2006-03-16
WO2006007825A2 (de) 2006-01-26

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