WO2006007785A1 - Circuit et procede de commande de basculement entre modes active et veille - Google Patents

Circuit et procede de commande de basculement entre modes active et veille Download PDF

Info

Publication number
WO2006007785A1
WO2006007785A1 PCT/CN2005/001067 CN2005001067W WO2006007785A1 WO 2006007785 A1 WO2006007785 A1 WO 2006007785A1 CN 2005001067 W CN2005001067 W CN 2005001067W WO 2006007785 A1 WO2006007785 A1 WO 2006007785A1
Authority
WO
WIPO (PCT)
Prior art keywords
board
signal
standby
master
main
Prior art date
Application number
PCT/CN2005/001067
Other languages
English (en)
French (fr)
Inventor
Quanhong Ma
Original Assignee
Huawei Technologies Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Publication of WO2006007785A1 publication Critical patent/WO2006007785A1/zh

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4295Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation

Definitions

  • the invention relates to a backup technology of a communication system, in particular to an active/standby switching control circuit and a control method thereof in a 1+1 backup system.
  • a redundancy mechanism of 1+1 backup is usually applied to the key boards in the system design.
  • 1+1 backup means that in one system, two identical boards work at the same time, one for the main and the other for the standby.
  • On the service level only the board in the active state performs service processing and implements the related bus control functions.
  • the board in the standby state does not participate in service processing and does not implement the bus control function.
  • the board in the active state When the board in the active state is faulty, the board will be transferred to the standby state for fault processing. This is called the backup. In this case, the board that is in the standby state will be transferred to the active state for service processing and implementation.
  • the related bus control function also known as the upgrade, minimizes the negative impact of the failure of a single board on the normal operation of the entire system, and greatly improves the overall reliability of the system.
  • Figure 1 shows the basic framework for the active/standby switchover control of two boards in the 1+1 sub-system. It can be seen from FIG. 1 that the master/replacement control circuits 111 and 121 of the two boards 110 and 120 participating in the backup communicate with each other through the backplane 100 to coordinate the active/standby switching control of the two boards. .
  • FIG. 2 shows the base The active/standby switching control circuit of the RS trigger model.
  • the NAND gate A 211 on the board A 210 and the NAND gate B 221 on the board B 220 pass through the back board 200 to form an RS flip-flop.
  • the ACT-A and ACT-B signals are the primary and backup status indication signals of the board A210 and the board B 220, respectively, where 0 indicates the active state and 1 indicates the standby state; CONT-A and CONT-B respectively For the control signals of board A and board B, if the signal is 0, the board is forced to enter the standby state. If the signal is 1, the board is allowed to go up.
  • the main control signal of the board and the main standby status indication signal of the board are input as the input terminals of the NAND gates 211 and 221, and The output of the gate is the main standby status indication signal of the board.
  • the input of the NAND gate A211 is the main standby control signal CONT-A of the board and the main standby status indication signal ACT-B of the board B 220, and the output thereof is the main standby state of the board.
  • Indicator signal ACT-A is the main standby control signal CONT-A of the board and the main standby status indication signal ACT-B of the board B 220, and the output thereof is the main standby state of the board.
  • Indicator signal ACT-A is the main standby control signal CONT-A of the board and the main standby status indication signal ACT-B of the board B 220, and the output thereof is the main standby state of the board.
  • Indicator signal ACT-A is the main standby control signal CONT-A of the board and the main standby
  • the system sets the active and standby control signals CONT on both boards to 0. Therefore, the primary and secondary status indication signals ACT-A and ACT of the two boards that have been operated by the NAND gate are also ACT-A and ACT.
  • -B is 1 , that is, the initial states of the two boards 210 and 220 are all in the standby state.
  • the control signal CONT of the ready-made board is set to 1, which allows the board to be transferred from the standby state to the standby state.
  • Main state At this time, if the board detects that the main standby status indication signal of the board is still 1, the main standby status indication signal ACT of the board NAND gate output is 0, indicating that the board enters the main state, that is, the main unit.
  • the system can set the master/slave control signal CONT of the board to 0 to force the board to be down and wait for fault processing. At this time, the primary and backup status indication signals of the board become 1. Since the ready-to-use standby but not control signal CONT is also set to 1, the board in the standby state can be upgraded to ensure the service of the system. Without interruption, the reliability of the system is improved. It should be noted that, as shown in FIG. 2, the primary standby status indication signal transmitted to the board on the board A 210 and the board B 220 is pulled up by the resistor 212 and the resistor 222 to ensure the primary standby status indication signal. It is high when the board is not in place.
  • the above-mentioned RS-trigger-based active/standby switching control circuit can implement the primary and backup switching control of two boards, but the following problems occur:
  • the above-mentioned RS-trigger-based active/standby switching control circuit is a combined circuit, and the control signal is burred. It is easy to cause an error in the transition of the active/standby switchover state. For example, when the board A210 is used as the main board and the board B 220 is in standby, if the main standby status indication signal ACT-A of the board A 210 has a high level glitch, the board B 220 is triggered to enter the main state. As a result, the board A 210 is downgraded, and the main standby is reversed. This phenomenon is not allowed by the 1+1 backup system.
  • the input signal should be processed by filtering glitch.
  • the self-locking function must be added to the active/standby switching control circuit to ensure When the main board is working normally, the active and standby boards of the standby board should not be affected by the active and standby status of the standby board. That is, once a board is used for the main use, unless the board itself is abnormally forced to drop or receives a backup command from the superior, the other board must not be downsized.
  • the conventional R-S flip-flop based active/standby switching control circuit is improved.
  • a signal filtering glitch circuit and a self-locking function circuit are added, and a clock signal is introduced, and the combination logic is used instead of the combination logic to realize the control of the primary standby switching, and the filter glitch is added to the main standby indication signal from the board. , filter out burrs, avoid the occurrence of the main and standby mis-switching phenomenon.
  • FIG. 3 shows an improved active/standby switching control circuit.
  • the circuit is a main control circuit of a single board in the 1+1 backup system.
  • the improved active/standby switching control circuit filters the input signal by using the clock signal CLK and the reset signal of the board. Burr handling.
  • the circuit mainly comprises two modules: a signal filtering glitch module 302 and a main standby processing module 301.
  • the signal filtering glitch module 302 receives the main standby state indication signal ACT-B from the board, the clock signal CLK of the board, and the reset signal of the board, on the rising edge or the falling edge of the board clock signal CLK and the board
  • the reset signal is invalid, that is, when the board is not reset
  • the main standby state indication signal ACT-B of the board is subjected to filter glitch processing to prevent the master/slave error switching due to the glitch of the board main standby state indication signal ACT-B. And outputting the filter glitch processed board main standby status indication signal ACT-B to the main standby processing module 301.
  • the main standby processing module 301 receives the filter glitch processed board main standby state indication signal ACT-B output by the signal filtering glitch module 302, the clock signal CLK of the board, the reset signal of the board, and the main board control signal CONT of the board. On the rising or falling edge of the clock signal of this board, judge the reset signal of the board, the main and standby control signals CONT, and the main standby status indication signal ACT-B of the board. If the board reset signal, active/standby control The signal CONT and the main standby status indication signal ACT-B of the board are invalid, that is, the board is upgraded when the board is neither reset nor raised, and the board is not upgraded.
  • This module outputs the main standby status indication signal ACT-A of the board. This signal is output to other modules of the board on the one hand, and is output to the active/standby switching control circuit of the board on the other hand.
  • the above-mentioned clock signal CLK of the present board implements the timing control of the active/standby switching control circuit, that is, the main standby processing module 301 and the signal filtering glitch module 302 in the active/standby switching control circuit are both raised or falling by the clock signal CLK of the board. trigger.
  • the reset signal of this board is used to indicate whether the board is in the reset state. If the board is reset, the main standby switching control circuit shown will force the board to be in the standby state.
  • the board's active and standby control signals, CONT are used to indicate whether the board is forced to be in standby state.
  • the improved active/standby switching control circuit shown in Figure 3 works as follows:
  • the active/standby control signal CONT or reset signal of the board will force the board to be in the standby state.
  • the board's active and standby control signals CONT and reset signal will indicate that the board can be upgraded.
  • the main standby processing module 301 in the active/standby switching control circuit detects the board main standby state indication signal ACT-B' after filtering the glitch, and if the board is in the standby state, the board is upgraded; In the active state, the board remains in standby until the board is actively provisioned.
  • a self-locking function circuit (not shown) is added, and the self-locking function circuit ensures that once the board is upgraded, the main standby state indication signal to the board will be It will not affect the main state of the board, unless the board is actively reduced due to faults or abnormalities, that is, any state of the board will not cause the board to be reduced.
  • the primary standby switching control circuit shown in FIG. 3 implements the primary standby switching control of the 1+1 backup system, and the signal glitching module is added and the sequential logic is applied, which can overcome the The master-slave error switching phenomenon caused by the glitch of the control signal in the active/standby switching control circuit of the RS flip-flop.
  • the method also has the following problems: Since the timing logic is introduced in the solution, the two boards shown in FIG. 2 are inevitably: the board A and the board B are identified for the primary standby state of the board. Delayed. For example, if board A is used at time t0, board B can only recognize that board A is in the active state at time t0+T, where T is the primary standby status indication signal and arrives at the board through physical transmission and digital processing. And is recognized by the board for the time required.
  • the board B considers that the board A is in the standby state, so the board B may also rise, and because the board A and The board B has a self-locking function. If the board B is upgraded, the board A and the board B are in the active state at the same time. This double master conflict is not allowed in the design of the 1+1 backup system.
  • the time to to tO+T is the time that may lead to dual masters, also known as the dual master collision domain.
  • the improved primary and standby switching control circuit shown in FIG. 3 overcomes the operation shown in FIG.
  • the master-slave switching control circuit has the problem of master-slave error switching, but at the same time brings the problem of double master conflict, which is also not allowed by the 1+1 backup system. Summary of the invention
  • an object of the present invention is to provide an active/standby switching control circuit that solves the problem of dual master conflicts that may occur in the prior art.
  • the invention discloses an active/standby switching control circuit, which comprises a main standby processing module for performing primary and standby switching control and an assistant reservation processing module for performing a master reservation control.
  • the owner reservation processing module receives the boarding assistant reservation instruction signal of the board, and determines the boarding assistant reservation instruction signal of the board, and if the board owner's reservation instruction signal is invalid, the board upgrades the master reservation. And outputting the upgrade request signal of the board to the main standby processing module and the active/standby switching control circuit of the board;
  • the main standby processing module receives the promotion reservation instruction signal of the board output by the promotion reservation processing module, and if the board promotion main reservation instruction signal remains valid for a predetermined time, the board is controlled to be upgraded, and the board is output. Primary standby status indication signal.
  • the mode-up reservation processing module of the present invention further receives the clock signal of the board, and judges the boarding main reservation instruction signal of the board on the valid edge of the clock signal;
  • the primary standby processing module further receives the clock signal of the board, and determines the promotion reservation indication signal of the board on the valid edge of the clock signal of the board.
  • the upgrade master reservation processing module of the present invention further receives the reset signal of the board, and when the reset signal of the board is valid, setting the board upgrade master reservation indication signal is invalid;
  • the main standby processing module further receives the reset signal of the board, and when the reset signal of the board is valid, setting the board upgrade instruction signal is invalid.
  • the upgrade main reservation processing module of the present invention further receives the clock signal of the board and the reset signal of the board, and when the reset signal of the board is valid, setting the board main reservation instruction signal is invalid. And determining, according to the valid edge of the clock signal of the board, the rising main reservation instruction signal of the board; the main standby processing module further receiving the clock signal of the board and the reset signal of the board, and setting when the reset signal of the board is valid.
  • the main standby status indication signal of the board is invalid, and the rising main reservation indication signal of the board is judged on the valid edge of the clock signal of the board.
  • the circuit of the present invention further includes a signal filtering glitch module that receives an upgrade request indication signal from the pair of boards, performs a glitch processing on the singer's reservation indication signal from the board, and filters the burr-treated board
  • the assistant reservation instruction signal is output to the promotion reservation processing module;
  • the step-up reservation processing module determines the riser reservation instruction signal of the board, and determines the leader reservation instruction signal of the board subjected to the filter glitch processing.
  • the signal filtering glitch module of the present invention further receives the clock signal of the board and the reset signal of the board, and filters the rising main reservation indication signal from the board when the valid edge of the board clock signal and the board reset signal are invalid.
  • the burr is processed, and the filtered burr-treated board-up main reservation instruction signal is output.
  • the circuit of the present invention further includes a slot number detecting module, the module receives the slot number of the board from the backplane, determines the priority of the board according to the slot number of the board, and outputs the priority indication signal of the board to the main board.
  • a slot number detecting module receives the slot number of the board from the backplane, determines the priority of the board according to the slot number of the board, and outputs the priority indication signal of the board to the main board.
  • the primary standby processing module further adjusts the predetermined time based on a priority indication signal.
  • the slot number detecting module of the present invention further receives the clock signal of the board and the reset signal of the board, and determines the priority of the board according to the slot number of the board when the valid edge of the clock signal of the board is invalid and the reset signal of the board is invalid. Level, and output the board priority indication signal.
  • the upgrade master reservation processing module of the present invention further receives the master/slave control signal of the board, and sets the board upgrade master reservation indication signal to be invalid when the master/slave control signal of the board is valid.
  • the primary standby processing module of the present invention further receives the active/standby control signals of the board, and is in the present When the board master/slave control signal is valid, the main standby status indication signal of this board is invalid.
  • the moderator reservation processing module of the present invention further receives the main standby state indication signal output by the main standby processing module, and sets the board upgrade master reservation indication signal to be valid when the main standby state indication signal of the board is valid.
  • the active/standby switching control method of the present invention includes the following steps:
  • step b the board is set to the standby state, and then the process ends;
  • the method of the present invention is triggered by the valid edge of the clock signal of the board.
  • the valid edge of the clock signal of the board is: a rising edge or a falling edge of the clock signal of the board.
  • the method for determining whether the board is ready includes:
  • A2. Determine whether the board can be used. If yes, the board is ready; otherwise, the board is not ready.
  • the method for determining whether the board is in the reset state is as follows: detecting the reset signal of the board, if the reset signal is valid, the board is in a reset state.
  • the method for determining whether the board can be used as the main part is as follows: detecting the active/standby control signals of the board. If the active/standby control signals are invalid, the board can be used.
  • the step c further includes: determining the priority of the board, and if the priority of the board is high, directly raising the master, and then ending the process; otherwise, performing Step d.
  • the method for setting the priority of the board in the present invention is as follows: The priority of the board is set according to the slot number of the board on the backplane in advance;
  • the method for determining the priority of the board is as follows: The priority of the board is determined according to the slot number of the board on the backplane.
  • the method of the present invention sends an upgrade request indication signal to the opposite board after the board is upgraded or the owner is upgraded, and the board is instructed to make an appointment;
  • the method for determining whether the board can be upgraded according to the step a is: detecting the board-up main reservation instruction signal sent to the board by the board, if the signal indicates that there is no appointment for the board, the board can be upgraded. Master Appointment; If the signal indicates that the board has been upgraded, the board cannot be upgraded.
  • the predetermined time described in step b is three times the time when the board's main reservation instruction signal is physically and digitally processed to reach the board and be recognized by the board.
  • step b after the board is upgraded, the main state is self-locked, and the main state is maintained.
  • the primary and backup switching control circuit and method shown in the present invention employs a master reservation mechanism, that is, the board must first make an appointment before the promotion, and can only be promoted after the reservation is successful. This can effectively avoid the double master conflict problem in the prior art and enhance the reliability of the system.
  • the present invention also adds a priority mechanism, that is, if the priority of the board is higher, the direct upgrade is performed without waiting for reservation; and if the priority of the board is lower, waiting for a certain time, if During this period of time, if there is no appointment for the board, the reservation is successful, and the board is upgraded; if the board is upgraded during this time, the board fails to make an appointment, and the standby status is not maintained. change. This can prevent the increase of control complexity caused by multiple arbitrations and the possible state oscillation phenomenon, and the P strip has low control complexity.
  • Figure 1 shows the basic framework of the active/standby switchover control of two boards in a 1+1 backup system.
  • Figure 2 shows the active/standby switchover control circuit based on the R-S trigger model.
  • Figure 3 shows the improved active/standby switching control circuit
  • FIG. 4 is a schematic diagram of an active/standby switching control circuit according to the present invention.
  • FIG. 5 is a timing diagram of input and output signals in the active/standby switching control circuit according to the present invention
  • FIG. 6 is a flowchart of an active/standby switching control method according to a preferred embodiment of the present invention. Mode for carrying out the invention
  • the present invention uses a single board upgrade reservation mechanism, that is, the board must first make an appointment before the promotion, and only after the reservation is successful. Can be promoted.
  • the present invention also adds a single board upgrade master reservation indication signal as a handshake signal for communication between the two boards, and the main standby state indication signal of the board is no longer used for handshake communication of the two boards. It is only used for control and status indication inside the board.
  • the above-mentioned promotion reservation mechanism must ensure that a board can make an appointment for the promotion only if it detects that there is no appointment for the board. If it is detected that the board has been upgraded, No promotion appointment will be made.
  • the present invention discloses an active/standby switching control circuit.
  • Figure 4 shows the active/standby switching control circuit of the present invention.
  • the main control circuit of the present invention mainly includes a signal filtering glitch module 401, a rising main reservation processing module 402, a main standby processing module 403, and a slot number detecting module 404.
  • the signal filtering glitch module 401 receives the assistant reservation instruction signal from the board TRY-B, the clock signal CLK of the board and the reset signal of the board, when the valid edge of the clock signal CLK of the board, for example, the rising edge or the falling edge, and the reset signal of the board is invalid, that is, when the board is not reset,
  • the booster reservation instruction signal TRY-B from the board is subjected to filter glitch processing to prevent the master/slave erroneous switching due to the glitch of the board main standby state indication signal, and the module outputs the filtered glitch processing board for the master reservation.
  • the indication signal TRY-B is sent to the master reservation processing module 402.
  • the main reservation processing module 402 receives the board-up reservation instruction signal TRY-B outputted by the signal filtering glitch module 401, the main standby status indication signal ACT-A output by the main standby processing module 403, the clock signal CLK of the board, The reset signal of the board and the main and standby control signals CONT of the board; on the rising or falling edge of the clock signal CLK of the board, first determine the reset signal of the board and the main control signal CONT, if the board reset signal or the active/standby control signal CONT is valid, that is, if the board is reset or the board is forced to be used, the board cannot be upgraded. If both signals are invalid, then the board's main standby status indication signal ACT-A is judged.
  • the board status indication signal ACT-A Valid that is, the board has been upgraded
  • the board must be in the state of the appointment of the master; otherwise, the decision of the assistant reservation instruction signal TRY-B from the board is judged, if the board of the board is reserved for the instruction indication signal TRY-B 'Invalid, that is, there is no appointment for the board, then the board is controlled.
  • the module outputs the main standby instruction signal TRY-A of the board to the main standby processing module 403 and the main standby switching control circuit to the board.
  • the slot number detecting module 404 receives the slot number indication signal of the board from the backplane, the clock signal CLK of the board, and the reset signal of the board, and detects the slot number of the board on the backboard.
  • the rising edge or falling edge is invalid and the reset signal of the board is invalid, that is, when the board is not reset, the priority of the board is determined according to the slot number of the board, and the priority indication signal of the board is output to the main standby processing module 403. ;
  • the main standby processing module 403 receives the upgrade request indication signal TRY-A of the board output by the upgrade main reservation processing module 402, and the priority indication letter of the board output by the slot number detection module 404. No., the clock signal CLK of the board, the reset signal of the board, and the main control signal CONT of the board, on the rising edge or the falling edge of the clock signal CLK of the board, if the board rises the main reservation indication signal TRY-A at the predetermined time
  • the main board remains active and the reset signal of the board is invalid, that is, the board has been upgraded to the master and the board is not upgraded for a predetermined time, then the board is controlled.
  • the main standby processing module 403 can take priority according to the board.
  • the level indication signal adjusts the above predetermined time to ensure that the board can be immediately upgraded when the priority of the board is high, and no reservation is required.
  • the module outputs the main standby status indication signal of the board to the main reservation processing module 402 and other modules of the board.
  • the clock signal CLK of the board is used as an input signal to realize timing control of the four-part circuit, so that the logic function of the main standby switching control circuit is triggered by the rising edge or the falling edge of the clock of the board.
  • the reset signal of the board is input as a control signal to the four modules of the active/standby switching control circuit shown to indicate whether the board is in the reset state. If the board is reset, the active/standby switching control circuit will force the board to be down or Keep it in standby.
  • the function of the active/standby control signal CONT of the board is the same as that of the active/standby control signals of the board in the prior art, which is used to indicate whether the board is forced to the standby state.
  • the signal filtering glitch module is implemented in the same manner as the signal filtering glitch module of the prior art active/standby switching control circuit.
  • the slot number detecting module is configured to detect the slot number of the board, determine the priority of the board, and output the priority indication signal to the primary standby processing module 403.
  • the priority mechanism of the present invention is as follows: A board with a higher priority can be preferentially upgraded, and no reservation waiting is required, that is, when a board with a higher priority is upgraded, the board can be upgraded immediately; , must wait for a certain period of time after the appointment of the lord, if there is no appointment for the board during this time, the appointment is successful, the board is upgraded; if during this time If the board is upgraded, the reservation fails, and the board remains in the standby state.
  • the method for determining the priority of the board is as follows:
  • the board with the slot number is an odd number, and the board with the even slot number has a lower priority.
  • the premise of the above-mentioned priority setting method is to ensure that the slot numbers of the two boards cannot be odd at the same time or even numbers at the same time.
  • the active/standby switching control circuit of the present invention is not limited to the method for determining the priority of the board by using the slot number of the detecting board, that is, the slot number detecting module is only the active/standby switching control circuit of the present invention.
  • the method of the present invention can also use other methods for setting the priority of the board, such as setting the priority of the board in advance.
  • the active/standby switching control circuit of the present invention retains the prior art self-locking function (not shown in FIG. 4), and the self-locking function ensures the primary standby state of the board once the board is upgraded.
  • the indicator signal will not affect the main state of the board, unless the board is actively reduced due to faults or abnormalities, that is, any state of the board will not cause the board to be reduced.
  • the active/standby control signal CONT or reset signal of the board is valid, which will force the board to be in standby state.
  • the main reservation processing module 402 will detect the board-up main reservation instruction signal output by the signal filtering glitch module 401. TRY-B', if there is no promotion reservation for the board, the board performs the promotion reservation, and outputs the board upgrade main reservation instruction signal TRY-A to the main standby processing module 403 and the active/standby switching control circuit of the board. ;
  • the priority indication signal of the board outputted by the slot number detecting module 404 is detected. If the priority of the board is higher, the board is directly upgraded without performing Waiting for an appointment; if the priority of this board is low, wait for a certain The time, if during this time, there is no appointment for the board, the reservation is successful, the board is upgraded; if the board is upgraded during this time, the board upgrade fails. Keep the standby state unchanged;
  • the board will remain in the active state until the board's active and standby control signals CONT force the board to be down.
  • the board in the active state If the board in the active state is working abnormally or fails, you can force the board to go through the active and standby control signals CONT of the board and wait for the fault. At this time, the board in standby mode can be upgraded to ensure that the system business will not be interrupted.
  • the primary and backup switching control circuit shown in Fig. 4 can implement the primary and backup switching control of the 1+1 backup system.
  • FPGAs field programmable gate arrays
  • Fig. 5 shows the timings of input and output signals of the main control circuit of the present invention.
  • the signal timing shown in FIG. 5 is measured in the time interval from time 0 to time 4T, and it is assumed that the priority of the board A including the active/standby switching control circuit is higher than the priority of the board B, and The two boards are not reset during the period.
  • the time interval T is the time required for the main reservation instruction signal to reach the board and be recognized by the board after physical transmission and digital processing.
  • TRY-A and TRY-B respectively indicate the main reservation instruction signal on the board A and the board B.
  • the low level indicates that the board is for the master reservation, and the high level indicates that the board has no promotion reservation;
  • ACT-A and ACT-B indicate the primary and backup status indicators on board A and board B, respectively. No. Low indicates that the board is in the main state, and high level indicates that the board is in the standby state;
  • TRY-A indicates the signal that the board's AUX reservation indication signal reaches the board B.
  • the signal is the same as the TRY-A waveform, but has a T time delay.
  • TRY-B indicates the signal that the board's assistant reservation indication signal reaches the board A.
  • the signal is the same as the TRY-B waveform, but it also has a T time delay.
  • the board does not have a master reservation; the board B is ready after power-on, and detects the board-up reservation instruction signal TRY-A of the board A is high. Level, then the master reservation is made at time T, that is, the main reservation instruction signal TRY-B is set to a low level. Since the priority of the board B is low, the board B cannot be directly raised, and it is necessary to wait for a period of time. Therefore, the board B enters the reservation waiting state.
  • the board-receiving reservation instruction signal TRY-B of the board B reaches the board A at the time of 2T. Therefore, the board A does not know that the board B has made the promotion reservation before the 2T time. Therefore, in the 0 to 2T time interval, at the latest 2T, if the board A is ready, the board A can make an appointment, and since the board A has a higher priority, no reservation waiting is required, so The board A will be directly upgraded at the same time as the appointment of the master. As shown in Figure 5, the board A picks up the master reservation and raises the master at the same time.
  • the board B has detected that the board A has been upgraded in the 2T ⁇ 3T time interval, and the board B has failed to make a reservation, that is, the board A is used for the main board and the board B is reserved.
  • the board is used for the main board and the board B is reserved.
  • board B can detect that board A has made a master reservation at time T and does not perform the master reservation operation.
  • the board B can detect that the board A has been upgraded in the T ⁇ 2T time interval, which will result in the board. B-up master appointment failed. If the board A does not rise in the 0 to 2T time interval (this is not shown in Figure 5:), then after 2 ⁇ , it can be detected that the board has been upgraded, so it will not be at 2 ⁇ . The main operation will be carried out later.
  • the wait time is set to 3T.
  • the invention also discloses a method for master/slave switching control, which adopts a reservation mechanism and a priority policy to solve the double master conflict problem.
  • FIG. 6 shows the flow of an active/standby switching control method in accordance with a preferred embodiment of the present invention.
  • the priority of the board needs to be determined in advance.
  • the method for determining the priority of the board is various.
  • the system may be randomly specified in advance or determined according to the slot number of the board. .
  • the method for setting the priority of the board in the embodiment shown in FIG. 6 is: determining the priority of the board according to the slot number of the board on the backboard. For example, if the slot number is an odd number, the priority is If the slot number is even, the priority is low. You can also set the slot number to an even number. The priority of the board is set to high, and the priority of the board with the odd slot number is set to low.
  • the method of the present invention is triggered by the rising or falling edge of the clock signal of the board.
  • the active/standby switching control method of the present invention mainly includes the following steps:
  • step 601 After the board is powered, proceed to step 601;
  • Step 601 Determine whether the board is in a reset state, and if yes, go to step 608; otherwise, go to step 602;
  • Step 602 Determine whether the board is available for the main use, and if yes, perform step 603; no, "J, perform step 608;
  • the method for judging whether the board can be used for the main purpose is: detecting the main control signal CONT of the board. If the main control signal CONT of the board indicates that the board can be used for the main use, the board can be used for the main purpose; The signal CONT indicates that the board is forced to be used, and the board cannot be used for the main purpose;
  • Step 603 Determine whether the board has been upgraded, if yes, go to step 608; otherwise, go to step 604;
  • the board since the board is valid after setting the master's reservation, the board's main reservation signal is valid. Therefore, the board can determine whether the board has been raised by detecting the board's assistant reservation instruction signal. Master appointment
  • Step 604 Determine the priority of the board, if it is high, go to step 607; otherwise, go to step 605;
  • Step 605 The board is upgraded to the master, and then step 606 is performed;
  • Step 606 Maintain the standby state 3T time, and check whether the board has been upgraded, if yes, go to step 608; otherwise, go to step 607;
  • Step 607 Set the board as the main state, and then end the process; In this step, after the board is upgraded, the board will also set its output to the board's master reservation signal. After the board is upgraded, the board must also make an appointment.
  • Step 608 Set the board to the standby state, and then end the process.
  • the above method retains the self-locking function of the prior art, that is, once the board is upgraded, the board will remain in the main state until the board is reset or the board's active/standby control signal CONT forces the board to be down.
  • the active board is faulty or fails, you can use the active/standby control signals of the board to force the board to be down.
  • the board in standby mode can be upgraded to ensure that the system services are not interrupted.
  • the method of the present invention introduces a master reservation mechanism and a priority policy, which can effectively avoid the double master conflict problem.
  • the active/standby switching control circuit and method of the present invention retains the prior art sequential logic and self-locking functions, thereby avoiding the occurrence of active/standby error switching, and on the basis of the prior art.
  • the priority reservation mechanism and the priority policy are added, which effectively avoids the double master conflict caused by the delay of the recognition of the board's primary standby state by the two boards, thereby enhancing the 1+1 backup system. reliability.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)

Description

一种主备倒换控制电路及其控制方法 技术领域
本发明涉及到通信系统的备份技术, 特别涉及到一种 1+1备份系统 中的主备倒换控制电路及其控制方法。 发明背景 - 在通信系统中, 为了提高系统整体的可靠性, 通常在系统设计中对 关键单板采用 1+1备份的冗余机制。其中, 1+1备份是指在一个系统中, 有两块相同的单板同时工作, 一块主用, 另一块备用。 从业务层面上来 讲, 只有处于主用状态的单板进行业务处理和实现相关的总线控制功 能, 处于备用状态的单板不参与业务处理, 也不实现总线的控制功能。 当主用状态的单板发生故障的时候, 该单板将转移到备用状态等待故障 处理, 又称为降备; 此时, 原来处于备用状态的单板将转移到主用状态 进行业务处理和实现相关的总线控制功能, 又称为升主, 使得单个单板 的故障对整个系统正常运行的负面影响最小化, 大大提高系统整体的可 靠性。
需要说明的是, 参与 1+1备份的两块单板在同一时间只能有一块单 板处于主用状态, 不能出现两块单板同时处于主用状态的情况, 这个控 制是由位于各个单板内的主备倒换控制模块来实现的。
图 1显示了 1+1 分系统两块单板进行主备倒换控制的基本框架。 从图 1可以看出, 参与备份的两个单板 110、 120的主^到换控制电路 111、 121通过背板 100互通主备倒换握手信号, 用于协调两个单板的主 备倒换控制。
传统的主备倒换控制电路是基于 R-S触发器模型的。 图 2显示了基 于 R-S触发器模型的主备倒换控制电路。 如图 2所示, 单板 A 210上的 与非门 A 211和单板 B 220上的与非门 B 221经过背板 200构成了一个 R-S触发器。 图 2中, ACT-A和 ACT-B信号分别为单板 A210和单板 B 220的主备用状态指示信号, 其中, 0表示主用状态, 1表示备用状态; CONT-A和 CONT-B分别为单板 A和单板 B的控制信号,如果该信号为 0, 则强制本板进入备用状态, 如果该信号为 1, 则允许本板升主。
从图 2可以看出, 在单板 A 210和单板 B 220上, 本板主备控制信 号和对板的主备用状态指示信号作为 2输入端与非门 211、 221的输入, 而与非门的输出为本板的主备用状态指示信号。 以单板 A 210为例, 与 非门 A211的输入为本板主备控制信号 CONT-A和对板单板 B 220的主 备用状态指示信号 ACT-B , 其输出为本板的主备用状态指示信号 ACT-A。
这样, 在系统初始状态, 系统将两个单板上的主备控制信号 CONT 都设置为 0, 因此, 经过与非门還辑操作的两个单板的主备用状态指示 信号 ACT-A和 ACT-B均为 1 , 即两个单板 210、 220的初始状态都为备 用状态。 当两个单板 210、 220上电启动、 软件加载、 初始化及自检等 操作完成后, 准备就绪的单板上的控制信号 CONT就被置为 1 , 即允许 该单板从备用状态转移到主用状态。 此时, 如果该单板检测到对板的主 备用状态指示信号仍为 1 , 则本板与非门输出的主备用状态指示信号 ACT为 0, 指示本板进入主用状态, 即升主。
若处于主用状态的单板检测到故障, 系统则可以将本板主备控制信 号 CONT设置为 0, 强制本板降备, 等待故障处理。 此时, 该单板的主 备用状态指示信号变为 1 , 由于准备就绪的备用但不上的控制信号 CONT也被置为 1 , 所以处于备用状态的单板就可以升主, 保证系统的 业务不中断, 提高了系统的可靠性。 需要说明的是, 如图 2所示, 在单板 A 210和单板 B 220上对板传 送过来的主备用状态指示信号要经过电阻 212和电阻 222的上拉, 保证 该主备用状态指示信号在对板没有在位的情况下为高电平。
上述基于 R-S触发器的主备倒换控制电路可以实现两块单板的主备 用倒换控制, 但是会产生以下问题: 上述基于 R-S触发器的主备倒换控 制电路是一种组合电路, 控制信号的毛刺很容易导致主备倒换状态发生 错误的转移。比如,在单板 A210主用 ,单板 B 220备用时,若单板 A 210 的主备用状态指示信号 ACT-A有一个高电平的毛刺, 就会触发单板 B 220进入主用状态, 进而导致单板 A 210降备, 从而出现主备误倒换的 . 现象, 这是 1+1备份系统所不允许的。
所以, 为了避免上述主备误倒换的情况, 在主备倒换控制模块的设 计中, 应当对输入的信号进行滤毛刺的处理, 另外, 还需要在主备倒换 控制电路中加入自锁功能, 保证当主用单板正常工作时, 无论备用单板 的主备用状态如何都不应影响主用单板的正常工作, 更不能因为备用单 板的状态导致主用单板降备而产生主备倒换, 也就是说, 某块单板一旦 主用, 除非本单板本身异常强制降备或者收到上级的降备命令, 其他情 况均不得使主用单板降备。
为了解决上述的问题, 对传统的基于 R-S触发器的主备倒换控制电 路进行了改进。 在改进的电路中, 加入了信号滤毛刺电路以及自锁功能 电路, 并且引入了时钟信号, 用时序逻辑代替组合逻辑实现主备用倒换 的控制, 对于来自对板的主备用指示信号增加滤毛刺处理, 滤除毛刺, 避免了主备误倒换现象的发生。
图 3显示了改进的主备倒换控制电路。 该电路为 1+1备份系统中某 一块单板的主 ^到换控制电路, 从图 3可以看出, 改进的主备倒换控制 电路利用时钟信号 CLK和本板的复位信号对输入信号进行滤毛刺处理。 该电路主要包括两个模块:信号滤毛刺模块 302和主备用处理模块 301。 其中, 信号滤毛刺模块 302接收来自对板的主备用状态指示信号 ACT-B, 本板的时钟信号 CLK 以及本板的复位信号, 在本板时钟信号 CLK 的上升沿或者下降沿且本板的复位信号无效时, 即本板没有复位 时,对对板的主备用状态指示信号 ACT-B进行滤毛刺处理, 防止由于对 板主备用状态指示信号 ACT-B的毛刺带来的主备误倒换,并输出经过滤 毛刺处理的对板主备用状态指示信号 ACT-B,到主备用处理模块 301。
主备用处理模块 301接收信号滤毛刺模块 302输出的经过滤毛刺处 理的对板主备用状态指示信号 ACT-B,、 本板的时钟信号 CLK、 本板的 复位信号以及本板主备控制信号 CONT, 在本板时钟信号的上升沿或者 下降沿, 对本板的复位信号、 主备控制信号 CONT以及对板的主备用状 态指示信号 ACT-B,进行判断, 如果本板的复位信号、 主备控制信号 CONT 以及对板的主备用状态指示信号 ACT-B,均无效, 即在本板既没 有复位、 又可以升主并且对板也没有升主的情况下, 本板升主。 该模块 输出本板的主备用状态指示信号 ACT-A,该信号一方面输出到本板的其 他模块, 另一方面输出到对板的主备倒换控制电路。
上述的本板时钟信号 CLK实现主备倒换控制电路的时序控制,即所 示主备倒换控制电路中的主备用处理模块 301和信号滤毛刺模块 302均 由本板时钟信号 CLK 的上升沿或下降沿触发。 本板的复位信号, 用于 指示本板是否处于复位状态, 如果本板复位, 所示主备用倒换控制电路 会强制本板为备用状态。 本板主备控制信号 CONT, 用于指示是否强制 本板处于备用状态。
图 3所示的改进的主备倒换控制电路的工作原理如下:
在初始状态或者单板复位时, 该单板的主备控制信号 CONT或复位 信号将强制本板为备用状态。 在本板准备就绪时, 本板主备控制信号 CONT及复位信号将指示本 板可以升主。 此时, 主备倒换控制电路中的主备用处理模块 301将检测 滤除毛刺后的对板主备用状态指示信号 ACT-B', 如果对板处于备用状 态, 则本板升主; 如果对板处于主用状态, 则本板保持备用状态, 直到 对板主动降备。
需要说明的是, 在上述的主备倒换控制电路中还加入了自锁功能电 路(图中没有显示), 该自锁功能电路保证一旦本板升主后, 对板的主 备用状态指示信号将不会影响本板的主用状态, 除非本板由于故障或异 常等原因主动降备, 即对板的任何状态将不会导致本板降备。
如上所述, 图 3所示的主备用倒换控制电路, 实现了 1+1备份系统 的主备用倒换控制, 并且由于增加了信号滤毛刺模块以及应用了时序逻 辑, 可以克服图 2所示的基于 R-S触发器的主备倒换控制电路中由于控 制信号的毛刺带来的主备误倒换现象。
但是, 该方法也会产生如下的问题: 由于在该方案中引入了时序逻 辑,必然导致如图 2所示的两个单板:单板 A和单板 B对于对板的主备 用状态识别的延后。 例如, 若单板 A在 t0时刻主用, 而单板 B只有在 tO+T时刻才能识别单板 A处于主用状态, 其中, T为主备用状态指示信 号经过物理传输和数字处理到达对板,并被对板识别所需的时间。那么, 在 t0到 tO+T的时间内, 虽然单板 A处于主用状态, 但是单板 B却认为 单板 A为备用状态,所以单板 B也可能会升主,又因为单板 A和单板 B 都具有自锁功能, 如果单板 B一旦升主, 就产生了单板 A和单板 B同 时处于主用状态的问题, 即称为双主冲突。 这种双主冲突, 在 1+1备份 系统的设计中是不允许的。 to到 tO+T的时间是可能导致双主的时间, 又称为双主冲突域。
因此, 图 3所示的改进的主备用倒换控制电路虽然克服了图 2所示 的主备用倒换控制电路的主备误倒换问题, 但是同时带来了双主冲突的 问题, 这也是 1+1备份系统所不能允许的。 发明内容
有鉴于此, 本发明的目的就是提供一种主备倒换控制电路, 解决现 有技术中可能出现的双主冲突的问题。
本发明公开了一种主备倒换控制电路, 包含进行主备用倒换控制的 主备用处理模块以及进行升主预约控制的升主预约处理模块。
其中, 所述升主预约处理模块接收对板的升主预约指示信号, 对对 板的升主预约指示信号进行判断, 如果对板的升主预约指示信号无效, 则控制本板升主预约, 并输出本板的升主预约指示信号到主备用处理模 块以及对板的主备倒换控制电路;
所述主备用处理模块接收由升主预约处理模块输出的本板的升主预 约指示信号, 如果本板升主预约指示信号在预定时间内保持有效, 则控 制本板升主, 并输出本板的主备用状态指示信号。
本发明所述升主预约处理模块进一步接收本板的时钟信号, 并在时 钟信号的有效沿对对板的升主预约指示信号进行判断;
所述主备用处理模块进一步接收本板的时钟信号, 并在本板时钟信 号的有效沿对本板的升主预约指示信号进行判断。
本发明所述升主预约处理模块进一步接收本板的复位信号, 并在本 板复位信号有效时, 设置本板升主预约指示信号无效;
所述主备用处理模块进一步接收本板的复位信号, 并在本板复位信 号有效时, 设置本板升主预约指示信号无效。
本发明所述升主预约处理模块进一步接收本板的时钟信号及本板的 复位信号, 在本板复位信号有效时, 设置本板升主预约指示信号无效, 并在本板时钟信号的有效沿对对板的升主预约指示信号进行判断; 所述主备用处理模块进一步接收本板的时钟信号及本板的复位信 号, 在本板复位信号有效时, 设置本板主备用状态指示信号无效, 并在 本板时钟信号的有效沿对本板的升主预约指示信号进行判断。
本发明所述电路进一步包括一个信号滤毛刺模块, 该模块接收来自 对板的升主预约指示信号, 对来自对板的升主预约指示信号进行滤毛刺 处理, 并将经过滤毛刺处理的对板升主预约指示信号输出到升主预约处 理模块;
所述升主预约处理模块对对板的升主预约指示信号进行判断, 是对 经过滤毛刺处理的对板的升主预约指示信号进行判断。
本发明所述信号滤毛刺模块进一步接收本板的时钟信号及本板的复 位信号, 在本板时钟信号的有效沿且本板复位信号无效时, 对来自对板 的升主预约指示信号进行滤毛刺处理, 并输出经过滤毛刺处理的对板升 主预约指示信号。
本发明所述电路进一步包括一个槽位号检测模块, 该模块接收来自 背板的本板槽位号, 根据本板槽位号确定本板的优先级, 并输出本板优 先级指示信号到主备用处理模块;
所述主备用处理模块进一步根据优先级指示信号调整所述预定时 间。
本发明所述槽位号检测模块进一步接收本板的时钟信号及本板的复 位信号, 在本板时钟信号的有效沿且本板复位信号无效时, 根据本板槽 位号确定本板的优先级, 并输出本板优先级指示信号。
本发明所述升主预约处理模块进一步接收本板主备控制信号, 并在 本板主备控制信号有效时, 设置本板升主预约指示信号无效。
本发明所述主备用处理模块进一步接收本板主备控制信号 , 并在本 板主备控制信号有效时, 设置本板的主备用状态指示信号无效。
本发明所述升主预约处理模块进一步接收主备用处理模块输出的本 板主备用状态指示信号, 并在本板主备用状态指示信号有效时, 设置本 板升主预约指示信号有效。
本发明所述主备倒换控制方法, 包括以下步驟:
a、 在单板准备就绪后, 判断该单板是否可以升主预约, 如果是, 该 单板升主预约, 然后执行步骤 b; 否则, 设置单板为备用状态, 然后结 束本流程;
b、保持备用状态预定时间,并在这段时间内检测对板是否进行了升 主预约, 如果对板升主预约, 则该单板预约失败, 保持备用状态, 然后 结束本流程; 否则, 该单板升主, 然后结束本流程。
本发明所述方法由单板的时钟信号有效沿触发。
所述本板时钟信号的有效沿为:本板时钟信号的上升沿或者下降沿。 步骤 a中, 判断单板是否准备就绪的方法包括:
al、 判断单板是否为复位状态, 如果是, 该单板未准备就绪; 否贝' J , 执行步骤 a2;
a2、 判断该单板是否可以主用, 如果是, 该单板准备就绪; 否则, 该单板未准备就绪。
步骤 al所述的判断单板是否为复位状态的方法为:检测该单板的复 位信号, 如果复位信号有效, 则本板为复位状态。
步骤 a2所述的判断单板是否可以主用的方法为:检测该单板的主备 控制信号, 如果主备控制信号无效, 则本板可以主用。
预先设定单板的优先级;
所述步骤 c在该单板升主预约后进一步包括:判断该单板的优先级, 如果该单板的优先级为高, 则直接升主, 然后结束本流程; 否则, 执行 步骤 d。
本发明所述单板优先级的设定方法为: 预先根据单板在背板上的槽 位号设定单板的优先级;
所述判断该单板优先级的方法为: 根据该单板在背板上的槽位号确 定该单板优先级。
本发明所述方法在单板升主预约或者升主以后, 输出升主预约指示 信号发送给对板, 指示该单板升主预约;
步骤 a所述的判断该单板是否可以升主预约的方法为: 检测对板发 送至本板的对板升主预约指示信号, 如果该信号指示对板没有升主预 约, 则本板可以升主预约; 如果该信号指示对板已经升主预约, 则本板 不能升主预约。
步骤 b所述的预定时间为 3倍的本板升主预约指示信号经过物理传 输和数字处理到达对板并被对板识别的时间。
步骤 b中,单板升主后对自身主用状态进行自锁,保持该主用状态。 由此可以看出, 本发明所示的主备用倒换控制电路以及方法采用了 升主预约机制, 即单板在升主之前必须先进行升主预约, 而且只有在预 约成功后才可以升主。 这样可以有效的避免现有技术中出现的双主冲突 问题, 增强系统的可靠性。
另外, 本发明还增加了优先级的机制, 即如果本板的优先级较高, 则直接升主, 而不进行预约等待; 而如果本板的优先级较低, 则等待一 定的时间, 如果在这段时间里, 对板没有升主预约, 则预约成功, 该单 板升主; 如果在这段时间里对板进行了升主预约, 则该单板升主预约失 败, 保持备用状态不变。 这样可以防止由于多次仲裁带来的控制复杂度 的增加以及可能出现的状态振荡现象, P条低了控制的复杂度。 附图简要说明
图 1显示了 1+1备份系统两块单板进行主备倒换控制的基本框架; 图 2显示了基于 R-S触发器模型的主备倒换控制电路;
图 3显示了改进的主备倒换控制电路;
图 4为本发明所述的主备倒换控制电路图;
图 5为本发明所述的主备倒换控制电路中输入输出信号的时序图; 图 6为本发明一个优选实施例所述的主备倒换控制方法流程图。 实施本发明的方式
下面结合附图以及具体的实施例对本发明作进一步的详细说明。 为了克服现有技术中主备倒换电路可能出现的双主冲突问题, 本发 明使用了单板升主预约机制, 即单板在升主之前必须先进行升主预约, 而且只有在预约成功后才可以升主。
本发明还在单板上增加了单板升主预约指示信号作为两个单板之间 通信的握手信号, 而本板的主备用状态指示信号不再用于两个单板的握 手通信, 而只是用于本单板内部的控制和状态指示。
需要说明的是, 上述升主预约机制必须保证, 某个单板只有在检测 到对板没有升主预约的情况下, 才可以进行升主预约, 如果检测到对板 已经进行了升主预约, 则不会进行升主预约。
基于这种思想, 本发明公开了一种主备倒换控制电路。 图 4显示了 本发明所述的主备倒换控制电路。
从图 4可以看出, 本发明所述的主^到换控制电路主要包括信号滤 毛刺模块 401、 升主预约处理模块 402、 主备用处理模块 403、 和槽位号 检测模块 404。
其中, 信号滤毛刺模块 401 接收来自对板的升主预约指示信号 TRY-B、本板的时钟信号 CLK以及本板的复位信号,在本板的时钟信号 CLK的有效沿, 例如上升沿或者下降沿且本板复位信号无效时, 即本板 没有复位时, 对来自对板的升主预约指示信号 TRY-B进行滤毛刺处理, 防止由于对板主备用状态指示信号的毛刺带来的主备误倒换, 该模块输 出经过滤毛刺处理的对板的升主预约指示信号 TRY-B,到升主预约处理 模块 402。
升主预约处理模块 402接收信号滤毛刺模块 401输出的对板的升主 预约指示信号 TRY-B,、主备用处理模块 403输出的主备用状态指示信号 ACT-A、 本板的时钟信号 CLK、 本板的复位信号以及本板主备控制信号 CONT; 在本板时钟信号 CLK的上升沿或者下降沿, 先判断本板复位信 号和主备控制信号 CONT, 如果本板复位信号或者主备控制信号 CONT 有效, 即本板复位或者强制本板备用, 则本板不能升主预约; 如果两个 信号均无效, 再判断本板主备用状态指示信号 ACT-A, 如果本板状态指 示信号 ACT-A有效, 即本板已经升主, 则本板一定处于升主预约状态; 否则,对来自对板的升主预约指示信号 TRY-B,进行判断,如果对板的升 主预约指示信号 TRY-B'无效, 即对板没有升主预约,则控制本板升主预 约。该模块输出本板的升主预约指示信号 TRY-A到主备用处理模块 403 以及到对板的主备用倒换控制电路。
槽位号检测模块 404接收来自背板的本板的槽位号指示信号、 本板 的时钟信号 CLK 以及本板的复位信号, 检测本板在背板上的槽位号, 在本板时钟的上升沿或者下降沿且本板的复位信号无效时, 即本板没有 复位时, 根据本板的槽位号确定本板的优先级, 并输出本板的优先级指 示信号到主备用处理模块 403;
主备用处理模块 403接收升主预约处理模块 402输出的本板的升主 预约指示信号 TRY-A、槽位号检测模块 404输出的本板的优先級指示信 号、 本板的时钟信号 CLK、 本板的复位信号以及本板主备控制信号 CONT, 在本板时钟信号 CLK的上升沿或者下降沿, 如果本板升主预约 指示信号 TRY-A在预定时间内保持有效且本板的复位信号无效,即本板 已经升主预约且在预定时间内对板没有升主预约, 则控制本板升主; 同 时, 主备用处理模块 403可以根据本板的优先级指示信号调整上述预定 时间, 保证在本板优先级较高的情况下, 本板可以立即升主, 而不需要 预约等待。 该模块输出本板的主备用状态指示信号到升主预约处理模块 402以及本板的其他模块。
其中,本板的时钟信号 CLK作为输入信号, 实现对四部分电路的时 序控制, 使所述主备用倒换控制电路的逻辑功能由本板时钟的上升沿或 者下降沿触发。 本板的复位信号, 作为控制信号输入到所示的主备倒换 控制电路的四个模块, 指示本板是否处于复位状态, 如果本板复位, 则 主备倒换控制电路将强制本板降备或者保持备用状态。 本板主备控制信 号 CONT的功能与现有技术中本板主备控制信号的作用相同, 即用于指 示本板是否强制为备用状态。
另外, 所述信号滤毛刺模块和现有技术中改进的主备倒换控制电路 的信号滤毛刺模块的实现方法相同。
在图 4所示的主^到换控制电路中引入本板槽位号的目的是引入优 先级的机制, 防止由于多次仲裁带来的控制复杂度的增加以及可能出现 的状态振荡现象。 因此, 该槽位号检测模块用于检测本板槽位号, 确定 本板的优先级, 并将优先级指示信号输出到主备用处理模块 403。
本发明所述的优先級机制为: 优先级高的单板可以优先升主, 无需 预约等待, 即当优先级高的单板升主预约后, 可以立即升主; 而优先級 低的单板, 必须在升主预约后, 等待一定的时间, 如果在这段时间里对 板没有进行升主预约, 则预约成功, 该单板升主; 如果在这段时间里对 板进行了升主预约, 则预约失败, 该单板保持备用状态不变。
在本发明的一个较佳实施例中, 所述确定本板优先级的方法为: 设 置槽位号为奇数的单板优先级较高, 槽位号为偶数的单板优先级较低。 也可以设置槽位号为偶数的单板优先级较高, 槽位号为奇数的单板优先 级较低。 上述优先级的设置方法的前提是要保证两个单板的槽位号不能 同时为奇数, 或者同时为偶数。
本发明所述的主备倒换控制电路并不限于采用所述检测单板槽位号 来确定单板优先级的方法, 即槽位号检测模块仅为本发明所述主备倒换 控制电路的可选项, 本发明也可以使用其他设置单板优先级的方法, 如 预先设置单板优先级。
需要说明的是, 本发明所述的主备倒换控制电路保留了现有技术的 自锁功能(图 4 中没有显示), 该自锁功能保证一旦本板升主后, 对板 的主备用状态指示信号将不会影响本板的主用状态, 除非本板由于故障 或异常等原因主动降备, 即对板的任何状态将不会导致本板降备。
现具体说明本发明所述主备倒换控制电路的原理:
在本板上电或者复位时, 该单板的主备控制信号 CONT或复位信号 有效, 将强制本板为备用状态;
如果本板准备就绪, 即该单板的主备控制信号 CONT及复位信号指 示本板可以升主预约 , 升主预约处理模块 402将检测由信号滤毛刺模块 401输出的对板升主预约指示信号 TRY-B',如果对板没有进行升主预约 , 则该单板进行升主预约,并输出本板升主预约指示信号 TRY-A到主备用 处理模块 403以及对板的主备倒换控制电路;
当主备用处理模块 403检测到本板已经升主预约时, 将检测槽位号 检测模块 404输出的本板的优先级指示信号, 如果本板的优先级较高, 则直接升主, 而不进行预约等待; 如果本板的优先级较低, 则等待一定 的时间, 如果在这段时间里, 对板没有升主预约, 则预约成功, 该单板 升主;如果在这段时间里对板进行了升主预约,则该单板升主预约失败, 保持备用状态不变;
一旦该单板升主, 该单板将一直保持主用状态, 直到本板的主备控 制信号 CONT强制本板降备;
如果处于主用状态的单板工作异常或者发生故障, 可以通过该单板 的主备控制信号 CONT, 将该单板强制降备, 等待故障处理。 而此时处 于备用状态的单板就可以升主, 保证系统业务不会中断。
如上所述, 图 4所示的主备用倒换控制电路可以实现 1+1备份系统 的主备用倒换控制。
需要说明的是, 本发明所述的主备倒换控制电路既可以应用分立器 件实现, 也可以应用如复杂可编程逻辑器件(CPLD )或现场可编程门 阵列 (FPGA )等的可编程逻辑器件实现。
图 5显示了本发明所述的主^到换控制电路的输入、输出信号时序。 图 5所示的信号时序是在时刻 0到时刻 4T的时间区间内测量得到的, 并且假设包含上述主备倒换控制电路的单板 A的优先级高于单板 B的优 先级, 且在这段时间内两个单板都没有复位。 其中, 时间间隔 T为升主 预约指示信号经过物理传输和数字处理到达对板并被对板识别所需的 时间。
现将图中所示各信号说明如下: 号, 低电平表示强制本板为备用状态, 高电平表示本板可以升主;
TRY-A和 TRY-B分别表示单板 A和单板 B上的升主预约指示信号, 低电平表示本板进行升主预约, 高电平表示本板没有升主预约;
ACT-A和 ACT-B分别表示单板 A和单板 B上的主备用状态指示信 号, 低电平表示本板为主用状态, 高电平表示本板为备用状态;
TRY-A,表示单板 A的升主预约指示信号到达单板 B的信号,从图中 可以看出, 该信号和 TRY-A波形相同, 但具有 T时间延时;
TRY-B,表示单板 B的升主预约指示信号到达单板 A的信号,从图中 可以看出, 该信号和 TRY-B波形相同, 但也具有 T时间延时。
如图 5所示, 在 0 ~ T时间区间内, 单板 Α没有升主预约; 单板 B 在上电后准备就绪, 并且检测到单板 A的升主预约指示信号 TRY-A,为 高电平,则在 T时刻升主预约,即置升主预约指示信号 TRY-B为低电平, 由于单板 B的优先级较低,所以单板 B不能直接升主,要等待一段时间, 所以单板 B进入预约等待状态。
在 T ~ 2T时间区间内,单板 B的升主预约指示信号 TRY-B在 2T时 刻到达单板 A, 因此, 单板 A在 2T时刻以前并不知道单板 B已经进行 了升主预约, 所以在 0到 2T时间区间内, 最晚在 2T时刻, 如果单板 A 准备就绪,单板 A就可以进行升主预约,并且由于单板 A具有较高的优 先级, 不需要预约等待, 所以单板 A会在升主预约的同时直接升主。 如 图 5所示, 单板 A在这段时间区间内升主预约并同时升主。
在 2T ~ 3T时间区间内,单板 B在 2T ~ 3T时间区间内检测到单板 A 已经升主, B板升主预约失败, 即单板 A主用, 单板 B备用。
在 3T ~ 4T时间区间内, 单板 Α主用, 单板 B备用。
如果单板 A在 0时刻以前升主(图 5没有显示这种情况),则单板 B 在 T时刻就可以检测到单板 A进行了升主预约而不会进行升主预约操 作。
如果单板 A在 0 ~ T时间区间内升主(图 5没有显示这种情况), 则 单板 B在 T ~ 2T时间区间内可以检测到单板 A进行了升主, 因而将导 致单板 B升主预约失败。 如果单板 A在 0 ~ 2T时间区间内没有升主(图 5没有显示这种情况:), 则在 2Τ时刻以后就可以检测到单板 Β已经进行了升主预约, 因此不会 在 2Τ时刻以后进行升主操作。
因此, 理论上, 如果单板 Β在升主预约后, 保持备用状态 2Τ时间, 而不是直接升主 , 就可以避免由于双方主备用状态识别的延后所产生的 双主冲突问题。但是考虑到单板 Α和单板 B的本板时钟不可能绝对同频 同相, 所以, 在实际的设计中需要增加一个保护时间 t, 即单板 B要在 升主预约以后的 2T+t时间内检测单板 A是否进行升主预约,如果没有, 则升主预约成功, 升主; 如果有, 则升主预约失败, 保持备用状态不变。 在本发明的一个较佳实施例中, 将所述的等待时间设置为 3T。
从图 4所示的主^到换控制电路和图 5所示的主备倒换控制电路的 输入输出信号时序图中可以看出, 由于本发明所述的主备倒换控制电路 引入了升主预约机制, 可以有效的避免现有技术中由于对对板状态识别 的延后所带来的双主冲突问题, 增强系统的可靠性。 同时, 采用优先级 策略, Ρ争低由于多次仲裁带来的控制复杂度同时避免可能出现的状态振 荡现象。
本发明还公开了一种主备倒换控制的方法, 该方法采用预约机制以 及优先级策略解决双主冲突问题。
图 6显示了本发明一个优选实施例的主备倒换控制方法的流程。 在本发明所述优选实施例中需要预先确定单板的优先级, 其中, 确 定单板优先级的方法有很多种, 例如可以由系统预先随机指定或者根据 单板的槽位号来确定等等。
图 6所示的实施例设定单板优先级的方法为: 根据单板在背板上的 槽位号来确定该单板的优先级, 例如, 如果槽位号为奇数, 则优先级为 高; 如果槽位号为偶数, 则优先级为低; 也可以将槽位号为偶数的单板 的优先级设置为高, 而将槽位号为奇数的单板的优先级设置为低。
另外, 本发明所述方法是由本板的时钟信号的上升沿或下降沿触发 的。
从图 6 可以看出本发明所述的主备倒换控制方法主要包含以下步 骤:
在本板上电后, 进入步骤 601;
步骤 601 : 判断本板是否处于复位状态, 如果是, 执行步驟 608; 否 则, 执行步骤 602;
步骤 602: 判断是本板是否可以主用,如果是,执行步骤 603; 否贝 "J , 执行步驟 608;
其中, 判断本板是否可以主用的方法为: 检测本板主备控制信号 CONT, 如果本板主备控制信号 CONT指示本板可以主用, 则本板可以 主用; 如果本板主备控制信号 CONT指示强制本板备用, 则本板不可以 主用;
步骤 603: 判断对板是否已经升主预约, 如果是, 执行步驟 608; 否 则, 执行步骤 604;
在这一步驟中, 由于单板在升主预约后, 将设置其输出的升主预约 信号有效, 因此, 本板通过检测对板的升主预约指示信号就可以判断对 板是否已经进行了升主预约;
步骤 604: 判断本板的优先级, 如果为高, 则执行步驟 607; 否则, 执行步骤 605;
步骤 605: 本板升主预约, 然后执行步骤 606;
步骤 606: 保持备用状态 3T时间, 并检测对板是否已经升主预约, 如果是, 则执行步驟 608; 否则, 执行步骤 607;
步骤 607: 设置本板为主用状态, 然后结束本流程; 在这一步骤中, 单板在升主后, 也将设置其输出到对板的升主预约 信号有效, 即本板升主后, 本板必然也进行升主预约。
步骤 608: 设置本板为备用状态, 然后结束本流程。
上述方法保留了现有技术的自锁功能, 即一旦本板升主, 本板将一 直保持主用状态,直到本板复位或者本板主备控制信号 CONT强制本板 降备。
如果主用单板工作异常或发生故障, 可以通过该单板的主备控制信 号, 强制该单板降备, 而此时处于备用状态的单板就可以升主, 保证系 统业务不会中断。
从图 6所示的方法可以看出, 本发明所述的方法引入了升主预约机 制和优先权策略, 可以有效的避免双主冲突问题。
由此可以看出, 本发明所述的主备倒换控制电路和方法, 保留了现 有技术的时序逻辑和自锁功能, 避免了主备误倒换现象的发生, 并且在 现有技术的基 上增加了升主预约机制和优先级策略, 有效的避免了由 于两个单板对其对板主备用状态识别的时间延后所造成的双主冲突问 题, 由此增强了 1+1备份系统的可靠性。

Claims

权利要求书
1、一种主备倒换控制电路, 包含进行主备用倒换控制的主备用处理 模块(403 ), 其特征在于, 该电路还包括: 进行升主预约控制的升主预 约处理模块(402 );
其中,所述升主预约处理模块( 402 )接收对板的升主预约指示信号, 对对板的升主预约指示信号进行判断, 如果对板的升主预约指示信号无 效, 则控制本板升主预约, 并输出本板的升主预约指示信号到主备用处 理模块(403 ) 以及对板的主备倒换控制电路;
所述主备用处理模块 ( 403 )接收由升主预约处理模块( 402 )输出 的本板的升主预约指示信号, 如果本板升主预约指示信号在预定时间内 保持有效, 则控制本板升主, 并输出本板的主备用状态指示信号。
2、如权利要求 1所述的主备倒换控制电路, 其特征在于, 所述升主 预约处理模块(402 )进一步接收本板的时钟信号, 并在时钟信号的有 效沿对对板的升主预约指示信号进行判断;
所述主备用处理模块 ( 403 )进一步接收本板的时钟信号 , 并在本板 时钟信号的有效沿对本板的升主预约指示信号进行判断。
3、如权利要求 1所述的主备倒换控制电路, 其特征在于, 所述升主 预约处理模块(402 )进一步接收本板的复位信号, 并在本板复位信号 有效时, 设置本板升主预约指示信号无效;
所述主备用处理模块 ( 403 )进一步接收本板的复位信号, 并在本板 复位信号有效时, 设置本板主备用状态指示信号无效。
4、如权利要求 1所述的主备倒换控制电路, 其特征在于, 所述升主 预约处理模块(402 )进一步接收本板的时钟信号及本板的复位信号, 在本板复位信号有效时, 设置本板升主预约指示信号无效, 并在本板时 钟信号的有效沿对对板的升主预约指示信号进行判断;
所述主备; ¾处理模块 ( 403 )进一步接收本板的时钟信号及本板的复 位信号, 在本板复位信号有效时, 设置本板主备用状态指示信号无效, 并在本板时钟信号的有效沿对本板的升主预约指示信号进行判断。
5、如权利要求 1至 4所述的主备倒换控制电路, 其特征在于, 所述 电路进一步包括一个信号滤毛刺模块( 401 ), 该模块接收来自对板的升 主预约指示信号, 对来自对板的升主预约指示信号进行滤毛刺处理, 并 将经过滤毛刺处理的对板升主预约指示信号输出到升主预约处理模块
( 402 );
所述升主预约处理模块( 402 )对对板的升主预约指示信号进行判断, 是对经过滤毛刺处理的对板的升主预约指示信号进行判断。
6、如权利要求 5所述的主备倒换控制电路, 其特征在于, 所述信号 滤毛刺模块(401 )进一步接收本板的时钟信号及本板的复位信号, 在 本板时钟信号的有效沿且本板复位信号无效时, 对来自对板的升主预约 指示信号进行滤毛刺处理, 并输出经过滤毛刺处理的对板升主预约指示 信号。
7、如权利要求 1至 4所述的主备倒换控制电路, 其特征在于, 所述 电路进一步包括一个槽位号检测模块 ( 404 ), 该模块接收来自背板的本 板槽位号, 根据本板槽位号确定本板的优先级, 并输出本板优先级指示 信号到主备用处理模块( 403 );
所述主备用处理模块( 403 )进一步根据优先级指示信号调整所述预 定时间。
8、如权利要求 7所述的主备倒换控制电路, 其特征在于, 所述槽位 号检测模块(404 )进一步接收本板的时钟信号及本板的复位信号, 在 本板时钟信号的有效沿且本板复位信号无效时, 根据本板槽位号确定本 板的优先级, 并输出本板优先级指示信号。
9、 如权利要求 1至 4所述的主备倒换控制电路, 其特征在于: 所述 升主预约处理模块(402 )进一步接收本板主备控制信号, 并在本板主 备控制信号有效时, 设置本板升主预约指示信号无效。
10、 如权利要求 1至 4所述的主备倒换控制电路, 其特征在于: 所 述主备用处理模块(403 )进一步接收本板主备控制信号, 并在本板主 备控制信号有效时, 设置本板的主备用状态指示信号无效。
11、 如权利要求 1至 4所述的主备倒换控制电路, 其特征在于: 所 述升主预约处理模块(402 )进一步接收主备用处理模块(403 )输出的 本板主备用状态指示信号, 并在本板主备用状态指示信号有效时, 设置 本板升主预约指示信号有效。
12、 一种主备倒换控制方法, 其特征在于, 该方法包括以下步骤: a、 在单板准备就绪后, 判断该单板是否可以升主预约, 如果是, 该 单板升主预约, 然后执行步驟 b; 否则, 设置单板为备用状态, 然后结 束本流程;
b、保持备用状态预定时间,并在这段时间内检测对板是否进行了升 主预约, 如果对板升主预约, 则该单板预约失败, 保持备用状态, 然后 结束本流程; 否则, 该单板升主, 然后结束本流程。
13、 如权利要求 12所述的主备倒换控制方法, 其特征在于, 所述方 法由单板的时钟信号有效沿触发。
14、如权利要求 13所述的主备倒换控制方法, 其特征在于, 所述本 板时钟信号的有效沿为: 本板时钟信号的上升沿或者下降沿。
15、 如权利要求 12所述的主备倒换控制方法, 其特征在于, 步驟 a 中, 判断单板是否准备就绪的方法包括:
al、 判断单板是否为复位状态, 如果是, 该单板未准备就绪; 否贝1 J , 执行步驟 a2;
a2、 判断该单板是否可以主用, 如果是, 该单板准备就绪; 否则, 该单板未准备就绪。
16、 如权利要求 15 所述的主备倒换控制方法, 其特征在于, 步骤 al所述的判断单板是否为复位状态的方法为: 检测该单板的复位信号, 如果复位倌号有效, 则本板为复位状态。
17、 如权利要求 15 所述的主备倒换控制方法, 其特征在于, 步骤 a2 所述的判断单板是否可以主用的方法为: 检测该单板的主备控制信 号, 如果主备控制信号无效, 则本板可以主用。
18、如权利要求 12所述的主备倒换控制方法, 其特征在于, 预先设 定单板的优先级;
所述步骤 a在该单板升主预约后进一步包括:判断该单板的优先级, 如果该单板的优先级为高, 则直接升主, 然后结束本流程; 否则, 执行 步骤 b。
19、如权利要求 18所述的主备倒换控制方法, 其特征在于, 所述单 板优先级的设定方法为: 预先根据单板在背板上的槽位号设定单板的优 先级;
所述判断该单板优先级的方法为: 根据该单板在背板上的槽位号确 定该单板优先级。
20、如权利要求 12所述的主备倒换控制方法, 其特征在于, 所述方 法在单板升主预约或者升主以后, 输出升主预约指示信号发送给对板, 指示该单板升主预约;
步骤 a所述的判断该单板是否可以升主预约的方法为: 检测对板发 送至本板的对板升主预约指示信号, 如果该信号指示对板没有升主预 约, 则本板可以升主预约; 如果该信号指示对板已经升主预约, 则本板 不能升主预约。
21、 如权利要求 20所述的主备倒换控制方法, 其特征在于, 步骤 b 所述的预定时间为 3倍的本板升主预约指示信号经过物理传输和数字处 理到达对板并被对板识别的时间。
22、 如权利要求 12所述的主备倒换控制方法, 其特征在于, 步驟 b 中, 单板升主后对自身主用状态进行自锁, 保持该主用状态。
PCT/CN2005/001067 2004-07-23 2005-07-18 Circuit et procede de commande de basculement entre modes active et veille WO2006007785A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN200410070886.3 2004-07-23
CNB2004100708863A CN100370701C (zh) 2004-07-23 2004-07-23 一种主备倒换控制电路及其控制方法

Publications (1)

Publication Number Publication Date
WO2006007785A1 true WO2006007785A1 (fr) 2006-01-26

Family

ID=35784873

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2005/001067 WO2006007785A1 (fr) 2004-07-23 2005-07-18 Circuit et procede de commande de basculement entre modes active et veille

Country Status (2)

Country Link
CN (1) CN100370701C (zh)
WO (1) WO2006007785A1 (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103513593A (zh) * 2013-10-08 2014-01-15 潍柴动力股份有限公司 在双控制器场景中实现控制的方法和装置
WO2017124577A1 (zh) * 2016-01-20 2017-07-27 邦彦技术股份有限公司 基于fpga的主备板卡在位自动检测及切换的系统及方法
CN109920370A (zh) * 2019-04-17 2019-06-21 东莞阿尔泰显示技术有限公司 一种新型led显示屏系统备份电路及其控制方法
CN112751753A (zh) * 2019-10-31 2021-05-04 中兴通讯股份有限公司 一种保护单板主备状态的方法和通信设备

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102769522A (zh) * 2012-08-07 2012-11-07 北京东土科技股份有限公司 一种框式设备主备倒换方法及系统
CN109164787A (zh) * 2018-08-31 2019-01-08 杭州和利时自动化有限公司 一种模拟量信号采集装置
CN112486882B (zh) * 2020-12-15 2023-05-26 安徽皖通邮电股份有限公司 一种背板上单板信号的复用装置的复用方法
CN113312089B (zh) * 2021-07-06 2023-06-16 浙江亿邦通信科技有限公司 低成本高效率的盘间通信物理通道倒换控制系统及方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1245999A (zh) * 1998-08-25 2000-03-01 深圳市华为技术有限公司 主备份倒换装置
CN1405985A (zh) * 2001-08-21 2003-03-26 华为技术有限公司 主备倒换控制电路及实现方法
CN1463081A (zh) * 2002-05-30 2003-12-24 华为技术有限公司 通信设备中实现主备设备快速倒换的方法
KR20040056394A (ko) * 2002-12-23 2004-07-01 엘지전자 주식회사 다중 무선 가입자 카드 사이의 인터페이스 제어 장치

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10303870A (ja) * 1997-04-28 1998-11-13 Fujitsu Ltd 系切り替え回路
US6209051B1 (en) * 1998-05-14 2001-03-27 Motorola, Inc. Method for switching between multiple system hosts
CN1109416C (zh) * 2000-04-25 2003-05-21 华为技术有限公司 交换机的主备倒换方法及其实现装置
CN1128558C (zh) * 2000-10-01 2003-11-19 深圳市中兴通讯股份有限公司 基站控制维护模块备份系统
CN100341255C (zh) * 2002-12-26 2007-10-03 华为技术有限公司 一种交叉主备保护的热备份方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1245999A (zh) * 1998-08-25 2000-03-01 深圳市华为技术有限公司 主备份倒换装置
CN1405985A (zh) * 2001-08-21 2003-03-26 华为技术有限公司 主备倒换控制电路及实现方法
CN1463081A (zh) * 2002-05-30 2003-12-24 华为技术有限公司 通信设备中实现主备设备快速倒换的方法
KR20040056394A (ko) * 2002-12-23 2004-07-01 엘지전자 주식회사 다중 무선 가입자 카드 사이의 인터페이스 제어 장치

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103513593A (zh) * 2013-10-08 2014-01-15 潍柴动力股份有限公司 在双控制器场景中实现控制的方法和装置
CN103513593B (zh) * 2013-10-08 2016-01-13 潍柴动力股份有限公司 在双控制器场景中实现控制的方法和装置
WO2017124577A1 (zh) * 2016-01-20 2017-07-27 邦彦技术股份有限公司 基于fpga的主备板卡在位自动检测及切换的系统及方法
CN109920370A (zh) * 2019-04-17 2019-06-21 东莞阿尔泰显示技术有限公司 一种新型led显示屏系统备份电路及其控制方法
CN112751753A (zh) * 2019-10-31 2021-05-04 中兴通讯股份有限公司 一种保护单板主备状态的方法和通信设备

Also Published As

Publication number Publication date
CN100370701C (zh) 2008-02-20
CN1725660A (zh) 2006-01-25

Similar Documents

Publication Publication Date Title
WO2006007785A1 (fr) Circuit et procede de commande de basculement entre modes active et veille
US8867680B2 (en) Circuitry system and method for connecting synchronous clock domains of the circuitry system
US8081643B2 (en) Relay connection unit
WO2010012236A1 (zh) 一种实现管脚分时复用的方法及片上系统
CN101488844A (zh) 一种板间通信链路切换控制的方法和系统
JP2003046596A (ja) ネットワークインターフェース
TW201727505A (zh) 偵測輸入/輸出裝置連接的方法及週邊輸入/輸出裝置與其主計算裝置
CN114365103A (zh) 菊花链模式进入序列
CN101291201A (zh) 心跳信息传输系统及方法
CN113625540B (zh) 双机热备控制方法、装置及双机热备系统
US20240241569A1 (en) Method for adaptively adjusting state transition time in peripheral component interconnect express system to enhance overall performance, and associated apparatus
US7912989B2 (en) Network interface for decreasing power consumption
JP2015154189A (ja) 通信システム、ゲートウェイ装置及び通信ノード並びに通信制御方法
JP5195075B2 (ja) 双方向バス制御回路
TW200408937A (en) Circuit for detection of internal microprocessor watchdog device execution and method for resetting microprocessor system
US9465766B1 (en) Isolation interface for master-slave communication protocols
CN112799991B (zh) Pcie交换芯片
JP2016058944A (ja) ノード
US8185678B1 (en) Method and apparatus for controlling a data bus
JP3266841B2 (ja) 通信制御装置
JP2015033863A (ja) 車両用電子制御装置
CN110690998B (zh) 一种基于bmc的主从设备管理方法
JP2007026033A (ja) 半導体装置及び半導体装置の動作モード自動判定方法
CN118331026A (zh) 一种双机冗余通讯方法及系统
JPS5895457A (ja) 二重系切替制御装置

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NG NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU LV MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase