WO2006000180A3 - Bondfolie und halbleiterbauteil mit bondfolie sowie verfahren zu deren herstellung - Google Patents

Bondfolie und halbleiterbauteil mit bondfolie sowie verfahren zu deren herstellung Download PDF

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Publication number
WO2006000180A3
WO2006000180A3 PCT/DE2005/001031 DE2005001031W WO2006000180A3 WO 2006000180 A3 WO2006000180 A3 WO 2006000180A3 DE 2005001031 W DE2005001031 W DE 2005001031W WO 2006000180 A3 WO2006000180 A3 WO 2006000180A3
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WIPO (PCT)
Prior art keywords
bonding film
faces
semiconductor chip
bonding
semiconductor component
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PCT/DE2005/001031
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English (en)
French (fr)
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WO2006000180A2 (de
Inventor
Michael Bauer
Thomas Engling
Alfred Haimerl
Angela Kessler
Joachim Mahler
Wolfgang Schober
Original Assignee
Infineon Technologies Ag
Michael Bauer
Thomas Engling
Alfred Haimerl
Angela Kessler
Joachim Mahler
Wolfgang Schober
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Application filed by Infineon Technologies Ag, Michael Bauer, Thomas Engling, Alfred Haimerl, Angela Kessler, Joachim Mahler, Wolfgang Schober filed Critical Infineon Technologies Ag
Publication of WO2006000180A2 publication Critical patent/WO2006000180A2/de
Publication of WO2006000180A3 publication Critical patent/WO2006000180A3/de

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    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

Die Erfindung betrifft eine Bondfolie (1, 21) und ein Halbleiterbauteil (20) mit Bondfolie (1, 21), sowie ein Verfahren zu deren Herstellung. Dabei dient die Bondfolie (1, 21) zum Kontaktieren von Halbleiterchips (2), wobei die Bondfolie (1, 21) in ihrer flächigen Erstreckung größer als der Halbleiterchip (2) ist. Im Randbereich (17), der außerhalb des Halbleiterchips (2) angeordnet ist, weist die Bondfolie (1, 21) Randanschlussflächen (10) auf, die über Verdrahtungsleitungen (8, 9) mit Kontaktanschlussflächen (5) in Verbindung stehen. Diese Kontaktanschlussflächen (5) entsprechen in Anordnung und Größe einer Anordnung und Größe von Kontaktflächen (6) des Halbleiterchips (2) und stehen mit diesen stoffschlüssig in Verbindung. Ein Halbleiterbauteil (20) weist zwei Bondfolien (1, 21) auf, wobei eine obere Bondfolie (1) die Oberseiten (16) und Randseiten des Halbleiterchips (2) bedeckt und eine untere Bondfolie (21) die Rückseite (15) des Halbleiterchips (2) kontaktiert und abdeckt.
PCT/DE2005/001031 2004-06-23 2005-06-09 Bondfolie und halbleiterbauteil mit bondfolie sowie verfahren zu deren herstellung WO2006000180A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004030383.5 2004-06-23
DE200410030383 DE102004030383A1 (de) 2004-06-23 2004-06-23 Bondfolie und Halbleiterbauteil mit Bondfolie sowie Verfahren zu deren Herstellung

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WO2006000180A2 WO2006000180A2 (de) 2006-01-05
WO2006000180A3 true WO2006000180A3 (de) 2006-04-27

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WO (1) WO2006000180A2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007043001A1 (de) * 2007-09-10 2009-03-12 Siemens Ag Bandverfahren für elektronische Bauelemente, Module und LED-Anwendungen
DE102007054710B3 (de) * 2007-11-16 2009-07-09 Semikron Elektronik Gmbh & Co. Kg Verfahren zur Herstellung einer Halbleiterbaugruppe
US8110912B2 (en) * 2008-07-31 2012-02-07 Infineon Technologies Ag Semiconductor device
DE102013107862A1 (de) * 2013-07-23 2015-01-29 Osram Opto Semiconductors Gmbh Oberflächenmontierbares optoelektronisches Halbleiterbauteil und Verfahren zur Herstellung zumindest eines oberflächenmontierbaren optoelektronischen Halbleiterbauteils
DE102013114107A1 (de) * 2013-12-16 2015-07-02 Osram Opto Semiconductors Gmbh Optoelektronisches Halbleiterbauelement
US11901309B2 (en) * 2019-11-12 2024-02-13 Semiconductor Components Industries, Llc Semiconductor device package assemblies with direct leadframe attachment

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EP0452506A1 (de) * 1989-11-06 1991-10-23 Nippon Mektron, Ltd. Verfahren zur herstellung einer biegsamen schaltungsplatte zum montieren von integrierten schaltungen
EP0482940A1 (de) * 1990-10-24 1992-04-29 Nec Corporation Verfahren zur Herstellung einer elektrischen Verbindung für eine integrierte Schaltung
EP0522593A1 (de) * 1991-07-12 1993-01-13 Rohm Co., Ltd. Verfahren zur Befestigung elektronischer Teile und Leiterplatten und Leiterplatten mit darauf befestigten elektronischen Teilen
US5394303A (en) * 1992-09-11 1995-02-28 Kabushiki Kaisha Toshiba Semiconductor device
DE19542883A1 (de) * 1995-02-02 1996-08-08 Fraunhofer Ges Forschung Chip-Gehäusung sowie Verfahren zur Herstellung einer Chip-Gehäusung
US5605547A (en) * 1995-03-27 1997-02-25 Micron Technology, Inc. Method and apparatus for mounting a component to a substrate using an anisotropic adhesive, a compressive cover film, and a conveyor
EP1220310A1 (de) * 1999-09-10 2002-07-03 Nitto Denko Corporation Halbleiterscheibe mit anisotropem leitfilm und seine herstellungsmethode
US6445063B1 (en) * 1998-03-09 2002-09-03 Micron Technology, Inc. Method of forming a stack of packaged memory die and resulting apparatus
DE10200268A1 (de) * 2001-05-02 2002-11-28 Mitsubishi Electric Corp Halbleitervorrichtung
US20030012005A1 (en) * 2000-12-19 2003-01-16 Yoshinori Ito Electronic circuit device

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3793714A (en) * 1971-05-27 1974-02-26 Texas Instruments Inc Integrated circuit assembly using etched metal patterns of flexible insulating film
US3868724A (en) * 1973-11-21 1975-02-25 Fairchild Camera Instr Co Multi-layer connecting structures for packaging semiconductor devices mounted on a flexible carrier
US4215359A (en) * 1977-12-13 1980-07-29 U.S. Philips Corporation Semiconductor device
EP0338232A2 (de) * 1988-04-20 1989-10-25 International Business Machines Corporation Verfahren zum Montieren eines Trägers für eine elektronische Anordnung mit biegsamem Film auf ein oder zum Trennen desselben von einem Substrat
EP0452506A1 (de) * 1989-11-06 1991-10-23 Nippon Mektron, Ltd. Verfahren zur herstellung einer biegsamen schaltungsplatte zum montieren von integrierten schaltungen
EP0482940A1 (de) * 1990-10-24 1992-04-29 Nec Corporation Verfahren zur Herstellung einer elektrischen Verbindung für eine integrierte Schaltung
EP0522593A1 (de) * 1991-07-12 1993-01-13 Rohm Co., Ltd. Verfahren zur Befestigung elektronischer Teile und Leiterplatten und Leiterplatten mit darauf befestigten elektronischen Teilen
US5394303A (en) * 1992-09-11 1995-02-28 Kabushiki Kaisha Toshiba Semiconductor device
DE19542883A1 (de) * 1995-02-02 1996-08-08 Fraunhofer Ges Forschung Chip-Gehäusung sowie Verfahren zur Herstellung einer Chip-Gehäusung
US5605547A (en) * 1995-03-27 1997-02-25 Micron Technology, Inc. Method and apparatus for mounting a component to a substrate using an anisotropic adhesive, a compressive cover film, and a conveyor
US6445063B1 (en) * 1998-03-09 2002-09-03 Micron Technology, Inc. Method of forming a stack of packaged memory die and resulting apparatus
EP1220310A1 (de) * 1999-09-10 2002-07-03 Nitto Denko Corporation Halbleiterscheibe mit anisotropem leitfilm und seine herstellungsmethode
US20030012005A1 (en) * 2000-12-19 2003-01-16 Yoshinori Ito Electronic circuit device
DE10200268A1 (de) * 2001-05-02 2002-11-28 Mitsubishi Electric Corp Halbleitervorrichtung

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