WO2005125019A1 - ターボ符号の誤り訂正復号方法及びターボ符号の誤り訂正復号装置 - Google Patents
ターボ符号の誤り訂正復号方法及びターボ符号の誤り訂正復号装置 Download PDFInfo
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- WO2005125019A1 WO2005125019A1 PCT/JP2004/008524 JP2004008524W WO2005125019A1 WO 2005125019 A1 WO2005125019 A1 WO 2005125019A1 JP 2004008524 W JP2004008524 W JP 2004008524W WO 2005125019 A1 WO2005125019 A1 WO 2005125019A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
Definitions
- TECHNICAL FIELD An error correction decoding method for a turbo code and an error correction decoding device for a turbo code.
- the present invention relates to an error correction code used in the field of communications, and more particularly to a turbo code error correction decoding method and a turbo code error correction decoding device.
- a reception sequence is decoded using a maximum a posteriori algorithm. Learning by backward processing is performed, and thereafter, the first result value by backward processing is calculated and stored, and at the same time as the learning time, the second result value by forward processing is calculated.
- the decoding output is determined using the two result values and the first result value stored before the first result value.
- the block length W of the first stage is changed according to the code length N which is the length of the reception sequence.
- the present invention has been made to solve the above problems, and an error correction decoding method for a turbo code and a turbo code error correction decoding method capable of easily determining a start position of calculation of a backward path metric. It is an object to obtain an error correction decoding device.
- the error correction decoding method for a turbo code uses an information bit system 1J, a detection bit system 1J1 corresponding to an encoder without interleaving, and an interleave from a received sequence of a turbo code of code length N.
- Into a check bit sequence 2 corresponding to a coded encoder divide each separated sequence into multiple blocks, and calculate the backward path metric and the forward path metric for each of the divided blocks.
- each separated sequence is selected for each M symbols from the beginning, and one block is constructed and divided into K blocks.
- the block length of this block has a configuration of M symbols
- the block length of the last block K has a configuration of (N_M (K-1)) symbols.
- FIG. 1 is a block diagram showing a configuration of a turbo code error correction decoding apparatus according to Embodiment 1 of the present invention.
- FIG. 2 is a diagram illustrating a method of dividing a reception sequence in an error correction decoding device for turbo codes according to Embodiment 1 of the present invention.
- FIG. 3 is a flowchart showing a turbo code decoding procedure of the turbo code error correction decoding device according to Embodiment 1 of the present invention.
- FIG. 4 is a diagram for explaining the timing of path metric calculation in turbo decoding of the error correction decoding device for turbo codes according to Embodiment 1 of the present invention.
- FIG. 5 is a flowchart showing a soft input / soft output decoding procedure corresponding to an encoder without interleaving in the turbo code error correction decoding apparatus according to Embodiment 1 of the present invention.
- FIG. 6 An interleaver in a turbo code error correction decoding apparatus according to Embodiment 1 of the present invention. 6 is a flowchart showing a soft-input soft-output decoding procedure corresponding to an encoder having a loop.
- FIG. 7 is a flowchart showing a turbo code decoding procedure of the turbo code error correction decoding device according to Embodiment 2 of the present invention.
- FIG. 8 is a diagram for explaining the timing of the path metric calculation in turbo decoding in the turbo code error correction decoding apparatus according to Embodiment 3 of the present invention.
- FIG. 9 is a diagram showing addresses of a backward path metric storage unit that stores a backward path metric calculated by a backward path metric calculation unit in a turbo code error correction decoding apparatus according to Embodiment 5 of the present invention. .
- FIG. 10 is a diagram showing addresses of a backward path metric storage unit that stores a backward path metric calculated by a backward path metric calculation unit in a turbo code error correction decoding apparatus according to Embodiment 5 of the present invention. is there.
- FIG. 11 is a diagram showing an address of a backward path metric storage unit that stores a backward path metric calculated by a backward path metric calculation unit in the error correction decoding apparatus for turbo codes according to Embodiment 5 of the present invention. is there.
- FIG. 12 is a block diagram showing a configuration of a turbo code error correction decoding device according to Embodiment 6 of the present invention.
- FIG. 1 is a block diagram showing a configuration of a turbo code error correction decoding apparatus according to Embodiment 1 of the present invention.
- the error correction decoding device for turbo codes includes a reception data storage unit.
- Received data storage means 1 stores the information bit sequence, check bit sequence 1 and check bit sequence 2 separated from received sequence 101, and external information storage means 2 calculates LLR calculation means 8 The stored external information sequence is stored.
- the backward branch metric calculation means 3 calculates the backward branch metric
- the backward path metric calculation means 4 calculates the backward path metric
- the backward path metric storage means 5 calculates the calculated backward direction. Is stored.
- Forward branch metric calculation means 6 calculates a forward branch metric
- forward path metric calculation means 7 calculates a forward path metric
- LLR calculation means 8 calculates a forward branch metric calculation means 6. Based on the calculated forward branch metric, the forward path metric calculated by the forward path metric calculation means 7 and the backward path metric stored in the backward path metric storage means 5, In order to perform decoding, the external information sequence is calculated and updated, and a hard-decision decoding sequence is generated and output as a decoding result 102.
- a reception sequence 101 from a demodulator (not shown) installed in a stage preceding the error correction decoding device for turbo codes corresponds to an information bit sequence and a test corresponding to the encoding data from the encoding side. It is separated into three sequences, a bit sequence 1 and a check bit sequence 2, and stored in the received data storage means 1.
- check bit sequence 1 is a check bit sequence corresponding to an encoder without interleaving
- check bit sequence 2 is a check bit sequence corresponding to an encoder with interleaving.
- ⁇ > is a function that rounds up the decimal point if it is not divisible.
- the detection bit sequence 1 and the detection bit system IJ2 are read.
- one block is formed by selecting every M symbols from the beginning, divided into K blocks, and blocks from block l [Block # l] to block (K_l) [Block # (Kl)]
- the length is composed of M symbols
- the block of the last block K [Block # K] is The lock length is made up of the remaining (N_M (K-1)) symbols.
- the external information sequence stored in the external information storage means 2 is not shown in FIG. 2, similar to the information bit system “system! J”, the check bit sequence 1 and the check bit sequence 2, Select one block for each M symbol, divide it into K blocks, and start from block 1 [Block # 1] to block (K-1) [Block # (K-1)]
- the block length of is set to M symbols, and the block length of the last block K [Block # K] is set to the remaining (N-M (K-1)) symbolonore.
- a soft input / soft output process is performed on each of the divided blocks as described below, and a soft input / soft output calculation method is performed using a logMAP algorithm or a MaxlogMAP algorithm.
- FIG. 3 is a flowchart showing a decoding procedure of the turbo code.
- the external information sequence is calculated and updated in order to perform the next decoding by the soft-input soft-output decoding procedure corresponding to the encoder without interleaving on the decoding side.
- step ST 13 the updated external information sequence is rearranged in the interleaving order and stored in external information storage means 2.
- step ST14 the information bit sequence read out in the interleaving order stored in the reception data storage means 1, the check bit sequence 2 stored in the reception data storage means 1, and the external information storage means 2 Reverse branch metric calculation means 3, reverse path metric calculation means 4, reverse path metric storage means 5, forward branch metric calculation means 6 based on the stored external information sequence in the updated interleave order.
- the external information sequence is calculated and updated, and a hard-decision decoded sequence is generated by the soft-input / soft-output decoding procedure corresponding to the encoder having the loop.
- step ST 15 the external information sequence updated in step ST 14 is deinterleaved, rearranged in the order of the received bit sequence, and stored in external information storage means 2.
- step ST16 it is checked whether the number of decoding iterations j has reached a predetermined number of decoding iterations P. If not, the number of decoding iterations j is updated in step ST17. The above steps ST12 and ST15 are repeated.
- step ST 18 the hard decision decoding sequence in the last decoding is output as the decoding result 102.
- FIG. 4 is a diagram illustrating the timing of path metric calculation in turbo decoding.
- external information sequence from block 1 [Block # 1] to block K [Block # K] by LLR calculation means 8 The timing of the calculation and the output of the decoding result 102 are shown.
- the L symbol 201 added before the block l [Block # 1] is the first L symbol in the M symbol of the subsequent block 2 [Block # 2].
- the first L symbol in the next M symbol in block 2 is calculated in order to calculate the initial value of the path metric in the backward direction. This indicates that learning of the backward path metric calculation is performed using the number of margin symbols. In other words, this shows that the reverse path metric of block 1 is calculated from the L symbol eye weight of block 2.
- the L symbolons 202, 203, 208, and 209 attached to the front of each block are the first L symbols in the M symbols of the subsequent blocks, respectively, and Before performing the backward path metric calculation for M symbols, the M symbols for each subsequent block This indicates that the learning of the path metric calculation in the reverse direction is performed using the first L symbols in as the number of margin symbols. However, for the last block K [Block # K], there is no subsequent block, and therefore learning using the L symbol 209 is not actually performed.
- the backward path metric calculation means 4 also calculates the backward path metric of block 1 and the L symbol eye weight of block 2 and calculates the calculated backward path metric.
- the metric is stored in the backward path metric storage means 5.
- the backward path metric calculation means 4 calculates the backward path metric of block 2 from the L-th symbol of block 3 and stores it in the backward path metric storage means 5, and at the same time, the forward path metric calculation means 7
- the forward path metric of block 1 is calculated, and then the LLR calculating means 8 calculates an external information sequence for the backward path metric and the forward path metric of block 1 and stores the calculated external information sequence in the external information. Store in means 2.
- the backward path metric calculation means 4 calculates the backward path metric of the block K and stores it in the backward path metric storage means 5, and at the same time, the forward path metric calculation means 7 calculates the forward path metric of the block (K 1), and then calculates the extrinsic information series for the backward path metric and the forward path metric of the block (K 1). Is stored in the external information storage means 2. Finally, the forward path metric calculation means 7 calculates the forward path metric of the block K, and then the LLR calculation means 8 outputs the external information sequence for the backward path metric and the forward path metric of the block K. Is calculated, and the calculated external information sequence is stored in the external information storage means 2.
- FIG. 5 is a flowchart showing a soft input / soft output decoding procedure corresponding to an encoder without interleaving in step ST12 of FIG.
- step ST21 the information bit sequence stored in the reception data storage means 1 is divided into K blocks in the order of reception and read out, and the detection bit sequence 1 stored in the reception data storage means 1 is read out. Is read out after being divided into K blocks, and each of the external information sequences stored in the external information storage means 2 (the value of the external information sequence is assumed to be 0 during the first decoding) is K And read out.
- step ST22 after the backward branch metric calculation means 3 calculates the backward branch metric, the backward path metric calculation means 4 outputs the backward path metric of the block l [Block # 1] to block 2.
- the L ( ⁇ M) symbol visual power of [Block # 2] is calculated, and the backward path metric of block 1 among the calculated backward path metrics is stored in the backward path metric storage means 5.
- step ST24 it is determined whether or not the block number variable i is the last block K. If it is not block K, the process proceeds to step ST25.
- the backward path metric calculation means 4 calculates the backward path metric of the block 2 [Block # 2] from the L (L M) symbolonole of the block 3 [Block # 3] and calculates the same.
- the backward path metric of the block 2 among the backward path metrics is stored in the backward path metric storage means 5.
- the forward path metric calculation means 7 calculates the forward path metric of the block 1.
- the LLR calculation means 8 calculates the backward path metric of the block 1 stored in the backward path metric storage means 5 and the forward branch of the block 1 calculated by the forward branch metric calculation means 6. Based on the metric and the forward path metric of block 1 calculated by the forward path metric calculation means 7, the external information sequence of block 1 is calculated, and the external information sequence is stored in the external information storage means 2 and hardened. Calculate the judgment value.
- step ST26 the variable i of the block number is updated, and the processing of steps ST24 and ST25 is repeated.
- the backward path metric calculation of the block (i + 1) [Block # (i + 1)] is performed.
- the block i [Block #i] are simultaneously subjected to the forward path metric calculation using the updated external information sequence, and the LLR calculation means 8 calculates the block stored in the backward path metric storage means 5
- the backward path metric of i, the forward branch metric of the block i calculated by the forward branch metric calculation means 6, and the forward path metric of the block i calculated by the forward path metric calculation means 7 The external information sequence of the block i is calculated and updated and stored in the external information storage means 2, and the hard decision value is calculated.
- the forward path metric calculation means 7 uses the updated external information sequence to Compute the direction path metric.
- the LLR calculation means 8 calculates the backward path metric of the block ⁇ stored in the backward path metric storage means 5, the forward branch metric of the block ⁇ calculated by the forward branch metric calculation means 6, Based on the forward path metric of the block ⁇ ⁇ ⁇ calculated by the forward path metric calculation means 7, the external information sequence of the block ⁇ is calculated and updated and stored in the external information storage means 2 and the hard decision value is calculated.
- FIG. 6 is a flowchart showing a soft-input soft-output decoding procedure corresponding to an interleaved encoder in step ST14 of FIG.
- step ST31 the information bit sequence stored in the reception data storage means 1 is divided into ⁇ ⁇ ⁇ ⁇ blocks in an interleaving order and read out, and the check bit sequence 2 stored in the reception data storage means 1 is read out.
- External information sequence read out after being divided into blocks and rearranged in the interleaving order stored in the external information storage means 2 (however, the value of the external information sequence is 0 at the first decoding) ) Are divided into ⁇ ⁇ ⁇ ⁇ blocks and read out.
- step ST32 after the backward branch metric calculation means 3 calculates the backward branch metric, the backward path metric calculation means 4 outputs the backward path metric of the block l [Block # 1] to block 2.
- the L ( ⁇ M) symbol visual power of [Block # 2] is calculated, and the backward path metric of block 1 among the calculated backward path metrics is stored in the backward path metric storage means 5.
- step ST34 it is confirmed whether or not the block number variable i is the last block K. If it is not block K, the process proceeds to step ST35.
- the backward path metric calculation means 4 calculates the backward path metric of the block 2 [Block # 2] from the L ( ⁇ M) symbolonore of the block 3 [Block # 3] and calculates the same.
- the backward path metric of the block 2 among the backward path metrics is stored in the backward path metric storage means 5.
- the forward branch metric calculation means 6 calculates the forward branch metric of the block 1, and then the forward path metric calculation means 7 Computes the forward path metric for block 1.
- the LLR calculation means 8 calculates the backward path metric of the block 1 stored in the backward path metric storage means 5 and the forward branch metric of the block 1 calculated by the forward branch metric calculation means 6.
- the external information sequence of block 1 is calculated and stored in the external information storage means 2 by the forward path metric of block 1 calculated by the forward branch metric calculation means 6 and the hard decision value. I do.
- step ST36 the variable i of the block number is updated, and the processing in steps ST34 and ST35 is repeated. Similarly, the path metric calculation in the opposite direction of the block (i + 1) [Block # (i + 1)] is performed.
- the block i [Block #i] are simultaneously subjected to the forward path metric calculation using the updated external information sequence, and the LLR calculation means 8 calculates the block stored in the backward path metric storage means 5
- the backward path metric of i, the forward branch metric of block i calculated by the forward branch metric calculation means 6, and the forward path metric of block i calculated by the forward path metric calculation means 7 The external information sequence of the block i is calculated and updated and stored in the external information storage means 2, and the hard decision value is calculated.
- the forward path metric calculation means 7 uses the updated external information sequence to Compute the path metric for the direction.
- the LLR calculation means 8 calculates the backward path metric of the block K stored in the backward path metric storage means 5, the forward branch metric of the block K calculated by the forward branch metric calculation means 6, Based on the forward path metric of block K calculated by the forward path metric calculation means 7, the external information sequence of block K is calculated and the hard decision value is calculated.
- the information bit system M ′, the detection bit sequence 1, the detection bit sequence 2, and the external information sequence have M symbol lengths from the head of N symbols.
- Each block is composed and divided into K blocks.
- Each block is divided into 1 block (K-1), and the symbol is M.
- the last block, K, and the remaining ( The N-M (K-1)) symbol starts the calculation of the path metric in the reverse direction regardless of the code length N when performing the soft-input soft-output processing on each of the divided blocks. Easy to locate The effect that can be obtained is obtained.
- the block diagram showing the configuration of the error correction decoding apparatus for turbo codes according to the second embodiment of the present invention is the same as FIG. 1 of the first embodiment. Also, the method of dividing the receiving sequence of the second embodiment is the same as that of FIG. 2 of the first embodiment, and the timing of the path metric calculation of the second embodiment is the same as that of FIG. 4 of the first embodiment. Is the same as In the first embodiment, the LLR calculation means 8 outputs the hard-decision decoding sequence as a decoding result 102 in the order of interleaving of the information bit sequence, but in the second embodiment, the LLR calculation means 8 The hard decision decoding sequence is output as a decoding result 102 in the order of the bit sequence, that is, in the order of the head of the information bit sequence.
- FIG. 7 is a flowchart showing a turbo code decoding procedure of the turbo code error correction decoding apparatus according to Embodiment 2 of the present invention.
- the flowchart shown in FIG. 7 is basically the same as that in the first embodiment described above except that the processing of steps ST12 and ST13 and the processing of steps ST14 and ST15 in FIG. 3 are replaced.
- step ST42 in FIG. 7 is basically the same as the processing in step ST14 in FIG. 3, and the hard-decision decoding sequence generation processing performed in step ST14 in FIG. Step ST42 in FIG. 7 must not be performed.
- the processing in step ST43 in FIG. 7 is the same as the processing in step ST15 in FIG. 3, and the processing in step ST44 in FIG. 7 is basically the same as the processing in step ST12 in FIG.
- the process of generating a hard-decision decoded sequence not performed in step ST12 of FIG. 3 is performed in step ST44 of FIG.
- the processing in step ST45 in FIG. 7 is the same as the processing in step ST13 in FIG. 3, and the processing in the other steps ST41, ST46, ST47, and ST48 in FIG. , ST16, ST17, ST18.
- the external information sequence is updated by combining the information bit system 1J in the interleaving order, the detection bit sequence 2, and the external information sequence in the interleaving order. Dint-leaving the information sequence and rearranging it in the received bit sequence order, combining the information bit system in the received bit sequence order, the detection bit sequence 1, and the external information sequence Calculate the part information sequence.
- the LLR calculation means 8 outputs a hard decision decoding sequence as a decoding result 102 in the order of the reception bit sequence of the information bit sequence, that is, in the order of the head of the information bit sequence.
- a hard-decision decoding sequence is used as a decoding result 102 in the interleaving order of the information bit sequence. Since it is output, it is necessary to store the decoding result 102 in a memory (not shown) and rearrange it in the order of the received bit sequence, and then perform the CRC operation.
- the hard-decision decoding sequence By outputting the hard-decision decoding sequence as the decoding result 102, it is possible to perform error detection operation processing such as CRC, which does not need to be stored in a memory or rearranged, at high speed.
- the external information sequence is updated by combining the information bit system U in the interleaving order, the detection bit sequence 2, and the external information sequence in the interleaving order. Then, the updated external information sequence is subjected to dint-leaving and rearranged in the order of the received bit sequence, and the information bit system I in the received bit sequence order, the check bit sequence 1, and the external information system IJ are combined.
- the decoding result 102 is output in the order of the head of the information bit sequence, and the effect that the error detection operation such as CRC can be performed at high speed can be obtained.
- the block diagram showing the configuration of the error correction decoding apparatus for turbo codes according to the third embodiment of the present invention is the same as FIG. 1 of the first embodiment. Further, the method of dividing the reception sequence according to the third embodiment is the same as that in FIG. 2 of the first embodiment.
- the reverse direction is used. The calculation of the path metric is performed using tilbits.
- the flowchart showing the decoding procedure of the turbo code according to the third embodiment is the same as the processing shown in FIG. 3 of the first embodiment, and the soft input corresponding to the encoder without interleaving according to the third embodiment.
- the flowchart showing the soft-output decoding procedure and the flowchart showing the soft-input soft-output decoding procedure corresponding to the interleaved encoder are the same as those in FIGS. 5 and 6 of the first embodiment, respectively.
- FIG. 8 is a diagram for explaining the timing of the path metric calculation in turbo decoding according to the third embodiment. Compared with FIG. 4 in the first embodiment, the path metric calculation in the reverse direction is performed.
- the L symbol 208 added before the block (K-1) becomes the Lx symbol 218, and the L symbol 209 added before the block K becomes the tail bit (Tail) 219.
- the L symbol 208 added before the block (K-1) becomes the Lx symbol 218, and the L symbol 209 added before the block K becomes the tail bit (Tail) 219.
- Tail tail bit
- the backward path metric calculation means 4 calculates the backward path metric, the number of margin symbols L for learning, which serves as a margin, L Is a predetermined fixed value, and when performing a backward path metric calculation, the block length of the final block K (NM (K ⁇ 1)) The symbol is short, and the symbol 208 of the block (K1) in FIG. 4 does not have a predetermined fixed value, and the path metric calculation of the block (K1) is performed in the reverse direction.
- the backward path metric calculation means 4 calculates the backward path metric
- the value of the code length N and the number L of margin symbols are used as shown in FIG.
- the value of the number of margin symbols L is roughly changed to a predetermined fixed value which is determined in advance.
- For block K take the large value of state 0 as the initial value of the backward path metric, calculate the path metric of the tilt bit, and then calculate the path metric of the block K in the reverse direction.
- Information can be used effectively, and the backward path metric can be calculated quickly and efficiently, and the learning period for the backward path metric calculation of block (K-1) and block K can be secured, and the entire decoding operation can be performed. In this case, the performance can be improved.
- the third embodiment similarly to the first embodiment, it is possible to easily determine the starting position of the calculation of the path metric in the backward direction regardless of the code length N. The effect is obtained.
- the backward path metric is calculated by using the tilt bit, whereby the tilt is calculated.
- the bit information can be effectively used, the backward path metric can be calculated quickly and efficiently, and the performance can be improved even in the entire decoding operation.
- the same effect can be obtained by performing decoding in the decoding procedure of the second embodiment.
- the block diagram showing the configuration of the turbo code error correction decoding apparatus according to the fourth embodiment of the present invention is the same as FIG. 1 of the first embodiment.
- the method of dividing the receiving sequence, the flowchart showing the turbo code decoding procedure, the timing of the path metric calculation, the soft input soft output decoding procedure corresponding to the encoder without interleave, and the interleave The soft-input / soft-output decoding procedure corresponding to the coder not provided is the same as that of FIG. 2, FIG. 3, FIG. 4, FIG. 5, and FIG.
- the forward path metric of the last block of the block is temporarily saved in a memory (not shown) or the like, and is used as an initial value when calculating the forward path metric of the next (i + 1) -th block.
- the forward path metric at the end of block 1 in the forward path metric calculation in Fig. 4 is temporarily saved in memory and used as the initial value when calculating the forward path metric of the next block 2. .
- the forward path metric at the end of the i-th block is temporarily saved in memory, and is used as an initial value when calculating the forward path metric of the next (i + 1) -th block.
- the accuracy of the forward path metric is improved, and the performance can be improved in the entire decoding operation.
- the forward path metric calculation means 7 calculates the forward path metric
- the forward path metric at the end of each block is temporarily saved.
- the accuracy of the forward path metric is improved, and the performance can be improved even in the entire decoding operation. Is obtained.
- Embodiment 4 similar effects can be obtained by performing decoding in the decoding procedure of Embodiment 2 described above.
- the block diagram showing the configuration of the error correction decoding apparatus for turbo codes according to the fifth embodiment of the present invention is the same as FIG. 1 of the first embodiment.
- the reception sequence division method, the flowchart showing the decoding procedure of the turbo code, the timing of the path metric calculation, the soft input soft output decoding procedure corresponding to the encoder without interleaving, and the interleaving The soft-input / soft-output decoding procedure corresponding to the coder not provided is the same as that of FIG. 2, FIG. 3, FIG. 4, FIG. 5, and FIG.
- the reverse path metric storage means 5 needs a memory capacity of a total of 2 M words of M words in the write area and M words in the read area.
- FIG. 9 is a diagram showing addresses of the backward path metric storage means 5 for storing the backward path metrics calculated by the backward path metric calculation means 4 in FIG.
- FIG. 9 (a) shows a write address when writing a path metric in the reverse direction of block 1 [Block # 1].
- FIG. 9 (b) shows the read address and block i [Blo ck when reading the path metric in the reverse direction of block (i-1) [B lock # (i_l)] when the variable i of the block number is even.
- # i] indicates the write address when writing the path metric in the reverse direction.
- FIG. 9 (a) shows a write address when writing a path metric in the reverse direction of block 1 [Block # 1].
- FIG. 9 (b) shows the read address and block i [Blo ck when reading the path metric in the reverse direction of block (i-1) [B lock # (i_l)] when the variable i of the block number is even.
- # i]
- FIG. 10 is a diagram showing addresses of the backward path metric storage means 5 for storing the backward path metrics calculated by the backward path metric calculation means 4 in FIG.
- FIG. 10 (a) shows the read address and block K [Block # K when reading the path metric in the reverse direction of block (K-1) [Block # (K-1)] when the final block number K is even. ] Indicates the write address when writing the path metric in the reverse direction of [].
- FIG. 10 (b) shows the read address when reading the path metric in the reverse direction of the block K [Block #K] when the final block number K is an even number.
- FIG. 11 is a diagram showing addresses of the backward path metric storage means 5 for storing the backward path metrics calculated by the backward path metric calculation means 4 in FIG.
- FIG. 11 (a) shows the read address and block K [Block # K when reading the path metric in the reverse direction of the block (K-1) [Block # (K-1)] when the final block number K is an odd number. ] Indicates the write address when writing the path metric in the reverse direction of [].
- Fig. 11 (b) It indicates the read address when reading the path metric in the reverse direction of the block K [Block # K] when the final block number K is an odd number.
- the backward path metric calculation means 4 calculates the backward path metric of the block 1, as shown in FIG. 9 (a), the backward path metric of the block 1 is calculated in the backward direction. Write in ascending order from address 0 to address (M_l) of the path metric storage means 5.
- the backward path metric calculation means 4 performs the backward path metric calculation of the block 2 (i is an even number) and the forward path metric calculation means 7 simultaneously performs the forward path metric calculation of the block 1
- the LLR calculation means 8 descends the path metric of the block 1 in the backward direction to the address (M-1) force of the backward path metric storage means 5 to address 0.
- the backward path metric calculation means 4 writes the backward path metric of the block 2 into the backward path metric storage means 5, but the LLR calculation means 8 reads the backward path metric value of the block 1.
- the address (M-1) of the backward path metric storage means 5 is written in descending order to address 0.
- the timing difference between the reading of the backward path metric of block 1 and the writing of the backward path metric of block 2 at this time is the learning period of the backward path metric calculation of block 2.
- the LLR calculation means 8 reads the backward path metrics of the block 2 from the address 0 to the address (M-1) of the backward path metric storage means 5 in ascending order. .
- the backward path metric calculation means 4 writes the backward path metric of the block 3 into the backward path metric storage means 5 .
- the LLR calculation means 8 reads the backward path metric of the block 2 The data is written in ascending order from the address 0 of the direction path metric storage means 5 to the address (M-1). The timing difference between the reading of the backward path metric of block 2 and the writing of the backward path metric of block 3 at this time is the learning period for the backward path metric calculation of block 3.
- the path in the reverse direction depends on the even or odd block number of the block to be processed.
- Write Metric By replacing the address of the backward path metric storage means 5 at the time of writing with the address in descending or ascending order, the memory capacity of the backward path metric storage means 5 can be suppressed to M words.
- an address of the backward path metric storage means 5 is generated as shown in FIGS. 10 and 11 according to the even or odd number of the final block number K.
- the LLR calculating means 8 stores the backward path metric of the block (K ⁇ 1) in the backward path metric storing means 5. From address (M-1) to address 0 in descending order. At this time, at the same time, the backward path metric calculation means 4 causes the backward path metric storage means 5 to store the backward path metric of the block K in the backward path metric storage means 5. The LLR calculation means 8 outputs the backward path metric of the block (K-1). After reading, write from address (M_l) to address (MK-N) in descending order.
- the timing difference between the reading of the backward path metric of the block (K 1) and the writing of the backward path metric of the block K is the learning period of the backward path metric calculation of the block K.
- the forward path metric calculation means 7 calculates the forward path metric of the block K, as shown in FIG. 10 (b)
- the LLR calculation means 8 calculates the backward path metric of the block K.
- the data is read out from the address (MK-N) to the address (M-1) in the backward path metric storage means 5 in ascending order.
- the LLR calculating means 8 stores the backward path metric of the block (K 1) in the backward path metric storing means 5 as shown in FIG. Read from address 0 to address (M-1) in ascending order.
- the backward path metric calculation means 4 causes the backward path metric storage means 5 to store the backward path metric of the block K in the backward path metric storage means 5.
- the LLR calculation means 8 outputs the backward path metric of the block (K-1). After reading, write from address 0 to address (N-M (K_1) -1) in ascending order.
- the forward path metric calculation means 7 calculates the forward When performing the path metric calculation, as shown in FIG.
- the path metric in the reverse direction of K is stored in the address of the reverse path metric storage means 5 (N ⁇ M (K—1)
- the addresses shown in FIG. 9, FIG. 10, and FIG. 11 are generated by address generation means (not shown) connected to the backward path metric storage means 5 in FIG. it can.
- the fifth embodiment similarly to the first embodiment, it is possible to easily determine the start position of the calculation of the path metric in the backward direction regardless of the code length N. The effect is obtained.
- the address of the backward path metric storage means 5 at the time of writing the backward path metric is written in descending order or according to the even or odd block number of the block to be processed.
- the memory capacity of the backward path metric storage means 5 can be reduced to M words, and the memory capacity of the backward path metric storage means 5 can be reduced.
- FIG. 12 is a block diagram showing a configuration of a turbo code error correction decoding apparatus according to Embodiment 6 of the present invention.
- This error correction decoding apparatus for turbo codes has a configuration shown in FIG. 1 of the first embodiment, in which a reverse read address generation means 31, a forward read address generation means 32, a reverse read address generation means 33, The read address generating means 34, the external information write address generating means 35, the switching means 36, the switching means 37, the write address generating means 38, the read address generating means 39 and the control means 40 are added.
- reception data storage unit 1 includes an information bit sequence storage unit 11, a check bit sequence 1 storage unit 12, and a check bit sequence 2 storage unit 13, and the external information storage unit 2 includes a reception bit sequence.
- a bit sequence order external information storage means 21 and an interleave order external information storage means 22 are provided.
- the information bit sequence storage means 11 stores the information bit sequence separated from the received sequence 101 (not shown), and the check bit sequence 1 storage means 12 stores the test bit sequence separated from the received sequence 101.
- the bit sequence 1 is stored, and the check bit sequence 2 storage means 13 stores the test bit sequence 2 separated from the received sequence 101.
- the external information storage unit 21 stores the external information sequence from the LLR calculation unit 8 in the order of the received bit sequence, and the external information storage unit 22 stores the external information sequence from the LLR calculation unit 8 in the interleave order. .
- the reverse read address generation means 31 stores the read addresses of the information bit sequence storage means 11, the received bit sequence order external information storage means 21 and the interleave order external information storage means 22 for calculating the backward path metric.
- the forward read address generation means 32 generates the read address of the information bit sequence storage means 11 for calculating the path metric in the forward direction, the reception bit sequence order external information storage means 21 and the interleave order external information storage means 22. Generate.
- the reverse read address generation means 33 generates a read address of the verification bit system for calculating the path metric in the reverse direction 12 and the test bit sequence 2 storage means 13, and generates the forward read address.
- the generating means 34 generates a read address of the check bit sequence 1 storage means 12 and the check bit sequence 2 storage means 13 for calculating the forward path metric.
- the external information write address generating means 35 generates a write address for writing the external information sequence from the LLR calculating means 8 into the external information storage means 21 in the received bit sequence and the external information storage means 22 in the interleaved order.
- the switching means 36 selects the output of the test bit sequence 1 storage means 12 or the test bit sequence 2 storage means 13 output, and the switching means 37 is the reception bit sequence order external information storage means 21 or the interleave order external information storage means. Select the output from 22.
- the write address generation means 38 generates a write address for writing the backward path metric in the reverse path metric storage means 5, and the read address generation means 39 is stored in the reverse path metric storage means 5. Generate a read address to read the reverse path metric.
- the control means 40 previously calculates and holds the code length N, the number of blocks K, the block length ⁇ , and the number of margin bits L, and gives each held value to each means, and Generates control signals for processing.
- a method for dividing a reception sequence according to the sixth embodiment a flowchart showing a turbo code decoding procedure, a timing of path metric calculation, a soft input / soft output decoding procedure corresponding to an encoder without interleaving, and an encoder with interleaving.
- the soft-input / soft-output decoding procedure to be performed is basically the same as that of FIG. 2, FIG. 3, FIG. 4, FIG. 5, and FIG. Details of generation of read address and write address of storage means 11, inspection bit sequence 1 storage means 12, test bit sequence 2 storage means 13, received bit sequence order external information storage means 21, and interleaving order external information storage means 22 Will be described.
- the received sequence 101 demodulated by a demodulator (not shown) is separated into an information bit sequence, a check bit sequence 1 and a check bit sequence 2 as soft-decision information.
- the test bit sequence 1 is stored in the storage means 12 and the test bit sequence 2 storage means 13.
- the addresses of the reverse direction read address generation means 31 and the reverse direction read address generation means 33 are set to (M + L-1).
- This address (M + L-1) is the head address of the L symbol 201 in the backward path metric calculation in FIG.
- the information bit sequence, the test bit sequence 1 and the external information sequence are read out from the information bit sequence storage unit 11, the check bit system storage unit 12 and the received bit sequence order external information storage unit 21, respectively.
- the external information sequence read from the external information storage means 21 in the order of the received bit sequence is 0.
- the values read from the inspection bit system 1U storage unit 12 and the received bit sequence order external information storage unit 21 are selected by the switching unit 36 and the switching unit 37 and input to the backward branch metric calculation unit 3.
- the backward branch metric calculation means 3 calculates the backward branch metric
- the backward path metric calculation means 4 calculates the backward path metric.
- the value of the backward read address generator 31 and the value of the backward read address generator 33 are counted down, and the address becomes 0 (the last address of block 1 in the backward path metric calculation in Fig. 4). The same operation is repeated until the backward path metric calculation means 4 calculates the backward path metric.
- the backward path metric storage means 5 stores the backward path metric value of the backward read address generating means 31 and the backward read address generating means 33 whose address is from M to 1 in the backward direction.
- the write address generation means 38 generates the write address of the backward path metric storage means 5 by, for example, the procedure described in the fifth embodiment.
- This address (iM + L_l) is the first address of the L symphony 202, 203,..., 208, 209 in the nosmetric calculation in the reverse direction of FIG.
- the information bit system, the test bit sequence 1, and the external information sequence are read from the information bit sequence storage unit 11, the check bit sequence 1 storage unit 12, and the received bit sequence order external information storage unit 21, respectively.
- the external information sequence read from the external information storage means 21 in the order of the received bit sequence is 0.
- the addresses of the forward read address generation means 32 and the forward read address generation means 34 are set to (M (i-2)).
- This address (M (i-2)) is the head address of block 1 block K in the forward path metric calculation in FIG.
- the information bit sequence, the check bit sequence 1 and the external information sequence are read out from the information bit sequence storage unit 11, the check bit sequence 1 storage unit 12, and the received bit sequence in-order information storage unit 21, respectively.
- the external information sequence to be read is set to 0 in the order of the received bit sequence external information storage means.
- the values read from the check bit system Ijl storage means 12 and the reception bit sequence order external information storage means 21 by the addresses of the reverse read address generation means 31 and the reverse read address generation means 33 are: It is selected by the switching means 36 and the switching means 37 and input to the backward branch metric calculation means 3.
- Reverse branch metric calculation means 3 is reverse The branch metric in the direction is calculated, and the backward path metric calculation means 4 calculates the backward path metric.
- the address of the forward read address generating means 32 and the forward read address generating means 34 is used to check the check bit system system Ijl storage means 12 and the received bit sequence forward external information storage means 21. Are selected by the switching means 36 and the switching means 37 and input to the forward branch metric calculation means 6.
- the forward branch metric calculation means 6 calculates a forward branch metric
- the forward path metric calculation means 7 calculates a forward path metric.
- the LLR calculation means 8 includes the forward branch metric calculated by the forward branch metric calculation means 6, the forward path metric calculated by the forward path metric calculation means 7, and the fifth embodiment.
- the external information sequence is calculated from the backward path metric read from the backward path metric storage means 5 using the address of the read address generation means 39 generated in the procedure described in the above.
- the address of the external information write address generation means 35 is set to (M (i-2)). This address (M (i-2)) is the start address of block 1 block K in the external information calculation shown in FIG. Then, the external information sequence calculated by the LLR calculation means 8 is written to the external information storage means 22 in the interleaving order.
- the addresses of the backward read address generating means 31 and the backward read address generating means 33 are counted down to ((M_l) i).
- This address ((M_l) i) is the last address of block 2-block K in the backward path metric calculation in FIG.
- the addresses of the forward read address generating means 32 and the forward read address generating means 34 are counted up to (M (i-1) _1).
- This address (M (i-l) -l) is the last address of block 1 to block K in the forward path metric calculation in FIG.
- the address of the external information write address generation means 35 is counted up to (M (i_l) _l), and the external information sequence is sequentially calculated and written into the interleaved external information storage means 22.
- This address (M (i_l) _l) is the last address of one block per block in the external information calculation in FIG.
- the addresses of the forward read address generator 32 and the forward read address generator 34 are set to (M (K-1)).
- This address (M (K-1)) Is the start address of block K in the forward path metric calculation in FIG.
- the address of the external information write address generating means 35 is set to ( ⁇ ( ⁇ —1)).
- This address (M (K-1)) is the first address of block ⁇ ⁇ ⁇ ⁇ in the external information calculation in FIG.
- the information bit sequence, the check bit sequence 1 and the external information sequence are read out from the information bit sequence storage unit 11, the check bit sequence 1 storage unit 12, and the received bit sequence order external information storage unit 21, respectively.
- the external information sequence read from the external information storage means 21 in the order of the received bit sequence is 0.
- the values read from the check bit system Ijl storage means 12 and the reception bit sequence forward external information storage means 21 by the addresses of the forward read address generation means 32 and the forward read address generation means 34 are as follows. It is selected by the switching means 36 and the switching means 37 and input to the forward branch metric calculation means 6.
- the forward branch metric calculation means 6 calculates a forward branch metric
- the forward path metric calculation means 7 calculates a forward path metric.
- the LLR calculation means 8 includes the forward branch metric calculated by the forward branch metric calculation means 6, the forward path metric calculated by the forward path metric calculation means 7, and the fifth embodiment.
- the external information sequence is calculated from the backward path metric read from the backward path metric storage means 5 based on the address of the read address generation means 39 generated in the procedure described in the above, and the external information write address generation means 35 Write to the address of the external information storage means 22 in the specified interleaving order.
- the addresses of the forward read address generator 32 and the forward read address generator 34 are counted up to (N ⁇ 1).
- This address (N-1) is the last address of block K in the forward path metric calculation in FIG.
- the address of the external information write address generation means 35 is counted up to (N-1).
- This address (N-1) is the last address of block K in the external information calculation in FIG.
- the address of the backward read address generation means 31 is set to the (M + L-1) th address in a turbo interleave table (not shown), and the information bit sequence storage means 11 and the The information bit sequence and the external information sequence are read from the slave order external information storage means 22. Further, the address of the backward read address generation means 33 is set to (M + L-1), and the inspection bit sequence 2 is read from the inspection bit system IJ2 storage means 13. The values read from the check bit sequence 2 storage means 13 and the interleaved-order external information storage means 22 are selected by the switching means 36 and the switching means 37 and input to the backward branch metric calculation means 3. The backward branch metric calculating means 3 calculates the backward branch metric, and the backward path metric calculating means 4 calculates the backward path metric.
- the address of the backward read address generator 31 is sequentially set to the previous address in the turbo interleave table, and the address of the backward read address generator 33 is counted down until the address becomes 0.
- the backward path metric calculation means 4 calculates the backward path metric, and the backward path metric storage means 5 stores the backward path metric whose address of the backward read address generating means 33 is up to 1 in the reverse direction. To memorize.
- the write address generation means 38 also generates the address 0 for the write address (M-1) force of the backward path metric storage means 5 by the procedure described in the fifth embodiment, for example.
- the addresses of the reverse read address generation means 31 and the reverse read address generation means 33 are used to read from the check bit sequence 2 storage means 13 and the interleave order external information storage means 22.
- the output value is selected by the switching means 36 and the switching means 37 and input to the backward branch metric calculation means 3.
- the backward branch metric calculation means 3 calculates a backward branch metric
- the backward path metric calculation means 4 calculates a backward path metric.
- the values read from the check bit sequence 2 storage means 13 and the interleaved-order external information storage means 22 at the addresses of the forward read address generation means 32 and the forward read address generation means 34 are switched by the switching means. It is selected in 36 and switching means 37 and input to the forward branch metric calculation means 6.
- the forward branch metric calculation means 6 calculates a forward branch metric
- the forward path metric calculation means 7 calculates a forward path metric.
- the LLR calculation means 8 includes the forward branch metric calculated by the forward branch metric calculation means 6, the forward path metric calculated by the forward path metric calculation means 7, and the fifth embodiment.
- the external information sequence is calculated from the backward path metric read from the backward path metric storage means 5 using the address of the read address generation means 39 generated in the procedure described in the above.
- the address of the external information write address generation means 35 is set to the (M (i-2)) th address in a turbo interleave table (not shown), and the external information sequence is written to the external information storage means 21 in the order of the received bit sequence.
- the address of the backward read address generating means 31 is sequentially set to the previous address in the turbo interleave table, and the address of the backward read address generating means 33 is counted down to ((M-l) i). .
- the address of the forward read address generation means 32 is sequentially set to the next address in the one-pointer leave table, and the address of the forward address generation means 34 is counted up to (M (i_l) _l).
- the address of the external information write address generating means 35 is sequentially set to the next address in the turbo interleave table, and the external information sequence is sequentially calculated and written to the external information storage means 21 in the order of the received bit sequence.
- the address of the forward read address generator 32 is set to the (M (K-1)) th address in the turbo interleave table, and the address of the forward read address generator 34 is set to ( M (K-1)).
- information bit sequence storage means 1 Read the information bit sequence, test bit sequence 2 and external information sequence from the check bit sequence 2 storage means 13 and the interleaved order external information storage means 22, respectively.
- the values read from the check bit sequence 2 storage means 13 and the interleaved-order external information storage means 22 are changed by the switching means 36 and the switching means. It is selected in the means 37 and input to the forward branch metric calculation means 6.
- the forward branch metric calculation means 6 calculates a forward branch metric
- the forward path metric calculation means 7 calculates a forward path metric.
- the LLR calculation means 8 includes the forward branch metric calculated by the forward branch metric calculation means 6, the forward path metric calculated by the forward path metric calculation means 7, and the fifth embodiment.
- the external information sequence is calculated from the backward path metric read from the backward path metric storage means 5 based on the address of the read address generation means 39 generated in the procedure described in the above, and designated by the external information write address generation means 35. Write to the address of the external information storage means 22 in the order of the interleave.
- the address of the forward read address generating means 32 is sequentially set to the next address in the turbo interleave table, and the address of the forward read address generating means 34 is counted up to (N-1).
- the address of the external information write address generation means 35 is sequentially set to the next address in the single pointer leave table.
- the above processing is repeated a predetermined number of times, and the hard decision decoding sequence finally output by the LLR calculation means 8 is output as the decoding result 102.
- the generation means 35 is a read address for the information bit sequence storage means 11, the detection bit sequence 1 storage means 12, the check bit sequence 2 storage means 13, the reception bit sequence order external information storage means 21, and the interleaving order external information storage means 22. Pula By generating the unit address as described above, the information bit sequence can be configured with a common storage means without storing interleaved and non-interleaved sequences in separate storage means, and the storage capacity can be reduced. The effect is obtained.
- the error correction decoding method for turbo codes according to the present invention is suitable for easily determining the start position of the calculation of the backward path metric regardless of the code length N.
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JP2009105772A (ja) * | 2007-10-24 | 2009-05-14 | Panasonic Corp | 反復復号装置及び反復復号方法 |
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JP2001267936A (ja) * | 2000-02-10 | 2001-09-28 | Motorola Inc | 畳込み符号用のソフト判定出力デコーダ |
JP2001267937A (ja) * | 2000-02-10 | 2001-09-28 | Motorola Inc | 畳込み符号用のソフト出力デコーダ |
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JP2001267936A (ja) * | 2000-02-10 | 2001-09-28 | Motorola Inc | 畳込み符号用のソフト判定出力デコーダ |
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