WO2005122695A2 - A system for mapping defective printed circuits - Google Patents

A system for mapping defective printed circuits Download PDF

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Publication number
WO2005122695A2
WO2005122695A2 PCT/IL2005/000650 IL2005000650W WO2005122695A2 WO 2005122695 A2 WO2005122695 A2 WO 2005122695A2 IL 2005000650 W IL2005000650 W IL 2005000650W WO 2005122695 A2 WO2005122695 A2 WO 2005122695A2
Authority
WO
WIPO (PCT)
Prior art keywords
scrap
pcb
layer
units
layers
Prior art date
Application number
PCT/IL2005/000650
Other languages
French (fr)
Other versions
WO2005122695A3 (en
Inventor
Nir Dery
Original Assignee
Camtek Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Camtek Ltd. filed Critical Camtek Ltd.
Priority to JP2007517648A priority Critical patent/JP4923180B2/en
Priority to CN2005800248665A priority patent/CN101297305B/en
Publication of WO2005122695A2 publication Critical patent/WO2005122695A2/en
Publication of WO2005122695A3 publication Critical patent/WO2005122695A3/en

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/161—Using chemical substances, e.g. colored or fluorescent, for facilitating optical or visual inspection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/163—Monitoring a manufacturing process

Definitions

  • mapping PCBs relates to a system and method for mapping PCBs.
  • PCBs are usually made in a way of manufacturing a single board that
  • PCBs large number of units [PCBs] can be produced on a single board and any number of them could be defective and known as "scrap-units".
  • a single defect in one of the unit's layer is enough in order to disqualify the - unit. Since the processes are done on a board scale (not on a unit scale], it is very important to identify in process the scrap-units and therefore prevent any work and material investment on a scrap-unit.
  • the present invention can be use either the PCB is produced using
  • the present invention makes use, in a preferred embodiment, in "a
  • the present invention is a scrap-units-mapping system and method, especially for mapping a multi-layers board that contains a plurality of PCBs.
  • scrap-units-mapping system that includes:
  • a scrap-units- mapping system that further includes: d) an optimization software that matches plurality of layer maps of each terrace-layer of the PCB and define sets of identified layers to join into a PCB with minimum scrap-units, enabling to collect each of defined sets to join into a PCB. e) a mechanism that collects, according to the optimization results, sets of the identified layers to join into PCBs
  • scrap- units-mapping system wherein the method for storing layers' information is the method that is defined in the international publication WO 03/081535 A1.
  • a method for scrap-units-mapping especially for mapping a multi-layers board that contains a plurality of PCBs, including the following steps: a] scanning by an optical inspection system each layer - both sides - of identified layers that are intended to create a specific PCB and marking the scrap-units on a layer map;
  • each color defines the defective layer.
  • the present invention successfully addresses the shortcomings of
  • Figure 1 illustrates a flow chart of a preferred embodiment of the
  • FIG. 2 illustrates the mapping method, according to the present
  • the present invention is a scrap-units-mapping system and method, especially for mapping a multi-layers board that contains a plurality of PCBs.
  • the system uses scanned images of the layers of a specific PCB. On each layer there are scrap-
  • the scanned image is a map of
  • the system combines these maps to create a map that illustrates
  • this map can be used for
  • Figure 1 illustrates a flow chart of a preferred embodiment of the present invention, using "lamination” method of production.
  • Three layers groups "A" 17, L1 , L2 and L3 are input to be scanned in the scan unit 18.
  • the images pass to the mapping unit ISthat create maps for each layer.
  • the optimize unit and software 21 decided - in order to have a PCB with
  • the first layer of L2 to be the second layer and the second
  • the optimize unit 21 collect
  • Figure 2 illustrates the mapping method, according to the present invention, using an example of two-sided and three layers board with twenty-five PCBs.
  • Each of the three layers of the board is scanned, having images of side 1 and side 2 of each layer L1 , L2 and L3.
  • the scrap-units 7/ are marked (in the illustration by "D").
  • the system combines the images into a map 12, which marks the location of the scrap-units with colors that identify the defect's layer location, the defects of L1 13, the defects of
  • layer L2 the defects of layer L3 75and multi-layers defects 16.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

A scrap-units-mapping system is disclosed. The system is especially designed for mapping a multi-layers PCB that contains a plurality of PCBs. The disclosed system comprised of an optical inspection system that scans each layer - both sides - of identified layers, that are intended to create a specific PCB, and marks the scrap-units on a layer map; a storage mean to store the layer maps, using any method for storing layers' information; and a combining software that combines the layer maps to create a PCB map, wherein each scrap-unit, which one of its' layers has a defect, is marked. Moreover, the system can further includes an optimization software that matches plurality of layer maps of each terrace-layer of the PCB and define sets of identified layers to join into a PCB with minimum scrap-units, enabling to collect each of the defined sets to join into a PCB.

Description

Title: A System for Mapping Defective Printed Circuits
FIELD OF THE INVENTION
The present invention relates to the field of automatic optical
inspection systems and methods. More specifically, the present invention
relates to a system and method for mapping PCBs.
BACKGROUND OF TΗE INVENTION
Automatic optical inspection systems use image processing and
dedicated algorithms to inspect the surfaces of a PCB or a wafer in
order to recognize defects on this surface.
PCBs are usually made in a way of manufacturing a single board that
contains a plurality of PCBs. The production and all the whole process is
done on the single board and then the single board is cut to the PCBs.
l Large number of units [PCBs] can be produced on a single board and any number of them could be defective and known as "scrap-units". A single defect in one of the unit's layer is enough in order to disqualify the - unit. Since the processes are done on a board scale (not on a unit scale], it is very important to identify in process the scrap-units and therefore prevent any work and material investment on a scrap-unit.
The present invention can be use either the PCB is produced using
"built-up" method or "lamination" method. "Built-up" is the method in
which each layer is build directly on the lower layer and "lamination" is the
method in which each layer is produced individually and the layer are
collected and joined into a PCB by pressure or lamination.
Therefore, it would be advantageous to have a system and a
method, which uses the inspection platform to create a scrap-units map
of each specific board.
The present invention makes use, in a preferred embodiment, in "a
method for storing layers' information of a layers-made object", which is patent pending and internationally published on October 2, 2003 having the publication number WO 03/081535 A1.
SUMMARY OF THE INVENTION
The present invention is a scrap-units-mapping system and method, especially for mapping a multi-layers board that contains a plurality of PCBs.
According to the teachings of the present invention there is
provided a scrap-units-mapping system that includes:
a) an optical inspection system that scans each layer - both sides - of identified layers, that are intended to create a specific PCB, and marks the scrap-units on a layer map;
b) a storage mean to store the layer maps, using any method for storing layers' information; and
c) combining software that combines the layer maps to create a PCB map, wherein each scrap-unit, which one of its' layers has a defect, is marked. According to further features in the described preferred embodiment of the present invention, there is provided a scrap-units- mapping system that further includes: d) an optimization software that matches plurality of layer maps of each terrace-layer of the PCB and define sets of identified layers to join into a PCB with minimum scrap-units, enabling to collect each of defined sets to join into a PCB. e) a mechanism that collects, according to the optimization results, sets of the identified layers to join into PCBs
According to another preferred embodiment of the present
invention, there is provided the scrap-units-mapping system further
includes a display for displaying the PCB map.
In another preferred embodiment, there is provided the scrap-
units-mapping system, wherein the scrap-units on the PCB map are
marked in colors wherein each color defines the layer location of the
defect. In yet another preferred embodiment, there is provided the scrap- units-mapping system, wherein the method for storing layers' information is the method that is defined in the international publication WO 03/081535 A1.
According to yet another aspect of the present invention there is provided a method for scrap-units-mapping, especially for mapping a multi-layers board that contains a plurality of PCBs, including the following steps: a] scanning by an optical inspection system each layer - both sides - of identified layers that are intended to create a specific PCB and marking the scrap-units on a layer map;
b) storing the layer maps, using any method for storing layers' information; and
c] combining said layer maps to create a PCB map, wherein each scrap-unit, which one of its' layers is defective, is marked.
The method, according to the present invention, is also provided
with the additional following steps: d) matching, by using an optimization software, plurality of layer maps of each terrace-layer of said PCB and define sets of identified layers to join into a PCB with minimum scrap-units; and e) collecting, according to the optimization results, sets of the identified layers to join into PCBs.
The method, according to the present invention, is also provided,
further includes the step of coloring the scrap-units on the PCB map by
colors, wherein each color defines the defective layer.
The method, according to the present invention, is also provided,
wherein storing layers' information method, as is defined in the
international publication WO 03/081535 A1 , is used.
The present invention successfully addresses the shortcomings of
the existing technologies by providing system and method for scrap-units
mapping on a PCB. BRIEF_DESCRIPTI0N_0F THE. FIGURES
The invention is herein described, by way of example only, with reference to the accompanying drawings. With specific reference now to the drawings in detail, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of the preferred embodiments of the present invention only, and are presented in the cause of providing what is believed to be the most useful and readily understood description of the principles and conceptual aspects of the invention. In this regard, no attempt is made to show structural details of the invention in more detail than is necessary for a fundamental understanding of the invention, the description taken with the drawings making apparent to those skilled in the art how the several forms of the invention may be embodied in practice.
In the figures:
Figure 1 illustrates a flow chart of a preferred embodiment of the
present invention, using "lamination" method of production.
Figure 2 illustrates the mapping method, according to the present
invention, using an example of two-sided and three layers board with 25
PCBs. DESCRIPTION OF JHE PREFERED EMBODIMENTS
The present invention is a scrap-units-mapping system and method, especially for mapping a multi-layers board that contains a plurality of PCBs.
The system, according to the present invention, uses scanned images of the layers of a specific PCB. On each layer there are scrap-
units that could be identify. Actually, the scanned image is a map of
scrap-units of a single side of a single layer.
The system combines these maps to create a map that illustrates
the scrap-units location on the PCB that will be produced from these
layers. When the PCB production is finished, this map can be used for
the further process of this PCB (e.g. drilling).
When using "lamination" method to produce a PCB, optimizing
software can be used that selects, for each layer, a specific layer from a
plurality of layers of the same kind in order to produce a PCB with
minimum scrap-units. The principles and operation of the system according to the present invention may be better understood with reference to the drawing and the accompanying -description.
Referring now to the drawing, Figure 1 illustrates a flow chart of a preferred embodiment of the present invention, using "lamination" method of production. Three layers groups "A" 17, L1 , L2 and L3 are input to be scanned in the scan unit 18. The images pass to the mapping unit ISthat create maps for each layer. The layers 20pass to
an output place "B" and the maps are passed to the optimize unit 21.
The optimize unit and software 21 decided - in order to have a PCB with
minimum scrap-units - to select the third layer of L1 to be the first layer
of the PCB, the first layer of L2 to be the second layer and the second
layer of L3 to be the last layer of the PCB. The optimize unit 21 collect
the layers, according to its' decision and creates a PCB 22 with
minimum scrap-units and creates a compatible map that marks the
scrap-units to be used in the further process. Figure 2 illustrates the mapping method, according to the present invention, using an example of two-sided and three layers board with twenty-five PCBs.
Each of the three layers of the board is scanned, having images of side 1 and side 2 of each layer L1 , L2 and L3. The scrap-units 7/ are marked (in the illustration by "D"). The system combines the images into a map 12, which marks the location of the scrap-units with colors that identify the defect's layer location, the defects of L1 13, the defects of
layer L2 14, the defects of layer L3 75and multi-layers defects 16.
As used herein in the specification and in the claims section that
follows, the term "scrap-unit" and the like refer to the disqualify PCB-unit
on a single board that contains plurality of PCBs.
Although the invention has been described in conjunction with
specific embodiments thereof, it is evident that many alternatives,
modifications and variations will be apparent to those skilled in the art,
accordingly, it is intended to embrace all such alternatives, modifications
and variations that fall within the spirit and broad scope of the appended
claims.

Claims

WHAT IS CLAIMED IS:
1. A scrap-units-mapping system, especially for mapping a multilayers PCB that contains a plurality of PCBs, said system comprising: a] an optical inspection system that scans each layer - both sides - of identified layers, that are intended to create a specific PCB, and marks the scrap-units on a layer map; b] a storage mean to store said layer maps, using any method for storing layers' information; and c] combining software that combines said layer maps to create a PCB map, wherein each scrap-unit, which one of its' layers has a defect, is marked.
2. The scrap-units-mapping system of claim 1 , further includes: d) an optimization software that matches plurality of layer maps of each terrace-layer of said PCB and define sets of identified layers to join into a PCB with minimum scrap-units, enabling to collect each of said defined sets to join into a PCB.
3, The scrap-units-mapping system of claim 2, further includes: e] a mechanism that collects, according to said optimization results, sets of said identified layers to join into PCBs.
4. The scrap-units-mapping system of claim 1 , further includes a display for displaying said PCB map.
5. The scrap-units-mapping system of claim 1 , wherein the scrap- units on said PCB map are marked in colors wherein each color defines the layer location of said defect.
6. The scrap-units-mapping system of claim 1 , wherein said method for storing layers' information is the method that is defined in the international publication WO 03/081535 A1.
7. A scrap-units-mapping method, especially for use for mapping a multi-layers PCB that contains a plurality of PCBs, said method comprising; a] scanning by an optical inspection system each layer - both sides - of identified layers that are intended to create a specific PCB and marking the scrap-units on a layer map; b] storing said layer maps, using any method for storing layers' information; and c] combining said layer maps to create a PCB map, wherein each scrap-unit, which one of its' layers is defective, is marked.
8. The method of claim 7, further includes: d) matching, by using an optimization software, plurality of layer maps of each terrace-layer of said PCB and define sets of identified layers to join into a PCB with minimum scrap-units; and e) collecting, according to said optimization results, sets of said identified layers to join into a PCBs.
9. The method of claim 7, further coloring the scrap-units on said PCB map by colors, wherein each color defines the defective layer.
0. The method of claim 7, wherein storing layers' information method, as is defined in the international publication WO 03/08 535 A1 , is used.
PCT/IL2005/000650 2004-06-21 2005-06-19 A system for mapping defective printed circuits WO2005122695A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007517648A JP4923180B2 (en) 2004-06-21 2005-06-19 System for mapping defective printed circuits
CN2005800248665A CN101297305B (en) 2004-06-21 2005-06-19 A system for mapping defective printed circuits

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IL162650 2004-06-21
IL162650A IL162650A (en) 2004-06-21 2004-06-21 Scrap-units- mapping system for mapping multiple layers of a single board and method therefor

Publications (2)

Publication Number Publication Date
WO2005122695A2 true WO2005122695A2 (en) 2005-12-29
WO2005122695A3 WO2005122695A3 (en) 2007-05-18

Family

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PCT/IL2005/000650 WO2005122695A2 (en) 2004-06-21 2005-06-19 A system for mapping defective printed circuits

Country Status (5)

Country Link
JP (1) JP4923180B2 (en)
CN (1) CN101297305B (en)
IL (1) IL162650A (en)
TW (1) TWI275335B (en)
WO (1) WO2005122695A2 (en)

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CN101865652A (en) * 2009-04-15 2010-10-20 上海汽车制动系统有限公司 Detection method and system of EBS (Electronic Brake System) electromagnetic valve model discrimination
CN101621893B (en) * 2008-07-02 2011-04-13 欣兴电子股份有限公司 Process and equipment thereof for manufacturing imprint dividing board of defective subboard of circuit board

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CN102338754A (en) * 2010-07-22 2012-02-01 牧德科技股份有限公司 Method for detecting defects of power supply layer and ground layer of circuit board
CN102074031B (en) * 2011-01-13 2013-08-07 广东正业科技股份有限公司 Standard establishment method for observational check machine of printed circuit board
CN102136016A (en) * 2011-03-09 2011-07-27 瑞谷科技(深圳)有限公司 Printed circuit board (PCB) designing method and device
KR101478790B1 (en) 2013-10-14 2015-01-06 (주)에이티테크놀러지 Apparatus for testing Printed Circuit Board
US9885671B2 (en) 2014-06-09 2018-02-06 Kla-Tencor Corporation Miniaturized imaging apparatus for wafer edge
US9645097B2 (en) 2014-06-20 2017-05-09 Kla-Tencor Corporation In-line wafer edge inspection, wafer pre-alignment, and wafer cleaning
CN105588840B (en) * 2015-12-04 2019-01-25 广州视源电子科技股份有限公司 Electronic component positioning method and device
CN105873358B (en) * 2016-05-31 2019-02-05 Oppo广东移动通信有限公司 Multiple-printed-panel for circuit board
KR101751518B1 (en) * 2016-08-24 2017-06-27 주식회사 아이디디 Marking apparatus and method for PCB panel
CN108804738B (en) * 2018-03-22 2021-04-06 广州兴森快捷电路科技有限公司 Circuit board defect tracking method and device based on positioning hole and computer equipment

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CN101621893B (en) * 2008-07-02 2011-04-13 欣兴电子股份有限公司 Process and equipment thereof for manufacturing imprint dividing board of defective subboard of circuit board
CN101865652A (en) * 2009-04-15 2010-10-20 上海汽车制动系统有限公司 Detection method and system of EBS (Electronic Brake System) electromagnetic valve model discrimination

Also Published As

Publication number Publication date
WO2005122695A3 (en) 2007-05-18
IL162650A (en) 2014-09-30
TW200601927A (en) 2006-01-01
IL162650A0 (en) 2005-11-20
CN101297305B (en) 2012-08-22
JP2008504521A (en) 2008-02-14
JP4923180B2 (en) 2012-04-25
TWI275335B (en) 2007-03-01
CN101297305A (en) 2008-10-29

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