WO2005117134A1

WO2005117134A1 - Diode and thyristor

Info

Publication number: WO2005117134A1
Application number: PCT/JP2004/007181
Authority: WO
Inventors: Ikuko Ogasawara; Masaaki Tomita; Kazuhiko Ito
Original assignee: Shindengen Electric Manufacturing Co., Ltd.; Akita Shindengen Co., Ltd.
Priority date: 2004-05-26
Filing date: 2004-05-26
Publication date: 2005-12-08
Also published as: JPWO2005117134A1; JP4907341B2

Abstract

In order to realize a semiconductor device for overvoltage protection enabling to obtain a stabilized blocking voltage, a first P type conductive region (2) and a first N type conductive region (3) are formed in an N type semiconductor substrate (100) and second P type conductive regions (40, 41) are formed contiguously to the first P type conductive region (2) such that breakdown is determined in the first P type conductive region (2). Since the breakdown voltage is insusceptible to interface charges or interface trap due to this structure, the breakdown voltage is stabilized and the blocking voltage is not varied easily.

Description

Specification

Diodes and thyristors

Technical field

The present invention relates to a semiconductor device, and further relates to an overvoltage protection diode and an overvoltage protection semiconductor thyristor for protecting an electronic circuit system from an abnormal voltage or an abnormal current. Background art

[0002] Diodes and thyristors are widely used as semiconductor devices for overvoltage protection that protect electronic circuits from abnormal voltages occurring in communication lines such as home appliances, in-vehicle electronic boards, and telephone lines.

FIG. 2 is a cross-sectional view showing a diode according to the related art. In FIG. 2, 1 is a semiconductor substrate conductive region, 2 is a first P-type conductive region, 3 is a first N-type conductive region, 10 is a first electrode, 11 is a second electrode, 20, 21 is an insulator, and 100 is a semiconductor substrate. It is. FIG. 4 is a graph showing the reverse characteristics of the diode shown in FIG.

[0004] The semiconductor substrate 100 has N-type conductivity. The first P-type conductive region 2 has a P-type conductivity type formed inside the semiconductor substrate 100 by impurity diffusion. The first N-type conductive region 3 has N-type conductivity formed inside the semiconductor substrate 100 by impurity diffusion. The semiconductor substrate conductive region 1 is a remaining portion where the first P-type conductive region 2 and the first N-type conductive region 3 are not formed. The insulators 20 and 21 are formed for stabilizing the bonding interface between the exposed semiconductor substrate conductive region 1 and the first P-type conductive region 2, and are usually silicon oxide films obtained by oxidizing silicon. is there. The first electrode 10 and the second electrode 11 are electrodes formed on both main surfaces of the semiconductor substrate 100. Here, the first electrode 10 is electrically connected to the first P-type conductive region 2. Further, second electrode 11 is electrically connected to first N-type conductive region 3. The insulators 20 and 21 are formed for stabilizing the interface, and are usually silicon oxide films obtained by oxidizing silicon.

[0005] In the diode shown in FIG. 2, the side of the surface of semiconductor substrate 100 on which first P-type conductive region 2 is provided (hereinafter, this side is referred to as the upper surface side. Also, the side of the semiconductor substrate 100 on which the first P-type conductive region 2 is provided is referred to as the upper side.) The side of the surface on which the IN-type conductive region 3 is provided (hereinafter referred to as the lower surface side. For other diodes to be described hereinafter, the side of the semiconductor substrate 100 on which the first N-type conductive region 3 is provided is the lower surface side. The forward direction is the direction of application of a voltage that is a positive potential with respect to (). This direction is also referred to as the forward direction of the voltage applied to the other diodes described hereinafter. Conversely, the direction of application of the voltage that makes the upper surface side a negative potential with respect to the lower surface side is the reverse direction (this direction is also the reverse direction of the voltage application direction of the other diodes described hereinafter). I do.

FIG. 4 is a graph showing the electrical characteristics in the reverse direction of the diode shown in FIG. As shown in FIG. 4, in the reverse direction, when a breakdown voltage is reached at the junction interface between the first P-type conductive region 2 and the first N-type conductive region 3, electrons and holes are actively generated, and the reverse voltage is increased. Is limited.

[0007] As described above, a diode having the above reverse characteristics has a power _S for suppressing a surge voltage with a breakdown voltage _vb , and a very fast electric surge in a nanosecond unit like an electrostatic discharge. However, the response is very fast, so it is almost used in places where surge voltage due to static electricity is easily picked up, such as in-vehicle electronic equipment that requires high reliability and reliability ( For example, see Patent Document 1).

[0008] In addition, since it is made of a semiconductor material, it has a great advantage in maintenance that reliability can be maintained for a long time without being consumed by an electric surge.

[0009] However, even in a diode having such an advantage, the breakdown voltage may change as it is used at a high temperature for a long time. This is because at the interface 9 between the first P-type conductive region 2 and the semiconductor substrate conductive region 1 and in the vicinity of the interface 9 adjacent to the insulators 20 and 21, the interface charge and the electronic state of the interface trap change. However, it is necessary to control very accurately the impurities contained in the manufacturing environment such as a clean room and the materials used.

[0010] However, since the production environment and the control of impurities in the materials used are costly, there is a limit to the implementation.

FIG. 3 is a cross-sectional view showing a thyristor according to the related art. In FIG. 3, 101 is a semiconductor Body conductive area, 102 is the 1st N-type conductive area, 103 is the 2nd N-type conductive area, 104 is the 1st P-type conductive area, 110-pole first electrode, llli-second electrode, 120, 121, 122, 123-pole insulation The body 200 is a semiconductor substrate. FIG. 5 is a graph showing the forward characteristics of the thyristor shown in FIG.

The semiconductor substrate 200 has a 有する -type conductivity. The first N-type conductive region 102 and the second Ν-type conductive region 103 have a Ν-type conductivity formed inside the semiconductor substrate 200 by impurity diffusion. The first P-type conductive region 104 has a 導電 -type conductivity type formed by impurity diffusion inside the semiconductor substrate 200. The semiconductor substrate conductive region 101 is a remaining portion where the first N-type conductive region 102, the second Ν-type conductive region 103, and the first P-type conductive region 104 are not formed. The first electrode 110 and the second electrode 111 are electrodes formed on both main surfaces of the semiconductor substrate 200. Here, the first electrode 110 is electrically connected to both the first P-type conductive region 104 and the first N-type conductive region 102. Further, the second electrode 111 is electrically connected to the second type conductive region 3.

[0013] In the thyristor shown in FIG. 3, the side of the surface of the semiconductor substrate 200 on which the first N-type conductive region 102 is provided (hereinafter referred to as the upper surface side). The side of the surface on which the first N-type conductive region 102 is provided is referred to as the upper surface side, and the side of the surface on which the second Ν-type conductive region 103 is provided (hereinafter referred to as the lower surface side). For the thyristor, the side of the surface of the semiconductor substrate 200 where the second type conductive region 103 is provided is referred to as the lower surface side. This direction is also referred to as a forward direction. Conversely, the direction of application of the voltage that makes the upper surface side a negative potential with respect to the lower surface side is the reverse direction (the direction of the voltage application to the other thyristors described hereinafter is also the reverse direction). It shall be.

FIG. 5 is a graph showing forward electrical characteristics of the thyristor shown in FIG. As shown in FIG. 5, in the forward direction, the first P-type conductive region 104 is an emitter, the first N-type conductive region 102 is a base, and the semiconductor substrate conductive region 101 is a collector. Emitter, with semiconductor substrate conductive region 101 as the base and first N-type conductive region 102 as the collector 電子 Electrons and holes are exchanged between transistors and turned off. An ignition operation for shifting from the state to the on state is performed.

That is, in the thyristor shown in FIG. 3 which was initially in the off state, the forward voltage force applied between the first electrode 110 and the second electrode 111 reaches the breakover voltage Vb in FIG. Alternatively, current flows due to punch-through. That is, electrons and holes are actively exchanged at the boundary surface 190 between the first N-type conductive region 102 and the semiconductor substrate conductive region 101 in the reverse bias state and near the boundary surface 190. Since the base of the PNP transistor and the collector of the NPN transistor are the common first N-type conductive region 102, the thyristor is fired and transitions to the ON state. It goes without saying that the depletion layer is maximized when the above-mentioned breakover voltage is reached.

It is a well-known fact that a thyristor having a PNPN structure shifts from an off state to an on state due to a firing operation. Therefore, a more detailed description of the internal operation is omitted here. In the structure shown in FIG. 3, since the periphery of the first N-type conductive region 102 has a curvature and the electric field intensity locally increases, when the avalanche breakdown starts the ignition operation, the current that triggers the ignition is the first P-type current. It flows from the peripheral portion of the first N-type conductive region 102 where the type conductive region 104 is located toward the vicinity of the center of the first N-type conductive region 102.

The thyristor performing the above-described ignition operation suppresses the surge voltage with the breakover voltage Vb as described above. Therefore, although the change is smaller than that of electrostatic discharge, the response to electrical surges in microseconds such as large lightning-induced surges of energy is not affected by other surge protection elements, such as lightning arresters and metal. Since it is much faster than oxide varistors, it is almost used where lightning-induced surges can be easily picked up, such as electronic equipment in communication networks that require high reliability.

[0018] Further, since it is made of a semiconductor material, there is a great advantage in maintenance that reliability can be maintained for a long period without being consumed by a surge current.

However, even in a thyristor having such an advantage, the breakover voltage may change as the thyristor is used at a high temperature for a long time. This is because the insulator 12 in the boundary between the first N-type conductive region 102 and the semiconductor substrate conductive region 101 and near the boundary 190 Forces considered to be due to changes in the electronic state of interface charges and interface traps in the region adjacent to 0, 121 It is necessary to control very accurately the impurities contained in the manufacturing environment such as clean rooms and the materials used .

[0020] However, since the production environment and the control of impurities in the materials used are costly, there is a limit to the implementation.

Patent Document 1: Japanese Patent Application Laid-Open No. 2002-373897

Disclosure of the invention

Problems to be solved by the invention

The present invention further improves a diode or thyristor having a conventional structure so that a breakdown voltage or a breakover voltage does not fluctuate even at a high temperature, that is, a blocking voltage is reduced by an overvoltage protection semiconductor device. For the purpose of stabilizing.

Means for solving the problem

[0022] As a means for solving the above-mentioned problems, the present invention provides a semiconductor device of a second conductivity type opposite to a semiconductor substrate formed by being exposed on one surface of a semiconductor substrate of the first conductivity type. A diode formed by forming a first conductive region and a second conductive region of a first conductivity type formed by being exposed on the other surface opposite to the one surface of the semiconductor substrate; A third conductive region of a second conductive type is formed so as to be exposed on one surface and to be adjacent to the first conductive region or to partially overlap the periphery of the first conductive region. Thus, the breakdown occurs in the inner peripheral portion of the third conductive region or in the vicinity of the inner peripheral portion or in the first conductive region or in the vicinity of the first conductive region.

In the above-described diode configuration, since the breakdown voltage in the reverse direction is not determined at the boundary between the exposed third conductive region and the semiconductor substrate conductive region 1 and in the vicinity thereof, the exposed third conductive region is not determined. It is possible to stabilize the breakdown voltage even if the interface charge or the electronic state of the interface trap at and near the interface between the semiconductor substrate and the conductive region of the semiconductor substrate changes. That is, in the above-described configuration, the breakdown voltage is determined at the inner peripheral portion of the third conductive region or at the first conductive region.

Accordingly, compared to the conventional structure shown in FIG. 2, the blocking voltage is more stable than the semiconductor for overvoltage protection. It is easy to realize the body device.

[0025] In the above-described diode, the third conductive region may surround the first conductive region when the semiconductor substrate is viewed in a plan view.

Therefore, it is possible to more reliably generate a breakdown in the inner peripheral portion of the third conductive region or in the vicinity of the inner peripheral portion or in the vicinity of the first conductive region or the first conductive region. .

[0027] The present invention also provides a first conductive region of a second conductivity type opposite to the semiconductor substrate, which is formed by being exposed on one surface of a semiconductor substrate of the first conductivity type; And a second conductive region of the first conductivity type formed in the first conductive region and exposed on the other surface of the semiconductor substrate opposite to the one surface. A thyristor having a third conductive region of a second conductivity type formed in such a manner that the thyristor is formed so as to be adjacent to the first conductive region or to partially overlap the peripheral portion of the first conductive region. A fourth conductive region of the second conductivity type is provided, and a breakover occurs at the inner peripheral portion of the fourth conductive region or in the vicinity of the inner peripheral portion, or the first conductive region or the first conductive region. In the vicinity of the building.

In the configuration of the thyristor described above, the avalanche breakdown or punch-through that triggers a breakover is not determined at the boundary between the exposed fourth conductive region and the semiconductor substrate conductive region and in the vicinity thereof. The breakover voltage can be stabilized even if the interface charge or the electronic state of the interface trap changes at and near the boundary between the conductive region of FIG. 4 and the semiconductor substrate conductive region. That is, in the above-described configuration, the breakover voltage is determined at the inner peripheral portion of the fourth conductive region or at the first conductive region.

Therefore, as compared with the conventional structure shown in FIG. 3, a semiconductor device for overvoltage protection with a stable blocking voltage can be realized.

Further, in the thyristor, the fourth conductive region may surround the first conductive region when the semiconductor substrate is viewed in a plan view.

Therefore, a breakover occurs more reliably in the inner peripheral portion of the fourth conductive region or in the vicinity of the inner peripheral portion or in the vicinity of the first conductive region or the first conductive region. You can live.

[0032] Further, the fourth conductive region may be exposed on the one surface.

Accordingly, it is possible to more reliably cause a breakover in the inner peripheral portion of the fourth conductive region or in the vicinity of the inner peripheral portion, or in the vicinity of the first conductive region or the first conductive region. it can.

[0034] In addition, the present invention may be arranged such that a plurality of the second conductive regions are provided in the above configuration.

[0035] Further, the present invention provides a first conductive region of a second conductivity type opposite to the semiconductor substrate formed by being exposed on one surface of a semiconductor substrate of the first conductivity type; And a second conductive region of the first conductivity type formed in the first conductive region and exposed on the other surface of the semiconductor substrate opposite to the one surface. A third conductive region of the second conductivity type formed in the third conductive region, and a third conductive region of the first conductivity type formed in the third conductive region exposed on the other surface opposite to the one surface. In the thyristor having the fifth conductive region, the fourth conductive type fourth conductive region is formed so as to be adjacent to the first conductive region or partially overlap the peripheral portion of the first conductive region. The region is formed so as to be adjacent to the third conductive region or to partially overlap the peripheral portion of the third conductive region. A sixth conductive region of the second conductivity type is provided, and a breakover occurs at an inner periphery of the fourth conductive region or near the inner periphery, or near the first conductive region or the first conductive region, Alternatively, it occurs in the inner periphery of the sixth conductive region or in the vicinity of the inner periphery or in the third conductive region or in the vicinity of the third conductive region.

[0036] In the above-described configuration, the breakdown voltage that triggers a breakover in both the forward and reverse directions causes the boundary surface between the exposed fourth conductive region and the semiconductor substrate conductive region and the vicinity thereof or the exposed sixth conductive region. The boundary between the exposed fourth conductive region and the semiconductor substrate conductive region and the boundary between the exposed sixth conductive region and the exposed sixth conductive region and the semiconductor substrate conductive region because the boundary is not determined at or near the boundary surface of the semiconductor substrate conductive region. And the electronic state of the interface charge or interface trap in the vicinity of the interface changes, The bar voltage can be stabilized. That is, in the above configuration, the breakover voltage is determined by the inner peripheral portion of the fourth conductive region, the inner peripheral portion of the first conductive region, the inner peripheral portion of the sixth conductive region, or the third conductive region. .

Accordingly, a thyristor having a stable blocking voltage can be realized as compared with the conventional structure shown in FIG.

[0038] Further, in the thyristor of the present invention, the fourth conductive region may surround the first conductive region when the semiconductor substrate is viewed in a plan view.

Further, according to the present invention, in the above thyristor, the sixth conductive region may surround the third conductive region when the semiconductor substrate is viewed in plan.

[0040] In addition, the present invention may be arranged such that in the thyristor, the fourth conductive region is exposed on the one surface.

[0041] In the present invention, in the thyristor described above, the sixth conductive region may be exposed on the other surface.

[0042] Further, the present invention further provides a thyristor according to the present invention, further comprising a second conductive type seventh conductive region that is exposed on the one surface and penetrates the second conductive region. May be formed. In this case, a so-called short emitter structure is formed on the upper surface side.

Further, an eighth conductive region of the second conductivity type, which is exposed on the other surface opposite to the one surface and formed so as to penetrate the fifth conductive region, may be further provided. Good. In this case, a so-called short emitter structure is formed on the lower surface side.

Further, according to the present invention, in the above configuration, one or two of the second conductive region, the fifth conductive region, the seventh conductive region, and the eighth conductive region are provided. There may be more than one.

The invention's effect

As described above, according to the present invention, the region for determining the blocking voltage is not located at the PN junction exposed on the surface of the semiconductor substrate and in the vicinity thereof. Therefore, even when the PN junction exposed on the surface of the semiconductor substrate and the electronic state of interface charges and interface traps existing near the PN junction change, the blocking voltage does not easily change. Therefore, even when exposed to high temperature for a long time, the overvoltage It is easy to realize a protective semiconductor device.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, a diode and a thyristor according to an embodiment of the present invention will be described.

Note that the present invention is not limited to the embodiments described below, and any semiconductor device having a diode or thyristor structure can be used as a composite device having other types of element structures such as an insulated gate field effect transistor. It can be preferably applied to a type semiconductor device and the like.

First, the diode according to the first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a sectional view showing a diode according to the first embodiment of the present invention. In FIG. 1, 1 is a semiconductor substrate conductive region, 2 is a first P-type conductive region, 3 is a first N-type conductive region, 10 is a first electrode, 11 is a second electrode, 20, 21 is an insulator, and 40, 41. Denotes a second P-type conductive region, and 100 denotes a semiconductor substrate.

[0048] The semiconductor substrate 100 is silicon having a rectangular cylindrical shape, and has N-type conductivity. A first P-type conductive region 2 and a first N-type conductive region 3 are formed on a semiconductor substrate 100. Further, the second P-type conductive regions 40 and 41 are formed adjacent to the first P-type conductive region 2. The semiconductor substrate conductive region 1 is a remaining portion where the first P-type conductive region 2, the first N-type conductive region 3, and the second P-type conductive regions 40 and 41 are not formed. Here, the first P-type conductive region 2 and the second P-type conductive regions 40 and 41 are electrically connected to the first electrode 10, and the first N-type conductive region 3 is electrically connected to the second electrode 11.

The first P-type conductive region 2 and the second P-type conductive regions 40 and 41 are formed by high-temperature diffusion after introducing a P-type impurity from the outside using an appropriate mask. Here, deep diffusion is performed so that the breakdown occurs at the boundary surface between the semiconductor substrate conductive region 1 and the first P-type conductive region 2 and near the boundary surface between the semiconductor substrate conductive region 1 and the second P-type conductive region 40, 41. The concentration of the second P-type conductive regions 40 and 41 is lower than that of the first P-type conductive region 2. The first N-type conductive region 3 is formed by high-temperature diffusion after introducing N-type impurities from the outside.

[0050] If necessary, the first P-type conductive region 2 and the first N-type conductive region 3 are separated by another mask in order to increase the conductivity of the region in contact with the first electrode 10 and the region in contact with the second electrode 11. It is of course possible to form them. For example, the first P-type conductive region 2 and the first N-type conductive region After the impurity diffusion in the region 3, the resistance of the region in contact with the first electrode 10 and the second electrode 11 of the first P-type conductive region 2 and the first N-type conductive region 3 is reduced separately. After introducing a high concentration of P-type and N-type impurities, high-temperature diffusion may be performed. Other conductive regions may be formed by multiple diffusions as needed, but are usually formed by a single diffusion.

After the N-type and P-type impurity diffusion processes are all completed, insulators 20 and 21 such as an oxide film are laminated and formed, and further, a first electrode 10 and a second electrode 11 are formed. Openings (diffusion windows) are formed in insulators 20 and 21 by etching. After that, the first electrode 10 and the second electrode 11 are formed.

[0052] The insulators 20, 21 are usually formed of a silicon oxide film or the like. If it does not adversely affect the characteristics of the diode to be manufactured, it may be formed of a silicon nitride film or glass, and may be formed of a multilayer structure including a plurality of insulators.

The second P-type conductive regions 40 and 41 are preferably formed in a frame shape so as to surround the first P-type conductive region 2. The reason for this is that, by surrounding the first P-type conductive region 2, the breakdown voltage described below is not affected by the state of the interface charge and the interface trap between the semiconductor substrate 100 and the insulators 20, 21 according to the present invention. This is because the effect of the above can be surely achieved. Note that it is also possible to form a plurality of divided portions without forming them in a frame shape, but in this case, it is preferable to form them at the corners of the first P-type conductive region 2. Also, many of these may be arranged as independent small island-shaped areas. Further, the first P-type conductive region 2 may have another shape such as a circle or an ellipse. Further, the shape of the semiconductor substrate 100 is not limited to a rectangular cylinder, but may be another shape such as a cylindrical shape.

Subsequently, characteristics of the operation of the diode according to the first embodiment of the present invention will be described. As shown in FIG. 1, the diode according to the first embodiment of the present invention is formed so that breakdown occurs in the reverse direction at the boundary surface between the semiconductor substrate conductive region 1 and the first P-type conductive region 2. I have. Therefore, the influence of the interface charge generated between the insulators 20 and 21 and the semiconductor substrate 100 and the electronic state of the interface trap on the breakdown voltage is almost negligible. Almost disappears. Further, the reason why the breakdown occurs at the interface between the semiconductor substrate conductive region 1 and the IP-type conductive region 2 due to the reverse voltage and the breakdown voltage does not fluctuate will be described in detail. FIG. 10 is a cross-sectional view for assisting the explanation of mathematical formulas related to the breakdown voltage stabilizing mechanism.

Here, the two-dimensional concentration distribution N of the first P-type conductive region 2 can be approximated by the following equation, where x is the horizontal direction and y is the vertical direction in FIG.

1

Equation 1

[0057]

[0058] Here, exp is an exponential function, erfc is a complementary error function, N is the surface concentration of the first P-type conductive region 2,

sl

X is the characteristic depth of the IP type conductive region 2 in the X direction, and y is the characteristic of the IP type conductive region 2 in the y direction. Cl cl

Is the semiconductor substrate surface, X is the left end of the diffusion window when the first P-type conductive region 2 is formed, and X is the right end of the diffusion window when the first P-type conductive region 2 is formed. Also, holes are made in the diffusion mask.

2

It is assumed that diffusion takes place through a diffusion window of x = x and x = x.

1 2

[0059] This approximation formula relatively well agrees with the actual concentration distribution when deep diffusion is performed, for example, at a depth of about 30 _βm . However, it is known that the mechanism of impurity diffusion in a silicon semiconductor substrate is not simple, and the approximation accuracy of the above equation may not be sufficient depending on the type of impurity atoms and the diffusion method or time.

Similarly, the two-dimensional concentration distribution N of the second P-type conductive region 40 and the two-dimensional

2a

The density distribution N can be approximated by the following equation, where x is the horizontal direction and y is the vertical direction.

2b

Equation 2

[0061]

Equation 3

Here, N is the surface concentration of the second P-type conductive regions 40 and 41, and x is the second P-type conductive regions 40 and 41 s2 c2

Is the characteristic depth in the x direction, y is the characteristic depth in the y direction of the second P-type conductive regions 40 and 41, and y = 0 is half c2

X is the left edge of the diffusion window when forming the second P-type conductive region 40, X is the second P-type conductive

3 4

X is the right end of the diffusion window when the region 40 is formed, X is the left end of the diffusion window when the second P-type conductive region 41 is formed,

Five

X is the right end of the diffusion window when the second P-type conductive region 41 is formed. Also, holes are formed in the diffusion mask.

6

X = x from x = x diffusion window and x = x force, etc. simultaneously and identically through x = x diffusion window

1 2 3 4

It is assumed that diffusion is performed in a manner. As in the case of the first P-type conductive region 2, this approximate expression may not have sufficient accuracy depending on the type of impurity atoms, the method of diffusion, the time, and the like.

Here, the second P-type conductive regions 40 and 41 are adjacent to each other from the outside of the first P-type conductive region 2 when the semiconductor substrate 100 is viewed from above or at the periphery of the first P-type conductive region 2. It is formed so as to partially overlap. Therefore, for example, since it is formed in a frame shape so as to surround the first P-type conductive region 2,

Equation 4

[0065]

χ ₃

[0066]

relationship of x ₂ rather than x _6.

Further, when the junction depth of the first P-type conductive region 2 with the semiconductor substrate conductive region 1 is X, and the junction depth of the second P-type conductive regions 40 and 41 with the semiconductor substrate conductive region 1 is X. , Semiconductor j2

Assuming that the concentration of the substrate conductive region 1 is N, the following relationship is established. [0068]

[0069]

,

Here, the first P-type conductive regions 2 are the same P-type and N-type second P-type conductive regions 40 and 41.

8

Are formed at the end of the first P-type conductive region 2 when viewed from the top, i.e., at x = x and its vicinity and X = x and its vicinity. breakdown

2

Occurs, the breakdown voltage is the semiconductor substrate conductive region N, the surface concentration N,

B S1 is considered to be determined by the junction depth X. That is, the breakdown voltage V is

It can be approximated by jl bl expression.

Equation 8

[0071]

V _bl = f (N _B ,

Further, since the second P-type conductive regions 40 and 41 surround the first P-type conductive region 2 and are formed deeper than the first P-type conductive region 2 when the first P-type conductive region 2 is viewed from above, x = x or its

Three

And the outer periphery indicated at or near χ = χ (outside, that is,

6

The edge indicated by the curvature r at the periphery on the opposite side of the

Four

And has an end portion indicated by a curvature r on an inner peripheral portion indicated by or near χ = χ.

Five

The end of the outer peripheral portion and the end of the inner peripheral portion have a curvature (x = (x + x) Z2, x = (x + x)) at the center of the second P-type conductive regions 40 and 41. / 2) is smaller than the curvature. By the way, the second

3 4 5 6

The curvature of the central portion (x = (x + x) / 2, x = (x + x) / 2) of the P-type conductive regions 40 and 41 is the second.

5 6

The horizontal size (W = x-X, X-X) of the diffusion window of the P-type conductive regions 40 and 41 is

4 3 6 5

If it is sufficiently larger than the depth X, it is almost infinite. Therefore, when the junction between the second P-type conductive regions 40 and 41 and the semiconductor substrate conductive region 1 is in a reverse bias state, the electric field strength is increased at the ends. Therefore, when a breakdown occurs in the second P-type conductive regions 40 and 41, the point at which the breakdown starts is the end.

Although the breakdown voltage has a close relationship with the electric field distribution generated at the junction between the second P-type conductive regions 40 and 41 and the semiconductor substrate conductive region 1 and in the vicinity thereof, in particular, the second P-type conductive regions 40 and 41 The electric field distribution at and around the outer periphery of the substrate is affected by the state of the interface charge and the interface trap between the semiconductor substrate 100 and the insulators 20 and 21. That is, when a breakdown occurs at the outer periphery of the second P-type conductive regions 40 and 41, the breakdown voltage V is approximated by the following equation.

b2

I can do it.

Equation 9

[0076]

_{_{V b 2 = f (N B}} , x j2, N s2, r, Q 88) where, Q is the interface charge density.

ss

When breakdown occurs at the inner peripheral portions 50 and 51 of the second P-type conductive region, the semiconductor substrate

The breakdown voltage V can be approximated by the following equation, since it is considered that it is not easily affected by the interface charge between 100 and insulators 20, 21 and the state of the interface trap.

b2i

Equation 10

_{_{V b 2i = f (N B}} , x j2, N s2, r)

Here, the concentration gradient a of the impurity is considered to be the ratio of the concentration difference N between the two points to the distance q between the two points when viewed two-dimensionally, so that the concentration gradient a of the first P-type conductive region 2 is Next formula

Represented by 1. By the way, when the concentration gradient a increases, the break of the IP type conductive region 2 occurs.

1

The down voltage V tends to be small.

bl

Equation 11

Similarly, the concentration gradient a of the second P-type conductive regions 40 and 41 represented by the following equation increases.

2

And the breakdown voltages V, V of the second P-type conductive regions 40, 41 tend to be small. Equation 12

Therefore, in the first embodiment of the present invention, x = (

1

X + χ) / 2, the value at y = x is x = (x) of the concentration gradient a of the second P-type conductive regions 40, 41.

2

+ χ) Ζ2 or χ = (χ + χ) / 2, y = x.

4 5 6 jl

[0083] That is, between the a and the a

1 2

Equation 13

The relationship is established.

[0085] Therefore,

Equation 14

[0086]

1, ^ b 2i, b 2, and in the first embodiment of the present invention, the breakdown voltage is not affected by the state of the interface charge or interface trap between the semiconductor substrate 100 and the insulators 20, 21. An effect is obtained.

[0087] Of course, depending on the design, breakdown may occur at the inner peripheral portions 50 and 51 of the second P-type conductive region. However, even in such a case, the electronic state of interface charge and interface trap breaks. The influence on the down voltage is almost negligible, and there is almost no change in the blocking voltage due to the change in the interface charge and the electronic state of the interface trap.

As described above, according to the structure of the diode according to the first embodiment of the present invention, the diode as an overvoltage protection semiconductor device having a stable breakdown voltage and little change in blocking voltage. Can be realized.

A thyristor according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a sectional view showing a thyristor according to the second embodiment of the present invention. In FIG. 6, 101 is a semiconductor substrate conductive region, 102 is a first N-type conductive region, 103 is a second N-type conductive region, 104 μm is a first P-type conductive region, 110 f is a first electrode, lllf is a second electrode, 120 , 121, 122, 123 »insulators, 140, 141 are third N-type conductive regions, and 200 is a semiconductor substrate.

[0090] The semiconductor substrate 200 is silicon having a rectangular cylindrical shape, and has a P-type conductivity. A first N-type conductive region 102 and a second N-type conductive region 103 are formed on a semiconductor substrate 200. Further, a first P-type conductive region 104 is formed in the first N-type conductive region 102. Here, the first N-type conductive region 102 and the first P-type conductive region 104 are electrically connected to the first electrode 110, and the second N-type conductive region 103 is electrically connected to the second electrode 111. Further, the third N-type conductive regions 140 and 141 are arranged so as to be adjacent to the first N-type conductive region 102.

[0091] The first N-type conductive region 102, the second N-type conductive region 103, and the third N-type conductive regions 140 and 141 are formed by high-temperature diffusion after introducing N-type impurities from the outside using an appropriate mask. You. Here, deep diffusion is performed so that a breakover occurs at the interface between the semiconductor substrate conductive region 101 and the first N-type conductive region 102 and the interface between the semiconductor substrate conductive region 101 and the third N-type conductive region 140, 141. The concentration of the nearby third N-type conductive regions 140 and 141 is lower than that of the first N-type conductive region 102. The first P-type conductive region 104 is formed by high-temperature diffusion after introducing a P-type impurity from the outside. The semiconductor substrate conductive region 101 is a remaining portion where the first N-type conductive region 102, the second N-type conductive region 103, the first P-type conductive region 104, and the third N-type conductive regions 140 and 141 are not formed. .

[0092] If necessary, the first P-type conductive region 104 and the second N-type conductive region 103 are formed by another mask in order to increase the conductivity of the region in contact with the first electrode 110 and the second electrode 111. Of course, it is possible. For example, the first P-type conductive region 104 and the second N-type conductive region After the impurity diffusion of 103, the P-type conductive region 104 and the second N-type conductive region 103 are separated by P in order to reduce the resistance of the region in contact with the first electrode 110 and the second electrode 111. High-temperature diffusion may be performed after high-type and N-type impurities are introduced. Other conductive regions may be formed by multiple diffusions as needed, but are usually one time.

After the N-type and P-type impurity diffusion steps are all completed, insulators 120, 121, 122, 123 such as oxide films are laminated and formed, and the first electrode 110 and the second electrode 111 are further etched. Open the windows for After that, the first electrode 110 and the second electrode 111 are formed.

[0094] The insulators 120, 121, 122, and 123 are usually formed of a silicon oxide film or the like. If there is no problem in characteristics, it can be made of silicon nitride film or glass, and it can be formed with a multilayer structure composed of multiple insulators.

[0095] The third N-type conductive region is preferably formed in a frame shape. Note that it is also possible to form a plurality of portions by dividing the frame without forming them in a frame shape. Alternatively, a large number of these may be arranged as independent small island-shaped regions. In addition, the first N-type conductive region 102 may have another shape such as a circle or an ellipse. Further, the shape of the semiconductor substrate 200 is not limited to a rectangular cylinder, but may be another shape such as a cylindrical shape.

[0096] Next, characteristics of the operation of the thyristor according to the second embodiment of the present invention will be described. As shown in FIG. 6, the thyristor according to the second embodiment of the present invention is formed so that breakover occurs in the forward direction at the boundary between the semiconductor substrate conductive region 101 and the first N-type conductive region 102. I have.

[0097] Therefore, the influence of the interface charge generated between the insulators 120 and 121 and the semiconductor substrate 200 and the electronic state of the interface trap on the breakover voltage is almost negligible due to the change in the interface charge and the electronic state of the interface trap. The fluctuation of the blocking voltage that occurs is hardly observed. The third N-type conductive regions 140 and 141 are usually deeply diffused in order to make the impurity concentration lower than that of the first N-type conductive region 102. In this case, the first N-type conductive region 102 is surrounded around the upper surface. As described above, the third N-type conductive regions 140 and 141 have regions of large curvature at the inner peripheral portions 150 and 151 of the third N-type conductive regions 140 and 141 as well as at the outer peripheral portion. Will be. [0098] Therefore, depending on the design, breakdown may occur on the inner peripheral side of the third N-type conductive regions 140 and 141, but even in such a case, the effect of the interface charge and the electronic state of the interface trap on the breakdown voltage is not significant. Almost no fluctuations in the blocking voltage due to the change in the interface charge and the electronic state of the interface trap are almost eliminated.

As described above, according to the structure of the thyristor according to the second embodiment of the present invention, a semiconductor device for overvoltage protection in which the breakover voltage is stable and the fluctuation of the blocking voltage is almost zero is obtained. A thyristor can be realized.

[0100] A thyristor according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a sectional view showing a thyristor according to the third embodiment of the present invention. In FIG. 7, 101 is a semiconductor substrate conductive region, 102 is a first N-type conductive region, 103 is a second N-type conductive region, 104 is a first P-type conductive region, 105 is a second P-type conductive region, and 110 is a first electrode. Reference numeral 111 denotes a second electrode, insulators 120, 121, 122, and 123f, third N-type conductive regions 140 and 141f, fourth N-type conductive regions 142 and 143f, and 200 a semiconductor substrate.

[0101] The semiconductor substrate 200 is silicon having a prismatic shape, and has a P-type conductivity. A first N-type conductive region 102 and a second N-type conductive region 103 are formed on a semiconductor substrate 200. Further, a first P-type conductive region 104 is formed in the first N-type conductive region 102. Further, a second P-type conductive region 105 is formed in the second N-type conductive region 103. Here, the first N-type conductive region 102 and the first P-type conductive region 104 are electrically connected to the first electrode 110, and the second N-type conductive region 103 and the second P-type conductive region 105 are electrically connected to the second electrode 111. Connected to. Further, the third N-type conductive regions 140 and 141 are arranged so as to be adjacent to the first N-type conductive region 102. Further, the fourth N-type conductive regions 142 and 143 are arranged so as to be adjacent to the second N-type conductive region 103.

[0102] Further, the first N-type conductive region 102, the second N-type conductive region 103, the third N-type conductive regions 140 and 141, and the fourth N-type conductive regions 142 and 143 are formed by using an appropriate mask to remove N-type impurities from the outside. After being introduced from, it is formed by high-temperature diffusion. Here, deep diffusion is performed so that breakover occurs at the boundary between the semiconductor substrate conductive region 101 and the first N-type conductive region 102 or at the boundary between the semiconductor substrate conductive region 101 and the second N-type conductive region 103. The concentration of the third N-type conductive regions 140 and 141 near the boundary between the semiconductor substrate conductive region 101 and the third N-type conductive regions 140 and 141 is made smaller than that of the first N-type conductive region 102, and the semiconductor substrate conductive region 101 and the fourth N-type The concentration of the fourth N-type conductive regions 142 and 143 near the boundary surface between the conductive regions 142 and 143 is made lower than that of the second N-type conductive region 103. The first P-type conductive region 104 and the second P-type conductive region 105 are formed by high-temperature diffusion after introducing P-type impurities from the outside.

[0103] If necessary, the first P-type conductive region 104, the second P-type conductive region 105, and the first N-type are formed by using another mask in order to increase the conductivity of the region in contact with the first electrode 110 and the second electrode 111. It is of course possible to form the conductive region 102 and the second N-type conductive region 103. For example, after performing the impurity diffusion of the first N-type conductive region 102 and the second N-type conductive region 103, the first electrode 110 and the second electrode 111 in the first N-type conductive region 102 and the second N-type conductive region 103 are formed. In order to reduce the resistance value of the contact region, high-temperature diffusion may be performed after separately introducing a high-concentration N-type impurity. Other conductive regions may be formed by multiple diffusions as needed, but usually only once.

After the N-type and P-type impurity diffusion steps have all been completed, insulators 120, 121, 122, 123 such as oxide films are laminated and formed, and the first electrode 110 and the second electrode 111 are further etched. Open the windows for After that, the first electrode 110 and the second electrode 111 are formed.

[0105] The insulators 120, 121, 122, and 123 are usually formed of an oxide film or the like. If there is no problem in terms of characteristics, force S, which can be made of silicon nitride film or glass, or a multilayer structure consisting of multiple insulators.

The third N-type conductive region and the fourth N-type conductive region are preferably formed in a frame shape. Note that it is also possible to form a plurality of divided portions without forming them in a frame shape, but in this case, it is preferable to form them at the corners of the first N-type conductive region 102 and the second N-type conductive region 103. Also, a large number of these may be arranged as independent small island regions. Further, the first N-type conductive region 102 and the second N-type conductive region 103 may have other shapes such as a circle and an ellipse. Furthermore, the shape of the semiconductor substrate 200 is not limited to the rectangular tube shape, but may be another shape such as a cylindrical shape.

[0107] Next, characteristics of the operation of the thyristor according to the third embodiment of the present invention will be described. As shown in FIG. 7, the thyristor according to the third embodiment of the present invention is formed so as to perform a firing operation in both forward and reverse directions. Therefore, the basic operation is the same in both the forward and reverse directions, and the following description will be made in the forward direction. Forward break The breakover voltage in the opposite direction to the bar voltage can be the same value or different values. In the structure shown in FIG. 7, when a voltage is applied in the forward direction, a breakover is formed at a boundary surface between the semiconductor substrate conductive region 101 and the first N-type conductive region 102.

[0108] Therefore, the influence of the interface charge generated between the insulators 120 and 121 and the semiconductor substrate 200 and the electronic state of the interface trap on the breakover voltage is almost negligible due to the change in the interface charge and the electronic state of the interface trap. The fluctuation of the blocking voltage that occurs is hardly observed. The third N-type conductive regions 140 and 141 usually perform deep diffusion to lower the impurity concentration than the first N-type conductive region 102. In this case, the third N-type conductive regions 140 and 141 surround the first N-type conductive region 102 when viewed from above. As described above, the third N-type conductive regions 140 and 141 have regions of large curvature at the inner peripheral portions 150 and 151 of the third N-type conductive regions 140 and 141 as well as the outer peripheral portions. Will be.

[0109] Therefore, depending on the design, breakover may occur on the inner peripheral side of the third N-type conductive regions 140 and 141, but even in such a case, the influence of the interface charge and the electronic state of the interface trap on the breakover voltage is obtained. Almost no fluctuations in the blocking voltage due to the change of the interface charge and the electronic state of the interface trap are hardly observed.

As described above, according to the structure of the thyristor according to the third embodiment of the present invention, a semiconductor device for overvoltage protection in which the breakover voltage is stable and the blocking voltage hardly varies. A thyristor can be realized.

[0111] A thyristor according to a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 8 is a sectional view showing a thyristor according to the fourth embodiment of the present invention. In FIG. 8, 101 is a semiconductor substrate conductive region, 102 is a first N-type conductive region, 103 is a second N-type conductive region, 104 is a first P-type conductive region, 105 is a second P-type conductive region, and 106 is a first hole. -Shaped conductive region, 107 is the second to L-shaped conductive region, 110 is the first electrode, 111 is the second electrode, 120, 121, 122, 123 is an insulator, 140, 141 is the third N-type conductive region, 142, 143 Denotes a fourth N-type conductive region, and 200 denotes a semiconductor substrate.

As shown in FIG. 8, the thyristor according to the fourth embodiment of the present invention is different from the thyristor according to the third embodiment of the present invention in that the first hole-shaped conductive region 106 and the second hole-shaped Conductive area When there is 107, it is usually called a short emitter structure, but sometimes it is called a short gate structure. The basic operation is the same as the thyristor according to the third embodiment. Here, the first hole-shaped conductive region and the second hole-shaped conductive region may be singular or plural, but usually the shape and arrangement are determined in consideration of the holding current and the surge withstand capability against surge. The basic operation is exactly the same as that of the thyristor according to the third embodiment of the present invention.

Therefore, according to the structure of the thyristor according to the fourth embodiment of the present invention, it is possible to realize a thyristor as a semiconductor device for overvoltage protection in which the break-over voltage is stable and the variation in the blocking voltage is almost zero. Can be done.

As described above based on the embodiment, the first conductivity type semiconductor layer exposed on one surface of the semiconductor substrate is exposed on the one surface and formed in the semiconductor layer. An overvoltage protection semiconductor device having a first conductive region of a second conductivity type opposite to that of the semiconductor layer, wherein the semiconductor device is exposed on the one surface and in the semiconductor layer; A second conductive region of a second conductivity type formed so as to be adjacent to or partially overlap with the periphery of the first conductive region, wherein the breakdown or breakover is performed. If it occurs in the inner peripheral portion of the second conductive region or in the vicinity of the inner peripheral portion or in the vicinity of the first conductive region or the first conductive region, the breakdown voltage or the breakover voltage becomes stable. And there is almost no change in blocking voltage Les, cormorants action can be obtained.

Brief Description of Drawings

FIG. 1 is a sectional view showing a diode according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a diode according to a conventional technique.

FIG. 3 is a cross-sectional view showing a thyristor according to a conventional technique.

FIG. 4 is a graph showing electrical characteristics of a diode according to a conventional technique.

FIG. 5 is a graph showing electrical characteristics of a thyristor according to a conventional technique.

FIG. 6 is a sectional view showing a thyristor according to a second embodiment of the present invention.

FIG. 7 is a sectional view showing a thyristor according to a third embodiment of the present invention.

FIG. 8 is a sectional view showing a thyristor according to a fourth embodiment of the present invention.

FIG. 9 is a plan view showing a diode according to the first embodiment of the present invention. Garden 10] is a cross-sectional view for assisting explanation of mathematical formulas relating to a breakdown voltage stabilizing mechanism.

Explanation of symbols

1 Conductive area of semiconductor substrate

2 1st P type conductive area

3 1st N-type conductive area

9 Interface between first P-type conductive region 2 and semiconductor substrate conductive region 1

10 brother 1 pole

11 2nd electrode

20 Insulator

21 Insulator

23 Insulator

24 Insulator

40 2P type conductive area

41 Second P-type conductive region

50 Inner circumference of 2P-type conductive region

51 Inner circumference of 2P-type conductive region

100 Semiconductor substrate

101 Semiconductor substrate conductive area

102 1st N-type conductive region

103 2nd N-type conductive area

104 1st P type conductive area

105 2nd P conductive area

106 1st hole conductive area

107 Second conductive hole

110 brother 1 pole

111 2nd electrode

120 Insulator 121 insulator

122 insulator

123 insulator

140 3rd N-type conductive region

141 3rd N-type conductive region

142 4th N-type conductive region

143 4th N-type conductive region

150 Inner circumference of 3rd N-type conductive region

151 Inner circumference of 3rd N-type conductive region

190 Interface between first N-type conductive region 102 and semiconductor substrate conductive region 101 200 Semiconductor substrate

Claims

The scope of the claims

[1] A first conductive region of a second conductivity type opposite to the semiconductor substrate formed by being exposed on one surface of a semiconductor substrate of the first conductivity type, and the one surface of the semiconductor substrate A diode having a first conductive type second conductive region formed by being exposed on the other surface opposite to

A third conductive region of the second conductive type which is exposed on the one surface and is formed so as to be adjacent to the first conductive region or to partially overlap a peripheral portion of the first conductive region. Wherein the breakdown occurs in the inner peripheral portion of the third conductive region or in the vicinity of the inner peripheral portion, or in the vicinity of the first conductive region or the first conductive region.

2. The diode according to claim 1, wherein the third conductive region surrounds the first conductive region when the semiconductor substrate is viewed in a plan view.

[3] A first conductive region of a second conductivity type opposite to the semiconductor substrate formed by being exposed on one surface of the semiconductor substrate of the first conductivity type, and exposed on the one surface. A second conductive region of a first conductivity type formed in the first conductive region; and a second conductive region formed by being exposed on the other surface of the semiconductor substrate opposite to the one surface. A thyristor having a third conductive region of the type;

A second conductive type fourth conductive region formed adjacent to the first conductive region or partially overlapping the peripheral portion of the first conductive region; 4. A thyristor, which is generated in an inner peripheral portion of the fourth conductive region, in the vicinity of the inner peripheral portion, or in the vicinity of the first conductive region or the first conductive region.

4. The thyristor according to claim 3, wherein the fourth conductive region surrounds the first conductive region when the semiconductor substrate is viewed in a plan view.

5. The thyristor according to claim 3, wherein the fourth conductive region is exposed on the one surface.

6. The thyristor according to claim 3, wherein a plurality of the second conductive regions are provided.

[7] What is a semiconductor substrate formed by being exposed on one surface of a semiconductor substrate of the first conductivity type? A first conductive region of a second conductive type of an opposite type, a second conductive region of a first conductive type exposed on the one surface and formed in the first conductive region; A third conductive region of the second conductivity type formed by being exposed on the other surface opposite to the one surface; and the third conductive region being exposed on the other surface opposite to the one surface. A thyristor having a first conductive type fifth conductive region formed in the third conductive region, wherein the thyristor is adjacent to the first conductive region or partially overlaps a peripheral portion of the first conductive region. A second conductive type fourth conductive region formed as described above and a second conductive type formed so as to be adjacent to the third conductive region or partially overlap the peripheral portion of the third conductive region. A conductive type sixth conductive region is provided, and a breakover is provided on the inner peripheral portion or the inner peripheral portion of the fourth conductive region. In the vicinity of the first conductive region or the first conductive region, or in the vicinity of the inner periphery of the sixth conductive region or the inner periphery, or in the third conductive region or the third conductive region. A thyristor generated in the vicinity of the conductive region.

[8] The thyristor according to claim 7, wherein the fourth conductive region surrounds the first conductive region when the semiconductor substrate is viewed in a plan view.

9. The thyristor according to claim 7, wherein the sixth conductive region surrounds the third conductive region when the semiconductor substrate is viewed in a plan view.

10. The thyristor according to claim 7, wherein the fourth conductive region is exposed on the one surface.

[11] The thyristor according to any one of claims 7 to 10, wherein the sixth conductive region is exposed on the other surface.

12. The thyristor according to claim 7, wherein a plurality of at least one of the second conductive region and the fifth conductive region is provided.

13. The semiconductor device according to claim 3, further comprising: a seventh conductive region of a second conductivity type that is exposed on the one surface and penetrates the second conductive region. The thyristor according to item 12 or ずれ.

14. The thyristor according to claim 13, wherein a plurality of said seventh conductive regions are provided.

[15] The semiconductor device is exposed on the other surface opposite to the one surface and penetrates the fifth conductive region. The thyristor according to any one of claims 7 to 14, further comprising an eighth conductive region of the second conductivity type formed so as to be formed.

The thyristor according to claim 15, wherein a plurality of the eighth conductive regions are provided.