WO2005109256A3 - Methos and apparatus for designing integrated circuit layouts - Google Patents

Methos and apparatus for designing integrated circuit layouts Download PDF

Info

Publication number
WO2005109256A3
WO2005109256A3 PCT/US2005/014983 US2005014983W WO2005109256A3 WO 2005109256 A3 WO2005109256 A3 WO 2005109256A3 US 2005014983 W US2005014983 W US 2005014983W WO 2005109256 A3 WO2005109256 A3 WO 2005109256A3
Authority
WO
WIPO (PCT)
Prior art keywords
layout
environment
feature
model
methos
Prior art date
Application number
PCT/US2005/014983
Other languages
French (fr)
Other versions
WO2005109256A2 (en
Inventor
Louis K Scheffer
Original Assignee
Cadence Design Systems Inc
Louis K Scheffer
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/836,582 external-priority patent/US7254798B2/en
Priority claimed from US10/836,581 external-priority patent/US7082588B2/en
Application filed by Cadence Design Systems Inc, Louis K Scheffer filed Critical Cadence Design Systems Inc
Priority to EP05740554A priority Critical patent/EP1759322A4/en
Priority to JP2007511456A priority patent/JP5147391B2/en
Publication of WO2005109256A2 publication Critical patent/WO2005109256A2/en
Publication of WO2005109256A3 publication Critical patent/WO2005109256A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes

Abstract

A method for modifying an IC layout using a library of pretabulated models, each model containing an environment with a feature, one or more geometries, and a modification to the feature that is calculated to produce a satisfactory feature on a wafer. The model may also contain a simulation of the environment reflecting no processing variations and/or a re-simulation of the environment reflecting one or more processing variations. The model may also contain data describing an electrical characteristic of the environment as a function of one or more process variations and/or data describing an adjustment equation that uses geometry coverage percentages of particular areas in the layout to determine an adjustment to the modification. In some embodiments, an upper layout for an upper of an IC are modified using information (such a density map) relating to a lower layout for a lower layer of the IC.
PCT/US2005/014983 2004-05-01 2005-04-29 Methos and apparatus for designing integrated circuit layouts WO2005109256A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP05740554A EP1759322A4 (en) 2004-05-01 2005-04-29 Methos and apparatus for designing integrated circuit layouts
JP2007511456A JP5147391B2 (en) 2004-05-01 2005-04-29 Method and apparatus for designing an integrated circuit layout

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US10/836,582 2004-05-01
US10/836,582 US7254798B2 (en) 2004-05-01 2004-05-01 Method and apparatus for designing integrated circuit layouts
US10/836,581 2004-05-01
US10/836,581 US7082588B2 (en) 2004-05-01 2004-05-01 Method and apparatus for designing integrated circuit layouts

Publications (2)

Publication Number Publication Date
WO2005109256A2 WO2005109256A2 (en) 2005-11-17
WO2005109256A3 true WO2005109256A3 (en) 2006-05-04

Family

ID=35320879

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/US2005/014983 WO2005109256A2 (en) 2004-05-01 2005-04-29 Methos and apparatus for designing integrated circuit layouts
PCT/US2005/015024 WO2005109257A2 (en) 2004-05-01 2005-04-29 Method and apparatus for designing integrated circuit layouts

Family Applications After (1)

Application Number Title Priority Date Filing Date
PCT/US2005/015024 WO2005109257A2 (en) 2004-05-01 2005-04-29 Method and apparatus for designing integrated circuit layouts

Country Status (3)

Country Link
EP (2) EP1759321A4 (en)
JP (2) JP5147391B2 (en)
WO (2) WO2005109256A2 (en)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7011600B2 (en) 2003-02-28 2006-03-14 Fallbrook Technologies Inc. Continuously variable transmission
US7448012B1 (en) 2004-04-21 2008-11-04 Qi-De Qian Methods and system for improving integrated circuit layout
EP1759321A4 (en) * 2004-05-01 2009-10-28 Cadence Design Systems Inc Method and apparatus for designing integrated circuit layouts
JP4974896B2 (en) 2004-10-05 2012-07-11 フォールブルック テクノロジーズ インコーポレイテッド Continuously variable transmission
EP1945490B1 (en) 2005-10-28 2018-12-05 Fallbrook Intellectual Property Company LLC Electromotive drives
EP1954959B1 (en) 2005-11-22 2013-05-15 Fallbrook Intellectual Property Company LLC Continuously variable transmission
CA2930483C (en) 2005-12-09 2017-11-07 Fallbrook Intellectual Property Company Llc Continuously variable transmission
EP1811202A1 (en) 2005-12-30 2007-07-25 Fallbrook Technologies, Inc. A continuously variable gear transmission
CN102269056B (en) 2006-06-26 2013-10-23 福博科技术公司 Continuously variable transmission
WO2008057507A1 (en) 2006-11-08 2008-05-15 Fallbrook Technologies Inc. Clamping force generator
US8738255B2 (en) 2007-02-01 2014-05-27 Fallbrook Intellectual Property Company Llc Systems and methods for control of transmission and/or prime mover
CN104121345B (en) 2007-02-12 2017-01-11 福博科知识产权有限责任公司 Continuously variable transmission and method therefor
CN103438207B (en) 2007-02-16 2016-08-31 福博科技术公司 Unlimited speed changing type buncher, buncher and method, assembly, sub-component and parts
CN105626801B (en) 2007-04-24 2019-05-28 福博科知识产权有限责任公司 Electric traction drives
US8641577B2 (en) 2007-06-11 2014-02-04 Fallbrook Intellectual Property Company Llc Continuously variable transmission
CA2692476C (en) 2007-07-05 2017-11-21 Fallbrook Technologies Inc. Continuously variable transmission
US8996263B2 (en) 2007-11-16 2015-03-31 Fallbrook Intellectual Property Company Llc Controller for variable transmission
WO2009085773A1 (en) 2007-12-21 2009-07-09 Fallbrook Technologies Inc. Automatic transmissions and methods therefor
US7861196B2 (en) 2008-01-31 2010-12-28 Cadence Design Systems, Inc. System and method for multi-exposure pattern decomposition
US8317651B2 (en) 2008-05-07 2012-11-27 Fallbrook Intellectual Property Company Llc Assemblies and methods for clamping force generation
EP2304272B1 (en) 2008-06-23 2017-03-08 Fallbrook Intellectual Property Company LLC Continuously variable transmission
WO2010017242A1 (en) 2008-08-05 2010-02-11 Fallbrook Technologies Inc. Methods for control of transmission and prime mover
US8069423B2 (en) 2008-08-11 2011-11-29 Cadence Design Systems, Inc. System and method for model based multi-patterning optimization
US8469856B2 (en) 2008-08-26 2013-06-25 Fallbrook Intellectual Property Company Llc Continuously variable transmission
US8167759B2 (en) 2008-10-14 2012-05-01 Fallbrook Technologies Inc. Continuously variable transmission
US8209656B1 (en) 2008-10-14 2012-06-26 Cadence Design Systems, Inc. Pattern decomposition method
CA2756273C (en) 2009-04-16 2017-06-27 Fallbrook Technologies Inc. Stator assembly and shifting mechanism for a continuously variable transmission
US8512195B2 (en) 2010-03-03 2013-08-20 Fallbrook Intellectual Property Company Llc Infinitely variable transmissions, continuously variable transmissions, methods, assemblies, subassemblies, and components therefor
US8888643B2 (en) 2010-11-10 2014-11-18 Fallbrook Intellectual Property Company Llc Continuously variable transmission
WO2012138610A1 (en) 2011-04-04 2012-10-11 Fallbrook Intellectual Property Company Llc Auxiliary power unit having a continuously variable transmission
US8386974B2 (en) 2011-04-14 2013-02-26 Synopsys, Inc. Accelerating coverage convergence using symbolic properties
US8443316B1 (en) 2011-11-09 2013-05-14 Synopsys, Inc. Accelerating coverage convergence and debug using symbolic properties and local multi-path analysis
US10047861B2 (en) 2016-01-15 2018-08-14 Fallbrook Intellectual Property Company Llc Systems and methods for controlling rollback in continuously variable transmissions
US10023266B2 (en) 2016-05-11 2018-07-17 Fallbrook Intellectual Property Company Llc Systems and methods for automatic configuration and automatic calibration of continuously variable transmissions and bicycles having continuously variable transmissions
US11215268B2 (en) 2018-11-06 2022-01-04 Fallbrook Intellectual Property Company Llc Continuously variable transmissions, synchronous shifting, twin countershafts and methods for control of same
US11174922B2 (en) 2019-02-26 2021-11-16 Fallbrook Intellectual Property Company Llc Reversible variable drives and systems and methods for control in forward and reverse directions
US11501052B1 (en) 2021-05-27 2022-11-15 Taiwan Semiconductor Manufacturing Company, Ltd Conductor scheme selection and track planning for mixed-diagonal-Manhattan routing

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6578190B2 (en) * 2001-01-11 2003-06-10 International Business Machines Corporation Process window based optical proximity correction of lithographic images

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0844038A (en) * 1994-08-03 1996-02-16 Matsushita Electron Corp Master mask forming device and production of semiconductor device
US5587923A (en) * 1994-09-07 1996-12-24 Lsi Logic Corporation Method for estimating routability and congestion in a cell placement for integrated circuit chip
US5723233A (en) * 1996-02-27 1998-03-03 Lsi Logic Corporation Optical proximity correction method and apparatus
JP2950280B2 (en) * 1997-03-31 1999-09-20 日本電気株式会社 Electron beam drawing method
JP3241010B2 (en) * 1998-11-18 2001-12-25 日本電気株式会社 Optical proximity correction method for semiconductor manufacturing process
JP2002148779A (en) * 2000-11-07 2002-05-22 Toshiba Corp Mask pattern correcting method, photomask, and computer-readable recording medium stored with mask pattern correcting program
US6574782B1 (en) * 2000-11-15 2003-06-03 International Business Machines Corporation Decoupled capacitance calculator for orthogonal wiring patterns
JP4187947B2 (en) * 2001-04-26 2008-11-26 株式会社東芝 PATTERN CORRECTION METHOD, PATTERN CORRECTION DEVICE, AND RECORDING MEDIUM CONTAINING PATTERN CORRECTION PROGRAM
JP3609810B2 (en) * 2002-09-18 2005-01-12 株式会社東芝 Mask pattern creating method and semiconductor device manufacturing method
JP4592240B2 (en) * 2001-09-29 2010-12-01 株式会社東芝 Mask pattern creating method and semiconductor device manufacturing method
JP3686367B2 (en) * 2001-11-15 2005-08-24 株式会社ルネサステクノロジ Pattern forming method and semiconductor device manufacturing method
JP3615182B2 (en) * 2001-11-26 2005-01-26 株式会社東芝 Optical proximity effect correction method and optical proximity effect correction system
US7363099B2 (en) * 2002-06-07 2008-04-22 Cadence Design Systems, Inc. Integrated circuit metrology
JP2004037827A (en) * 2002-07-03 2004-02-05 Sony Corp Method for verifying design pattern and method for correcting design pattern
US6893800B2 (en) * 2002-09-24 2005-05-17 Agere Systems, Inc. Substrate topography compensation at mask design: 3D OPC topography anchored
JP2004046880A (en) * 2003-07-18 2004-02-12 Matsushita Electric Ind Co Ltd Apparatus for extracting circuit parameter
EP1759321A4 (en) * 2004-05-01 2009-10-28 Cadence Design Systems Inc Method and apparatus for designing integrated circuit layouts

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6578190B2 (en) * 2001-01-11 2003-06-10 International Business Machines Corporation Process window based optical proximity correction of lithographic images

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1759322A4 *

Also Published As

Publication number Publication date
JP2007535715A (en) 2007-12-06
WO2005109257A3 (en) 2005-12-15
EP1759322A4 (en) 2008-03-12
WO2005109256A2 (en) 2005-11-17
WO2005109257A2 (en) 2005-11-17
EP1759321A2 (en) 2007-03-07
JP2007538272A (en) 2007-12-27
EP1759322A2 (en) 2007-03-07
JP5147391B2 (en) 2013-02-20
EP1759321A4 (en) 2009-10-28

Similar Documents

Publication Publication Date Title
WO2005109256A3 (en) Methos and apparatus for designing integrated circuit layouts
WO2001042964A3 (en) Method and apparatus for structure prediction based on model curvature
US6775818B2 (en) Device parameter and gate performance simulation based on wafer image prediction
JP4980684B2 (en) Substrate information acquisition conversion method and program and apparatus thereof
WO2005008747A3 (en) Methods and systems for inspection of wafers and reticles using designer intent data
WO2007044630A3 (en) Method and manufacture of multiple photomask patterns and computer readable medium
TW200632708A (en) System for designing integrated circuits with enhanced manufacturability
WO2002000343A3 (en) A microfluidic design automation method and system
TW200609782A (en) Physical design system and method
WO2008048730A3 (en) Interactive hierarchical analog layout synthesis for integrated circuits
WO2007006037A3 (en) Placement methods for standard cell library
US20060218514A1 (en) Power supply analysis method and program product for executing the same
JP2011113291A (en) Method for simulating operation of semiconductor device, method for-acquiring measured data and circuit designing method
DE60323249D1 (en) IRREGULAR BRAIDED AND EMBEDDED GEOMETRIC DESCRIPTION IN A COMPUTER GRAPHIC SYSTEM
US20180173838A1 (en) Integrated circuit, and computing system and computer-implemented method for designing integrated circuit
JP2004234618A (en) Semiconductor device model, and forming method and device thereof
US20050132315A1 (en) Extendable method for revising patterned microelectronic conductor layer layouts
Steinecke et al. EMI modeling and simulation in the IC design process
CN101866829A (en) Method for intellectual property protection for parameterized units of integrated circuit
CN107039254B (en) Implantation structure for area reduction
US7475373B2 (en) Method and apparatus to visually assist legalized placement with non-uniform placement rules
Donze et al. Masterimage approach to VLSI design
WO2003036523A1 (en) Simulation method, simulation program, and display method
Llamas et al. Development of digital application specific printed electronics circuits: from specification to final prototypes
US9846758B2 (en) Method of designing an integrated circuit and computer program product

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2007511456

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

WWW Wipo information: withdrawn in national office

Country of ref document: DE

WWE Wipo information: entry into national phase

Ref document number: 2005740554

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 2005740554

Country of ref document: EP