JP5147391B2 - Method and apparatus for designing an integrated circuit layout - Google Patents

Abstract

A method for modifying an upper layout for an upper layer of an IC using information of a lower layout for a lower layer of the IC, the method including (2205) receiving the upper layout containing features and modifications to features, (2215) producing a density map of the lower layout having geometry coverages of sub-regions of the lower layout, (2220) selecting a feature in the upper layout, (2225) retrieving, from the density map, the geometry coverage of a sub-region below the feature, (2230) determining a vertical deviation of the feature using the geometry coverage, (2235) determining an alteration to the modification using the vertical deviation, (2240) applying the alteration to the modification and (2245) repeating for all features.

Description

  The present invention relates to a method and apparatus for designing an integrated circuit layout.

  An integrated circuit (IC) is a device (eg, a semiconductor device) that includes many electronic components such as transistors, resistors, diodes, and the like. These components are often interconnected to form a plurality of circuit components such as gates, cells, memory devices, arithmetic units, controllers, decoders, and the like. An IC includes multiple layers of wiring that interconnect its electronic and circuit components. Traditionally, ICs use a preferred direction (PD) wiring model that specifies a preferred wiring direction for each of its wiring layers. In the priority direction wiring model, the priority direction is generally alternated between successive wiring layers.

  An example of the PD wiring model is a PD Manhattan wiring model that designates layers in which the priority direction horizontal and vertical wirings alternate. Another example of the PD wiring model is a PD diagonal wiring model that designates a layer in which the priority direction diagonal wiring is replaced. The PD diagonal wiring model can take into account a shorter wiring distance than the PD Manhattan wiring model, and can reduce the total wire length required for the interconnection of IC electronics and circuit components.

  A design engineer designs an IC by transforming the logic or circuit description of the IC into a geometric description called a layout. To create a layout, a design engineer typically uses an electronic design automation (EDA) application. These applications provide a set of computer-based tools for creating, editing, and analyzing IC design layouts. The IC layout includes a geometric representation of the IC elements that will be fabricated on the wafer, such as IC components, interconnect lines, via pads, and the like. Thus, an IC layout generally includes (1) a circuit module having pins (ie, a geometrical representation of an electronic or circuit IC component), and (2) an interconnect that connects the pins of a circuit module on the same layer. Includes several geometric shapes such as lines (ie, a geometric representation of the wiring) and (3) vias that connect the pins of the circuit module across different layers (ie, a geometric representation of the non-planar wiring) .

  In order to produce an IC after the IC layout design is completed, a printing plate (photomask) is created based on the IC layout, for which purpose the photomask includes various geometric shapes of the IC layout. The various geometries contained on the photomask represent IC elements (such as IC components, interconnect lines, via pads, etc.) created on the wafer with a specific circuit pattern, and the wafer is an integrated circuit Forming the base of Overlying the wafer will typically be a protective insulating layer and a light sensitive photoresist layer. A light source and lens are used to focus the light through the photomask onto the photoresist layer of the wafer so that selected areas of the photoresist layer are modified (typically weakened or enhanced). In doing this, the circuit pattern represented on the photomask is “engraved” on the photoresist layer of the wafer. The modified area of the photoresist layer (as well as the underlying insulating layer) is then etched away to produce the desired circuit pattern of IC elements. Through multiple stages of design, photomasking (illumination), and etching, multiple layers of the IC are created.

  However, in general, the geometry originally designed in the IC layout (and replicated on the photomask) and the resulting fabrication geometry actually generated on the wafer through photomasking and etching processes There is considerable discrepancy in shape. The discrepancy between the geometry designed in the layout and the resulting fabricated geometry is mainly due to the fact that recently the geometry dimensions are smaller than the wavelength of light used in photomask processing, so the geometry This is due to the problem of accurate reproduction of dimensions. In response, various optical methods, such as “Resolution Enhancement Technology (RET)”, have been developed to reduce the geometric dimensions at a size smaller than the wavelength of light used in photomask processing. Accurate playback is possible. However, even if “resolution enhancement technology” is used for IC fabrication, the geometry actually fabricated on the wafer will resemble the geometry initially designed for the IC layout (within a predetermined tolerance threshold). There is no guarantee.

  The discrepancy between the geometry designed for the layout and the resulting fabrication geometry is also caused by diffracted light that strikes the geometry from the surrounding geometry, which is a photo of the surrounding geometry. It is diffracted from the surrounding geometric shape at the time of mask processing. This diffracted light can cause distortions or inaccuracies in the appearance of the geometry with which it comes into contact. Therefore, there is some degree of unpredictability in the production of geometric shapes on the wafer, regardless of whether RET is used.

  FIG. 1 shows the case where it occurs between the initial geometry 105 when designed in an IC layout (and replicated on a photomask) and the fabrication geometry 120 actually generated on the wafer. There are examples of changes. In the example of FIG. 1, the initial geometric shape 105 has five related forms indicated by points: four corner forms and one line-point form 112. As shown in FIG. 1, the fabrication geometry 120 has four rounded corners 125 and curved segments 127. In general, for IC fabrication, the geometry 120 corner 125 generated on the wafer will have significant errors (ie, it will be substantially different from the corner 110 of the original geometry 105). ). In addition, the line segments of the fabricated geometric shape 120 also have a considerable error, and as shown in the example of FIG.

  Conventionally, the geometry in the IC layout is modified (and replicated on a photomask) to adjust the error in the resulting geometry created on the wafer. FIG. 2 shows an example of a correction (corrected shape) 230 placed on the initial geometric shape 105 and a production geometric shape 235 actually generated on the wafer. As shown in FIG. 2, the modification 230 is placed on the corner configuration 110 of the initial geometry 105, which produces a less rounded corner 240 on the fabricated geometry 235. The correction 230 is also placed in the line-point form 112 of the initial geometry 105, which produces a line segment 242 with less curves in the created geometry 235. The generated geometry 235 generated using the modification 230 is more similar in appearance to the initial geometry 105, but still there is some discrepancy between the generated geometry 235 and the initial geometry 105. Please note that there is. In general, modifications are made to the initial geometry, producing only satisfactory resulting geometric shapes that are within an acceptable threshold of variance from the initial geometry.

  Currently, there are two ways to create a modification to the first geometric shape of a layout. One of them is a simulation-based method in which an initial correction is made to the first geometric shape of the layout and a simulation simulation is performed on the first geometric shape to generate a simulated geometric shape. The simulated geometry is used to determine if the initial geometry modification is satisfactory. If the initial geometric shape modification does not yield a satisfactory simulated geometric shape, the correction is adjusted (eg, scaled up or down) to generate another simulated geometric shape. This process is repeated until a satisfactory simulated geometric shape is generated. However, simulation-based techniques require that all geometric shapes in the layout be repeatedly simulated until a satisfactory geometric shape is generated. Considering that there can be billions of such geometries on a layout, this approach can be very time consuming.

The second method is a rule-based method in which correction rules are generally created by IC designers themselves. Such rules define what modifications should be made to the geometry in different situations. The rule-based approach takes less time than the simulation-based approach, but a number of rules must be created to cover the various situations that are likely to occur in the IC layout. Also, each modification rule can be complex and cumbersome to create and apply.
Thus, there is a need for a simple and efficient method of determining modifications to a geometry in a layout that is calculated to produce a satisfactory geometry when fabricated on a wafer.

  Some embodiments of the present invention modify a form in an IC layout using a library of pre-tabulated models that includes modifications to the form that each model calculates to produce a satisfactory form on the wafer. Provide a method. Each model also includes a morphological environment that includes the geometric shape in which the morphology is located and zero or more adjacent geometric shapes. In some embodiments, a method for modifying a form in an IC layout includes 1) selecting a form in the layout for modification, 2) identifying an environment that includes the form, and 3) matching the environment. Identifying a model in a pre-tabulated library to include, 4) retrieving a modification to the form from the conforming model, and 5) applying the modification to the form in the layout. In some embodiments, the fitting model also includes simulated environment data, re-simulated environment data, electrical property data, and / or other data such as accommodation equations or function data. In these embodiments, the method retrieves (at stage 4) any or all of the other types of data included in the fit model.

  In some embodiments, the method of building a library of pre-tabulated models is 1) a set of exemplary pre-tabulated environments where each environment includes a form and one or more geometric shapes. 2) selecting the current environment in the set, 3) creating and applying a modification to the current form in the current environment, 4) simulating the current environment with the modification, 5 ) Repeat steps 3 and 4 until a satisfactory simulation of the current environment and current form is achieved, 6) Current by storing data of the current environment (last modified) in the model And 7) repeating steps 2 through 6 until all environments in the set have been processed. In some embodiments, the set of environments in the library is tailored to have a layout with specific preferred direction wiring, such as Manhattan or diagonal preferred direction wiring. In some embodiments, the set of environments in the library is tailored to be a layout that does not have a specific preferred direction wiring, such as an analog designed layout.

  Some embodiments of the present invention provide an alternative method of modifying a shape in an IC layout using a library of pre-tabulated models, which includes 1) layout for modification Selecting a form within, 2) identifying a layout environment containing the form, 3) determining whether a model in the library contains a matching environment, 4) if included, from the conforming model to the form Searching for and applying corrections, 5) if not, determining if the model in the library includes an environment within a given distribution from the layout environment, 6) if included, “fit” Searching for and applying modifications to the form from the model, and 7) if not, creating and storing a new fit model in the library for the layout environment. In some embodiments, rather than performing steps 5-7, the method uses conventional rule-based techniques to determine modifications to features in the layout when no matching model is found in the library. . In some embodiments, the method does not create a pre-prepared library, but rather creates a library at the same time while modifying the form in the layout, i.e., used to modify the layout. When creating a pre-tabulated library "on the fly" during execution time is executed.

  In some embodiments, the model in the pre-tabulation library is pre-tabulation environment data describing a pre-tabulation environment that includes morphology, one or more geometric shapes, and modifications to the morphology. To accommodate. In some embodiments, the model also provides simulated environment data that describes the simulated environment, which is a prediction of how the pre-tabulated environment will appear when fabricated on the wafer assuming there are no process variations. Accommodate. In some embodiments, the model also describes a re-simulation environment that is a prediction of how the pre-tabulation environment will appear when fabricated on the wafer assuming one or more process variations. Accommodates resimulated environment data.

  Some embodiments provide an alternative library construction method for building a pre-tabulated library of models where each model contains simulated environment data and / or re-simulated environment data. In these embodiments, the library construction method includes 1) creating a set of exemplary pre-tabulated environments, each containing a form, 2) selecting a current environment within the set, and 3) satisfactory. The stage of determining the modification to the form in the current environment that generates the simulated environment 4) The stage of creating the model of the current environment by storing the data of the current environment in the model 5) The simulated environment satisfying the model 6) storing simulated environment data that describes, 6) generating a re-simulated environment of the current environment that reflects one or more process variations, 7) re-simulating the model to re-simulate the environment Storing environment data, and 8) repeating steps 2 through 7 until all environments in the set have been processed.

In some embodiments, the model also contains electrical property data that describes electrical properties (such as capacitance, inductance, or resistance) of the pre-tabulation environment. In some embodiments, each model is a function of the size and placement of one or more geometric shapes in the pre-tabulation environment and / or a function of one or more process variations. As a characteristic equation representing the electrical characteristics of the pre-tabulation environment.
Some embodiments provide an alternative library construction method for constructing a library containing capacitance equations, the method comprising: 1) a set of exemplary pre-forms each including a pair of adjacent geometric shapes The stage of creating a tabulation environment, 2) the stage of selecting the current environment in the set, 3) the stage of generating the initial environment by simulating the current environment, 4) the 3D (3D) electromagnetic simulation as the initial environment To find the initial capacitance (C ₀ ) between pairs of adjacent geometries, 5) re-simulate the current environment to take into account exemplary values of one or more process variations Generating a modified environment, 6) determining a distance difference (ΔW) between a pair of adjacent geometric shapes in the modified environment and the initial environment, and 7) converting the 3D simulation to the modified environment. Go Finding a capacitance value (C) between a pair of adjacent geometric shapes; 8) a capacitance value (C), a distance difference (ΔW), and an exemplary value of one or more process variations. Storing as an example result, 9) repeating steps 5 to 8 a predetermined number of times to generate a set of example results, 10) a capacitance equation that considers all example results in the set 11) storing the capacitance equation in a model for the current environment, and 12) repeating steps 2 through 11 until all environments in the set have been processed.

  In some embodiments, the model also adjusts to describe an adjustment equation or function that uses at least one geometric range percentage of a particular area of the design layout to determine adjustments to pre-tabulation modifications in the model. Contains equation or function data. Some embodiments provide an adjustment method that uses a library of pre-tabulated models with a predetermined adjustment equation or function to modify the geometry in the IC layout. For each form of layout, the method includes 1) identifying the current environment containing the form, 2) identifying the model in the library containing the conforming environment, 3) modifying the form; A predetermined adjustment equation used to adjust the correction, including one or more predetermined coefficients and one or more variables that are the geometric range percentage of a particular area in the layout 4) determining the geometric range percentage of the area specified in the adjustment equation, 5) determining adjustments to be made to the correction using the adjustment equation, 6) And) 7) applying the adjusted correction to the form.

  Some embodiments provide a library construction method for generating a library containing a predetermined adjustment equation or function. For each pre-tabulation environment within a set of pre-tabulation environments (including initial modifications to the form), the method 1) one or more exemplary geometries of a particular region surrounding the form A stage in which a simulation considering the geometric shape range values is performed on the environment, 2) a stage in which the initial correction is adjusted, 3) a stage in which steps 1 and 2 are repeated until a satisfactory simulation is generated, and 4) the initial correction Determining the total adjustment made to the 5) storing the total adjustment value and one or more geometric range values as exemplary results, 6) a set of exemplary Repeat steps 1 to 5 a predetermined number of times to generate results, 7) consider all exemplary results in the set and have a total adjustment value of one or more geometric shapes A key to explain how the value is derived from the range value Step determines equations, and 8) includes the step of storing the adjusted equation model for the environment.

  In some embodiments, the geometry in the top layout for the top layer of the IC is modified using information related to the bottom layout for the bottom layer of the IC. In some embodiments, the geometry in the top layout is modified using the density map of the bottom layout. In some embodiments, the geometry in the layout for an IC layer is modified based on layout / layer relief data (vertical deviation data).

Some embodiments provide a method for modifying a layout for an upper layer of an IC using information related to the layout for the lower layer of the IC. The method includes 1) receiving an upper layout for the upper layer of the IC, including features and modifications to the feature, 2) retrieving data for the lower layout for the lower layer of the IC, 3) in a sub-region of the lower layout Generating a density map of the lower layout showing the percentage of the geometric range, 4) selecting a current form (with modifications) in the upper layout, 5) a sub-layout of the lower layout below the current form Retrieving a percentage of the geometric shape range of the region from the density map, 6) determining an estimate of the vertical deviation of the current form based on the percentage of the geometric form range, and 7) present form based on the vertical deviation. Determining the change to the modification of the current, 8) applying the change to the modification of the current form, and 9) stage 4 until all forms of the upper layer have been processed. Including the step of repeating steps 8.
The novel features of the invention are set forth in the appended claims. However, for purposes of explanation, some embodiments of the invention are shown in the accompanying drawings.

Many details are set forth below for purposes of explanation. However, those skilled in the art will recognize that the invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order not to obscure the description of the present invention with unnecessary detail.
The following description is divided into six sections. General integrated circuit layout design methods and general terms and concepts are described below in Section I. Next, Section II uses a library of pre-tabulated models that describe the environment (a sub-region of the IC layout) and the modifications that apply to the geometry or form of the environment, and then the geometry in the IC layout. A method of correcting the shape will be described. Section III describes an alternative method of modifying geometry in an IC layout using a library of pre-tabulated models. Section IV describes other data that can be included in the model in the library, such as simulation data or electrical data of the environment described in the model. Section V describes how to modify a geometric shape in an IC layout using a library of pre-tabulated models along with methods based on equations or functions. Section VI describes how to modify the geometry in a layout for an IC layer using information related to the layout for another IC layer.

Section I: General Design Methods, Terminology, Concepts FIG. 3 is a flow diagram of a general design method 300 for designing an integrated circuit layout. The method 300 can be implemented, for example, by an electronic design automation (EDA) application that creates, edits, or analyzes an integrated circuit design layout. The general design method 300 begins (at 305) when an initial design layout is received that includes a plurality of geometries each having zero or more features. The initial design layout is typically designed by a design engineer.

  Next, modifications to the geometric shapes and forms in the layout are determined and applied to the design layout to generate a modified layout (at 310). In some embodiments, layout corrections are determined using a library of pre-tabulated models, each containing corrections applied to the geometry or form in the layout (as described in Section II). The library of models is pre-tabulated to generate a layout that results in a satisfactory layout, i.e., a modified layout that looks from the first layout (received at 305) to a simulated layout that is within a predetermined variance threshold.

  Note that the following steps 315 to 330 of method 300 are completely optional. Next, a simulated layout of the modified layout is generated using the simulator program (at 315). The purpose of using the simulated layout is to confirm that a satisfactory simulated layout is generated by the modified layout. The simulated layout predicts what the modified layout will look like when it is fabricated on a wafer, and assumes that there is no process variation (ie, assumes a “normal” process state). Generated by. In some embodiments, when generating the simulated layout, the simulator program may be able to use the characteristics of the photoresist layer, the effects of the optics of the exposure machine, the characteristics of the light source, and the characteristics of the etcher used in the photomask process. Consider various factors.

  Next, in this method, it is determined whether or not the simulated layout is satisfactory, that is, whether or not it is within a predetermined dispersion threshold range from the first layout (received at 305). If it is not within range, an error has occurred when the modified layout is generated using a pre-tabulated library of models designed to generate a satisfactory simulated layout. If a satisfactory simulated layout is generated by the modified layout, the method proceeds to step 330. The modified layout that produced a satisfactory simulated layout can then be used to construct a photomask that includes various geometric shapes and modifications of the modified layout.

  At step 330, the method generates a re-simulated layout of the modified layout using a simulator program that takes into account one or more process variations (ie, variations that occur during IC fabrication). In some embodiments, in generating the re-simulation layout, the simulator program may add the same factors (ie, photoresist layer) as in step 315, in addition to one or more specific process variations. Characteristics, influence of optical equipment of the exposure machine used in photomask processing, characteristics of light source, characteristics of etching machine used in photomask processing, etc.).

  In addition, the re-simulation layout predicts how the corrected layout will appear in the state of being produced on the wafer. It is generated by a simulator program that assumes one or more processing variations. Thus, compared to the simulated layout (generated at 315), the re-simulated layout reflects one or more processing variations and appears to be significantly different from the simulated layout. For example, the geometric shape in the re-simulated layout may be thinner, thicker, or a different shape than the geometric shape in the simulated layout.

In some embodiments, how a re-simulated layout is created with a specific value (e.g., lens focus variation with a defocus value of +10 nm) taken into account for a modified layout. Predict whether it will appear. In some embodiments, one or more re-simulated layouts are generated (at 330). Thus, the general design method 300 ends.
Note that the re-simulated layout (generated at 330) generally makes a very accurate prediction as to how the modified layout will actually appear when made. Thus, the design engineer can use the re-simulated layout to determine whether another correction should be made to the corrected layout. Furthermore, when the resimulated layout is input to various layout analysis programs, for example, the electrical characteristics of the modified layout can be calculated. However, such a program may require a significant amount of time to reproduce the re-simulation performed at step 330.

  In some embodiments, as described in Section IV, the models in the pre-tabulated library are the simulated results of stage 315 and / or the re-simulated results of stage 330 (including specific values for specific process variations). Contains data describing By storing the simulation results of step 315 and / or the re-simulation results of step 330, these simulation results do not need to be replayed, thus saving processing time. This can make the processing time practical for applications that were not practical before (repeated viewing by the designer).

  An IC design layout (received at 305) generally includes (1) a circuit module having pins (ie, a geometrical representation of an electronic or circuit IC component), and (2) a circuit module pin on the same layer. Several geometries, such as interconnect lines to connect (ie, a geometric representation of wiring), and (3) vias that connect the pins of circuit modules across different layers (ie, a geometric representation of non-planar wiring) The academic shape will be included. Vias include (1) one pad in each of the two layers traversed by the wiring, and (2) a cut that is a three-dimensional hole between the two layers. Via pads have a specific shape when viewed from above and can include geometric shapes on the layers of the IC.

  FIG. 4 shows a top view of a sub-region 405 of a layout that includes a geometry that can represent various IC elements such as circuit modules, interconnect lines, or via pads that will be fabricated on the wafer. Yes. The geometric shape 410 includes a corner (that is, a point where two sides of the geometric shape intersect and form an angle of 90 degrees), and a bent portion (that is, a point where the two sides of the geometric shape intersect and form an angle other than 90 degrees). ), Or a form 415 (indicated by a point) such as a point on the side of the geometric shape 410 (ie, a line-point form). As used herein, a geometric shape including the shape currently being processed by the method of the present invention is referred to as the primary geometric shape. A geometric shape adjacent to the main geometric shape is called an adjacent geometric shape.

  FIG. 5 shows a top view of a sub-region 505 of the layout of the main geometry 512 that includes the current form 515 and the environment 520 surrounding form 515. Also, various adjacent geometric shapes 510 are shown around the current form 515. The environment 520 is a sub-region of the layout having a predetermined size, including the current form 515, some or all of the primary geometric shape 512 in which the current form is located, and zero or more adjacent geometries. Including part or all of the shape 510. In the example shown in FIG. 5, the shape of the environment 520 is a four-sided polygon. However, in other embodiments, the environment 520 has another geometric shape, such as a circle or an octagon. In some embodiments, the environment 520 is a square with the current form 515 centered.

  FIG. 6 is a conceptual diagram of a model 600 stored in a model pre-tabulation library that includes descriptive data of a pre-tabulation environment 605 that is compatible with the layout environment 520 of FIG. The pre-tabulation environment 605 has a predetermined size. In some embodiments, the model has dimensions that describe the environment surrounding the form, modifications to the form, the primary geometric shape in which the form is located, and zero or more geometric shapes that are included in the environment. And placement data. In some embodiments, the descriptive data includes coordinate values of morphology, modification, primary geometric shape, and zero or more neighboring geometric shapes, where the coordinate value is of the shape in the environment. The position (eg, the form is located in the center of the environment and has x, y coordinate values of 0, 0). In the example shown in FIG. 6, the environment 605 described by the model 600 includes a current form 610, a modification 615 to the current form 610, a main geometric shape 612, and one adjacent geometric shape 614.

  In some embodiments, the processing of the form in the IC layout determines the layout environment surrounding the form, finds a model with a conforming pre-tabulation environment in the pre-tabulation library, and identifies the modifications contained in the model in the layout environment. It is applied to the form in For example, the processing of form 515 in FIG. 5 determines the layout environment 520 surrounding form 515, finds model 600 (of FIG. 6) with pre-tabulation environment 605 that matches layout environment 520, and is included in model 600. The modified 615 is applied to the form 515 of the layout environment 520.

  In some embodiments, after processing the form 515 in the layout, the processing area 530 around the form 515 located in the center of the processing area 530 is identified. Processing area 530 indicates that the modification made to form 515 is sufficient for processing area 530 and that other forms of processing in processing area 530 are not required. The processing area 530 may be larger or smaller than the environment 520 surrounding the form 515. The processing area 530 can be used to facilitate selection of other forms for processing (as described below in connection with FIG. 7).

  Note that the determination of the dimensions and placement of modifications that produce a satisfactory shape on the wafer is primarily based on the environment surrounding the shape, such as the dimensions and placement of the primary and adjacent geometric shapes. . That is, the environment surrounding the feature affects the modifications that must be made to the feature to produce a satisfactory feature on the wafer. This is due to diffracted light striking the form from the surrounding geometric shape, and this light is diffracted from the surrounding geometric shape during photomask processing of the surrounding geometric shape. However, the farther away the geometrical shape on the layout is from the form, the smaller the effect on the modification made to the form (because the amount of diffracted light that reaches the form decreases). These factors should be considered when predetermining the size of the environment.

The following is a list of terms and definitions used in this specification.
“Layout” form, geometry, environment, or modification means a form, geometry, environment, or modification found in the layout.
A “pre-tabulation” form, geometry, environment, or modification is a form, geometry, environment, or modification described in a pre-tabulation model stored in a library of pre-tabulation models.
A “mock” form, geometry, environment, or layout is a prediction of how the form, geometry, environment, or layout will appear when fabricated on a wafer, and processing Generated by a simulator program that assumes no variation (ie, assumes a “normal” processing state).

A “re-simulated” form, geometry, environment, or layout is a prediction of how the form, geometry, environment, or layout will appear when fabricated on a wafer; Generated by a simulator program that assumes one or more process variations. A re-simulated form, geometry, environment, or layout does not necessarily imply that a form, geometry, environment, or layout has been previously simulated, but one or more processes It is used as a term indicating a simulation that reflects fluctuations.
The fabrication form, geometry, environment, or layout is the form, geometry, environment, or layout that was actually generated on the wafer.
A model is said to contain morphologies, geometries, environments, modifications, equations, etc. when it includes data describing morphologies, geometries, environments, modifications, equations, etc. An environment is said to contain a geometric shape when it includes all or only a portion of the geometric shape.

Section II: Geometric correction using pre-tabulation library
Layout Modification Method Using Library of Pre-tabulated Models FIG. 7 illustrates the geometry in an IC layout using a library of pre-tabulated models , each including modifications applied to geometric shapes or forms in the IC layout. 5 is a flowchart of a layout correction method 700 for correcting a shape. Layout modification method 700 includes stage 310 of general design method 300 (FIG. 3). Accordingly, the method 700 receives a design layout and generates a modified layout. Method 700 may be performed, for example, by an electronic design automation (EDA) application that creates, edits, or analyzes IC design layouts.

  Method 700 begins (at 705) when an IC design layout is received having one or more geometries that each include zero or more features to be modified. The method then selects (at 710) the current form in the layout for modification. In some embodiments, method 700 first selects corners and bends for processing, and then method 700 uses lines for processing after all corners and bends have been processed. -Select another form, such as a point form. Next, the method 700 determines (at 712) whether the current form is located within the processing region. If so, the method 700 proceeds to step 710 where another form is selected. If not, the method 700 continues at step 715.

  Next, the method identifies (at 715) the current environment with a predetermined size, including the current form, in the layout. The current environment can be identified by, for example, setting the shape of the current environment as a rectangle having a predetermined size and positioning the rectangle so that the current form is at the center. The current environment includes the current form and one or more layout geometries. In other embodiments, the identification of the current environment is done in another way, for example using different shapes. An example of stage 715 in which the environment 520 surrounding the current form 515 is identified is shown in FIG.

  Next, the method identifies (at 720) a model that contains a pre-tabulation environment that is included in the library of pre-tabulation models and that matches the current layout environment. The pre-tabulation environment has a predetermined size equal to the predetermined size of the current layout environment. Each model in the library is created for a specific form (pre-populated form) of a specific environment (pre-populated environment), where the specific environment includes a form, one or more geometric shapes, Including modifications to the form. A method of building a pre-tabulated model library will be described below in connection with FIG.

  Compare the dimensions and placement of one or more geometric shapes in the current environment with one or more geometric shapes in the model's pre-tabulation environment to match the pre-creation to the layout environment Find a model that houses a table environment. A method for identifying a conforming model (ie, a model having a pre-tabulated environment defined in the current layout environment) is described below in connection with FIG. In this embodiment, it is assumed that a fit model is found in the library. In another embodiment described below in Section III, consider the case where no matching model is found in the library.

  Next, the method retrieves (at 725) data describing the pre-tabulation correction for the pre-tabulation form from the fit model, and the pre-tabulation correction is performed with a predetermined distribution of the current layout form and the pre-tabulation form Designed to produce the underlying fabrication on the wafer. In addition, as will be described below, the pre-tabulation correction generates a simulated form within a predetermined distribution from the pre-tabulation form. In some embodiments, the adaptation model also includes simulated environment data, re-simulated environment data, electrical property data, and / or other data in a pre-tabulated environment, such as accommodation equations or function data (described in Section IV). Like). In these embodiments, the method retrieves (at 725) any or all of the other types of data included in the fit model. These other types of data can be used by, for example, design engineers to determine how the pre-tabulation environment is expected to appear in the produced state, the electrical characteristics of the pre-tabulation environment, etc. .

  Next, pre-tabulation correction is applied to the current form in the design layout (at 730). Pre-tabulation modifications have already been created based on the pre-tabulation form and the environment (as described below in connection with FIG. 8) to produce a satisfactory production form on the wafer. Since the pre-tabulation form and environment have already been determined to match the current form and environment in the layout, applying the pre-tabulation correction to the current form will again produce the form on the wafer. Satisfactory forms should be generated in this state.

Next, the method identifies (at 732) processing regions that are around the current form. The processing area indicates that the modification made to the current form is sufficient for the processing area and that other forms of processing in the processing area are not required. An example of a stage 732 in which processing regions 530 around the current form 515 are identified is shown in FIG.
Next, the method determines (at 735) whether the current form is the final form on the design layout. If so, the method ends. If not, the method proceeds to step 710 where the next current form of the layout is selected for processing.

Building a Pre-tabulated Model Library As described above, the layout modification method 700 identifies models that contain a pre-tabulated environment that is included in the pre-tabulated model library and that matches the current layout environment (720). so). FIG. 8 is a flow diagram of a method 800 for building a library of pre-tabulation models. FIG. 8 is described in relation to FIGS. 5, 6, 9A to 9F, 10A to 10C, and 11A to 11B.
The method 800 is a set of pre-tabulations for a library that each includes a feature (such as a corner or bend), the primary geometry in which the feature is located, and zero or more adjacent geometric shapes. Start by creating an environment. In general, the set of pre-tabulated environments created for a library will cover a wide range of environments that can be found on the IC layout. The set of environments will typically cover many different forms and geometric configurations that may be encountered on an IC layout.

In some embodiments, the library or set of environments is tailored to a layout with specific preferred direction wiring. As described above, the IC uses a PD wiring model that specifies the priority wiring direction for each of the wiring layers. For example, the layers are considered to have Manhattan or diagonal preferred direction wiring. Alternatively, in the case of an analog designed IC, the layer is considered not to have priority direction wiring.
The layout for a layer with Manhattan preferred wiring is probably for one of the layout coordinate axes whose orientation is horizontal or vertical (ie, generally parallel to the boundary of the layout and / or the expected IC of the layout). And have a geometric shape with sides that form an angle of 0 ° or 90 °. Thus, a library or set of environments that have been tuned to a Manhattan preferred wiring layout will include environments that have geometric shapes with horizontal or vertical edges. FIGS. 9A through 9F show an example of an environment 905 that can be created for a Manhattan priority wiring layout. As shown in FIGS. 9A-9F, each environment 905 includes a form 910, a main geometric shape 915 in which form 910 is located, and zero or more adjacent geometric shapes 920. Note that the geometric shapes 915 and 920 are oriented horizontally or vertically.

  In contrast, a layout for a layer with diagonal preferred direction wiring will probably have a geometry with sides that are diagonally oriented (ie, at an angle of 45 ° or 135 ° to one of the layout coordinate axes). It will have an academic shape. Accordingly, a library or set of environments adjusted to have a diagonal priority wiring layout will include environments having geometric shapes with diagonal sides. 10A to 10C show an example of an environment 1005 that can be created for a diagonal priority wiring layout. As shown in FIGS. 10A-10C, each environment 1005 includes a form 1010, a primary geometry 1015 in which form 1010 is located, and zero or more adjacent geometric shapes 1020. The sides of the geometric shapes 1015 and 1020 are diagonally oriented.

  Alternatively, in the case of an analog designed IC, the layer is considered not to have priority direction wiring. Thus, a library or set of environments tailored for analog design ICs will include environments having any shape or orientation geometry. 11A-11C illustrate an example environment 1105 that can be created for an analog design layout. As shown in FIGS. 11A-11C, each environment 1105 includes a feature 1110, a primary geometry 1115 in which the feature 1110 is located, and zero or more geometric shapes 1120.

  After creating the set of environments (at 805), the method 800 is then applied to the form in each pre-tabulated environment that is predicted to produce a satisfactory form with the form created on the wafer. The fix that will be determined is determined (from step 810 to step 835). Modifications to the form in the environment are based on the main geometric shape included in the environment and any adjacent geometric shapes. That is, the geometric shape surrounding the form affects the corrections calculated for the form.

At step 810, the method 800 selects an environment in the set of pre-tabulation environments as the current pre-tabulation environment. The method then creates a modification and applies it to the form in the current pre-tabulation environment. In some embodiments, the method creates and applies the modifications using techniques known in the art.
Next, a simulation is performed (at 820) for the current pre-tabulation environment that includes modifications to the form. This simulation can be performed, for example, by a simulator that receives a current pre-tabulation environment as an input and generates a current simulated environment. The current simulated environment predicts the way in which the current pre-tabulation environment (including modifications to the form) will appear when fabricated on the wafer. In some embodiments, the simulator assumes no processing variation (ie, “normal” processing conditions).

  Next, the method is satisfactory in the result of the simulation, that is, the current simulated environment is apparently within the predetermined dispersion threshold from the pre-tabulation form included in the current pre-tabulation environment. It is determined whether the simulation form is included (at 825). If not, the method proceeds to step 815 where the method creates another form and applies it to the form in the current pre-tabulation environment, and another simulation is applied to the current pre-tabulation environment. (Including the following modification). The method repeats steps 815 to 825 until a satisfactory simulated environment is created.

  If the method determines that the simulation results are satisfactory (yes at 825), then the method creates a model for the current pre-tabulation environment (at 830) and Stores pre-tabulated environment data. In some embodiments, the model for the current pre-tabulation environment includes a current pre-tabulation environment that includes the last modification made to the form within the current pre-tabulation environment (ie, the modification that produced a satisfactory simulated result). A data structure for storing data to be described.

9A to 9F, FIG. 10A to FIG. 10C, and FIG. 11A to FIG. 11C show examples of the modifications 925, 1025, and 1125 of the forms 910, 1010, and 1110 included in the pre-tabulation environment 905, 1005, and 1105. Yes. For the sake of brevity, the modifications 925, 1025, 1125 shown are four-sided polygons, but in other embodiments, the modifications included in the pre-tabulation environment are different shapes. Please be careful.
Next, the method determines (at 835) whether the current pre-tabulation environment is the final pre-tabulation environment in the set of pre-tabulation environments. If it is not the final pre-tabulation environment, the method proceeds to step 810, where the method selects the next environment in the set of pre-tabulation environments as the next current pre-tabulation environment. If the final pre-tabulation environment, the method ends.

It fits pre tabulated environment finding methods, as described above, and the layout modification method 700, pre-tabulated were included in the library model, now identifies the model to accommodate the layout environment compatible pre tabulation environment (720 so). FIG. 12 is a flow diagram of an adaptation method 1200 for identifying models contained in a library of pre-tabulation models that contain a pre-tabulation environment that conforms to the layout environment. FIG. 12 includes step 720 of the layout modification method 700. FIG. 12 is described with reference to FIGS. 13A to 13H.

  Method 1200 begins when the environment of the layout is identified (step 715 of FIG. 7), where the layout environment includes the form, the primary geometry in which the particular form is located, and zero or more adjacent geometric shapes. Including. A single layout can have eight different orientations (appearances), and the eight orientations have the same effect as when the morphology is simulated or created if the same modification is applied to the morphology of each orientation. Note that they are equivalent in that they receive Thus, as described herein, a model's pre-tabulation environment is determined to be “fit” to the layout environment when it matches any of the eight orientations of the layout environment. This is based on the fact that the modifications described in the fit model applied to the form at each orientation produce the same form when simulated or created.

  Eight different orientations of the layout environment can be generated by rotating and reflecting a single orientation of the layout environment. Figures 13A through 13H show eight different orientations of the layout environment 1305, each of which is equivalent. FIGS. 13B-13D show the rotated orientation of the layout environment 1305 shown in FIG. 13A (FIG. 13B shows 90 ° clockwise rotation, and FIG. 13C shows 180 ° clockwise rotation. FIG. 13D shows a 270 ° clockwise rotation of the layout environment 1305 shown in FIG. 13A). FIG. 13E shows a layout environment that is the reflected orientation of the layout environment 1305 shown in FIG. 13A, ie, the orientation reflected across the 45 ° axis of the layout environment (the intersection of the x and y coordinates of the layout environment). The orientation after reflection is shown. 13F to 13H show the orientation after rotation of the layout environment 1305 shown in FIG. 13E (FIG. 13F shows 90 ° clockwise rotation and FIG. 13G shows 180 ° clockwise rotation. FIG. 13F shows a 270 ° clockwise rotation of the layout environment 1305 shown in FIG. 13E).

  After identifying the layout environment, the method then transforms the layout environment to the first reference orientation (at 1205). In some embodiments, the reference orientation of the layout environment has a main geometric shape (a form in the layout environment is located) located at the lower left of the layout environment. In other embodiments, a different definition of the reference orientation is used. Note that each layout environment has two reference orientations since there are two orientations of each layout environment in which the main geometry is located in the lower left corner of the layout environment. For example, FIGS. 13A and 13E both illustrate the reference orientation of the layout environment 1305. In some embodiments, the first reference orientation of the layout environment is achieved by rotating the layout environment until the primary geometry is located in the lower left corner of the layout environment.

Next, the method compares (at 1210) the layout environment of the first reference orientation with the pre-tabulation environment of the model in the pre-tabulation library. In some embodiments, the comparison of the layout environment of the first reference orientation and the pre-tabulation environment compares, for example, the main geometric shape included in the layout and the pre-tabulation environment with any adjacent geometric shapes. Can be done.
In other embodiments, a two-stage comparison process is used to compare the layout environment of the first reference orientation with the pre-tabulation environment. In the first stage, the layout environment and the pre-tabulation environment are divided into sub-regions. In some embodiments, the layout environment and the pre-tabulation environment are divided into 16 sub-regions. Next, the percentage of the geometric shape range in each sub-region is determined for each sub-region in both environments. The geometric shape range percentage in the sub-region is obtained by dividing the area covered by the main geometric shape of the sub-region and the adjacent geometric shape by the total area of the sub-region and multiplying by 100.

For each sub-region, a 2-bit number reflecting the geometric shape range percentage in the sub-region is determined. In some embodiments, the 2-bit number setting is 00 when the geometric shape range percentage is 0% to 25%, 01 when the geometric shape range percentage is 25% to 50%, and the geometric shape range. 10 when the percentage is between 50% and 75%, and 11 when the percentage of the geometric range is between 75% and 100%. Next, a composite bit number is generated for each environment by combining the two bits of the layout environment and the pre-tabulation environment. In some embodiments, the 16 bits of the 16 sub-regions of the layout environment and the pre-tabulation environment are combined to generate 32 bits for each environment. If the two composite bit numbers are the same, the second stage compares the dimensions and placement of the main geometric shape and any adjacent geometric shapes included in the layout environment and the pre-tabulation environment.
In other embodiments, other methods of calculating a hash function can be used. In another embodiment, the layout environment and the pre-tabulation environment are divided into several sub-regions other than 16 sub-regions. In some embodiments, the number of composite bits for each environment is a number other than a 32-bit number.

  Next, the method determines (at 1215) whether a model having a pre-tabulation environment that matches the layout environment has been found in the pre-tabulation library. If found, the method ends, whereby the layout correction method 700 then retrieves data describing the pre-tabulation correction (at 725) from the fit model. If not found, the method transforms the layout environment to the second reference orientation (at 1220). In some embodiments, the second reference orientation of the layout environment reflects the first reference orientation across the 45 ° axis of the first reference orientation (ie, x and y of the first reference orientation). Achieved by crossing the coordinates of

  Next, the method finds (at 1225) a model in the pre-tabulation library that has a pre-tabulation environment that matches the layout environment in the second reference orientation. In some embodiments, the method of finding a suitable pre-tabulation environment is to compare the dimensions and placement of the primary geometry included in the layout environment and the pre-tabulation environment with any adjacent geometric shapes. In another embodiment, the method for finding a suitable pre-tabulation environment is to compare the layout environment and the pre-tabulation environment using the two-stage comparison process described above. The method then ends, whereby the layout correction method 700 retrieves (at 725) data describing the pre-tabulation correction from the fit model.

  In the adaptation method 1200 described above, each model in the library is one of eight equivalent orientations that may be encountered in the layout, adapting to the pre-tabulation environment through the rotation and reflection process of the adaptation method 1200. Note that it includes a pre-tabulation environment that can be adapted to. Thus, the rotation and reflection process of the adaptation method 1200 considers only one pre-tabulation environment of the pre-tabulation library for any of the eight equivalent orientations encountered in the layout, so that The storage space required to store the table library is reduced.

In the embodiments described above, a single layout environment can have eight different orientations (appearances). In other embodiments, a single layout environment can be two, four, or 16 depending on the symmetry of the light source used in photomask processing and whether the 45 ° and 0 ° libraries can be combined. Can have different orientations. For example, if the light source is perfectly symmetrical, a single layout environment can have 16 different orientations.
In the embodiment described in Section II, it is assumed to find a model with a pre-tabulation environment that matches the layout environment. In another embodiment described in Section III, consider the case where no matching model is found in the library.

Section III: Alternative Method of Modifying Geometry in IC Layout Using Library of Pre-tabulated Model Figure 14 Modifying Geometry in IC Layout Using Library of Pre-tabulated Model 5 is a flowchart of an alternative layout modification method 1400. Alternative method 1400 includes stage 310 of general design method 300 (FIG. 3). Accordingly, the method 1400 receives a design layout and generates a modified layout. The method 1400 can be implemented, for example, by an electronic design automation (EDA) application that creates, edits, or analyzes an integrated circuit design layout. The alternative method 1400 includes several steps similar to those performed in the layout modification method 700 of FIG. Only the steps different from the layout correction method 700 will be described in detail here.

  The method 1400 begins (at 705) when an IC design layout is received having one or more geometries that each include zero or more features to be modified. Next, the method selects (at 710) the current form in the layout for modification. Next, the method identifies (at 715) the current environment in the layout including the current form. Next, the method determines (at 1420) whether a model having a pre-tabulation environment that matches the current layout environment is included in the library of pre-tabulation models. This can be determined, for example, using an adaptation method 1200 (described above in connection with FIG. 12) that identifies an adaptation model.

  If a matching model is found, the method 1400 retrieves data describing the pre-tabulation correction from the matching model (at 725) and applies the pre-tabulation correction to the current configuration (at 730). In some embodiments, the adaptation model can also be simulated environment data, re-simulated environment data, electrical property data, and / or other data in a pre-tabulated environment such as accommodation equation or function data (described in Section IV). Including. In these embodiments, the method retrieves (at 725) any or all of the other types of data included in the fit model.

  If no match model is found (No at 1420), the method 1400 determines whether the pre-tabulation model library includes a pre-tabulation environment that is within a predetermined variance threshold from the current layout environment. (At 1422). To make this determination, the method, for example, determines whether the geometry size and placement of the current layout environment is within a predetermined variance from the geometry size and placement of the pre-tabulated environment of the library. Judging. If so, a model with a pre-tabulation environment that is within a predetermined variance threshold is considered a “fit” model, and the method 1400 continues at step 725, where the pre-tabulation correction is accounted for. Data is retrieved from the “fit” model and pre-tabulation correction is applied to the current form (at 730).

If the method 1400 determines that the library does not include a model with a pre-tabulated environment that is within a predetermined variance threshold from the current layout environment (No at 1422), the current layout environment is the “new” environment. The method proceeds to step 1425. At step 1425, the method performs, for example, steps 815 to 830 of the library construction method 800 of FIG. 8 to create a model for the “new” environment and the current configuration. The new model is stored in a library that contains a pre-tabulation environment that duplicates the “new” environment and a pre-tabulation modification to the pre-tabulation form that duplicates the current form. The method then applies the pre-tabulation correction to the current form in the design layout (at 1430).
Next, the method determines (at 735) whether the current form is the final form of the design layout. If so, the method ends. If not, the method proceeds to step 710 where the next current form in the layout is selected for processing.

  In an alternative embodiment, after determining that the fit model is not included in the library (no at 1420), the method 1400 does not perform step 1422, but immediately after this determination for the “new” environment. A model is created (at 1425). In other embodiments, after determining that the fit model is not included in the library (No at 1420), the method 1400 uses a conventional rule-based approach rather than performing steps 1422, 1425, 1430. Determine the modifications to the current form in the layout. In other embodiments, after determining that the “fit” model is not included in the library (NO at 1422), the method 1400 uses conventional rule-based techniques rather than performing steps 1425 and 1430. Determine the modifications to the current form in the layout.

  In yet another embodiment, the method 1400 is performed without creating a conventional pre-tabulated library. In this embodiment, the method 1400 creates a pre-tabulated library (by creating a model for the pre-tabulated library in step 1425) while modifying the form in the layout. Thus, the method 1400 creates a pre-tabulated library “on the fly” during run time when used to modify the layout. If a model for a pre-tabulated library is created during runtime, it will typically be stored in a cache with relatively faster read and write times. In this embodiment, the method is in a library that contains only models that have a pre-populated environment where the relevance or “fit” model duplicates the environment previously encountered / identified in the layout during the layout modification process. It will be determined whether it is included (at 1420 and 1422). If no suitability or “fit” model is found, a new model for the new environment will be created (at 1425).

Section IV: Alternative Data Stored in the Library Model As described in Section II, the model in the library includes a pre-tabulation environment that includes the form, modifications to the form, and the primary geometric shape in which the form is located. Data describing zero or more adjacent geometric shapes. In some embodiments, the model in the library is a data structure that stores data describing the pre-tabulation environment (eg, by the dimensions and placement of objects in the pre-tabulation environment). In some embodiments, additional data is included in the model, such as data describing simulated results and / or re-simulated results.

FIG. 15 shows a conceptual diagram of data stored in the model 1500 in the pre-tabulation library. As shown in FIG. 15, the model 1500 includes pre-tabulated environment data 1505 that describes the morphology, modifications to the morphology, major geometric shapes, and zero or more neighboring geometric shapes.
In some embodiments, the model 1500 also simulates a simulated environment that is a prediction of how a pre-tabulated environment will appear when fabricated on a wafer assuming no process variation. Contains environmental data 1510. In some embodiments, the model 1500 describes a re-simulation environment that is a prediction of how the pre-tabulation environment will appear as it is fabricated on the wafer, assuming one or more process variations. Resimulation environment data 1515 to be included. In some embodiments, the model 1500 also includes electrical property data 1520 that describes electrical properties of the pre-tabulated environment. In some embodiments, the model 1500 also includes an adjustment equation or function 1525 that uses the geometric range percentage of a particular area in the design layout to determine adjustments to the pre-tabulation correction of the model (in Section V). As explained). In some embodiments, the model 1500 includes any or all of various types of data 1505, 1510, 1515, 1520, 1525. By storing such data in each model, there is no need to perform additional time-consuming operations to derive various types of data, and various types of data 1505, 1510, 1515, 1520, 1525. Are readily available to be used by designers (e.g., how pre-tabulated environments are expected to appear in the fabricated state, electrical characteristics of pre-tabulated environments, etc.) To do).

Simulated environment and re-simulated environment data As an example of how the first three types of data differ, pre-tabulated environment data 1505 includes data describing the modification of the environment, while simulated environment data 1510 and re-simulated environment data Simulated environment data 1515 is considered to include data describing how the environment will likely appear when it is created after the modifications are applied, and the re-simulated environment data 1515 is one or more Reflecting many process variations, the simulated environment data 1510 will not. Thus, the model containing simulated environment data 1510 and / or re-simulated environment data 1515 is not only a description of the modifications applied to the environment, but also the actual environment (with the modifications applied) when created. Data explaining the prediction of how it will appear can also be given. Therefore, the simulation data can be easily made available without having to perform another time-consuming simulation or re-simulation on the model environment.

  The simulated environment data 1510 and re-simulated environment data 1515 of the model 1500 can be generated and stored through modification of the library construction process 800 of FIG. FIG. 16 is a flow diagram of an alternative library construction method 1600 for building a pre-tabulated library of models each containing simulated environment data and / or re-simulated environment data. The method 1600 of FIG. 16 is identical to the library construction process 800 up to stage 830 of the process 800.

At step 830 of process 800, after a satisfactory simulated environment is generated by repeated corrections and simulations (from step 815 to step 825), pre-tabulated environment data is stored in the model. The simulation is performed (at 820) against the current pre-tabulated environment (including modifications to the configuration) by the simulator assuming no processing variation (ie, assuming “normal” processing state).
At step 830, the method 1600 then stores (at 1605) data describing the satisfactory simulated environment (simulated environment data) in the model. Recall that a satisfactory simulated environment is a simulated result of a pre-tabulated environment that includes final modifications made to the form within the pre-tabulated environment.

The method then uses a simulator program that takes into account one or more processing variations of the current pre-tabulation environment (including final modification of the form and produced a satisfactory simulated environment). A re-simulation environment is generated (at 1615). In some embodiments, when generating the re-simulation environment, the simulator program considers certain process variations (eg, lens defocus or light dose) that have certain values.
In other embodiments, a set of two or more re-simulation environments reflecting a set of values for a particular process variation is generated (at 1610) for a single pre-tabulated environment. In these embodiments, a plurality of simulated environments are generated for a single pre-tabulated environment, and each re-simulated environment is generated by a simulator that considers a range of different values for specific processing variations. For example, a re-simulation environment can be generated to reflect each out-of-focus value, −6, −3, +3, +6, resulting in a total of four re-simulation environments for a single pre-tabulated environment. .

The re-simulation environment is a prediction of how the correction environment will appear in the state of being fabricated on the wafer, but it is one such as a change in lens focus or exposure (light amount) during photomask processing. Alternatively, it is generated by a simulator program that assumes more processing variation. Thus, compared to the simulated environment (generated at 820), the re-simulated environment reflects one or more process variations and is apparently slightly different from the simulated environment. For example, the geometric shape of the re-simulated environment may be thinner, thicker, or a different shape than the corresponding geometric shape of the simulated environment.
Next, the method stores the re-simulation environment (re-simulation environment data) in the model (at 1615). In some embodiments, the model also stores data associated with any particular process variation reflected by the re-simulation environment (ie, considered by the simulator that generates the re-simulation environment) and any particular value of the process variation. To do.

In an embodiment where multiple re-simulation environments are generated for a single pre-tabulation environment, multiple re-simulation environments are stored in the model. For each re-simulation environment of the plurality of re-simulation environments, any specific process variation reflected by the re-simulation environment and data related to any specific value of the process variation are stored in the model in association with the re-simulation environment. For example, if a particular re-simulation environment reflects +6 out of focus, a +6 out-of-focus value is associated with the specific re-simulation environment and stored in the model. In other embodiments, a separate model is created for each re-simulation environment of the plurality of re-simulation environments, and the model includes data describing the re-simulation environment and any specific process variations and processes reflected by the re-simulation environment. Stores data associated with any particular value of variation.
In some embodiments, the method 1600 performs only step 165 and not steps 1610 and 1615 so that only simulated environment data is stored in the model. In other embodiments, the method 1600 performs only steps 1610 and 1615 and not step 1605 so that only re-simulated environment data is stored in the model.

Introducing Electrical Property Data In some embodiments, the model 1500 also includes electrical property data that describes one or more electrical properties of the pre-tabulation environment. In some embodiments, the model 1500 includes equations (characteristic equations) related to the electrical characteristics of the identification of the pre-tabulated environment. In some embodiments, the characteristic equation may determine the electrical properties of the identification of the pre-tabulation environment as a function of the size and placement of one or more geometric shapes of the pre-tabulation environment and / or It is expressed as a function of more process variation.
In the embodiments described below, the characteristic equation is related to the capacitance characteristic of the environment, but in other embodiments, the characteristic equation is related to the electrical characteristics of another environment, such as inductance or resistance. In the embodiment described below, lens defocus and light amount processing variation are considered, but in other embodiments, other processing variation is considered.

  In some embodiments, the pre-tabulation environment includes two or more geometric shapes, and the characteristic equation (capacitance equation) relates to the capacitance between the two geometric shapes of the environment. In some embodiments, the capacitance equation is calculated as two functions of the pre-tabulation environment as a function of distance between two geometries and one or more process variations (such as lens defocus or ray dose). Describe the capacitance between geometric shapes. As described with reference to FIGS. 3 and 16, a re-simulation environment that reflects one or more process variations is apparently slightly different from a simulated environment that does not take process variations into account. For example, the geometric shape of the re-simulated environment may be thinner, thicker or different than the geometric shape of the simulated environment. As the adjacent geometric shape of the environment becomes thinner or thicker, the distance between adjacent geometric shapes varies, and thus the capacitance between adjacent geometric shapes varies.

  FIGS. 17A and 17B show simulated results for the same pre-tabulation environment that includes a first pair of adjacent geometric shapes 1715 and a second pair of adjacent geometric shapes 1720. Adjacent geometries of the environment can create interactions (capacitance) between the geometric shapes, and the amount for the interaction is affected by the distance between adjacent geometric shapes. FIG. 17A shows a simulation result 1705 of the pre-tabulation environment that does not reflect the process variation. As shown in FIG. 17A, there is a first distance between a first pair of adjacent geometric shapes 1715 and a second distance between a second pair of adjacent geometric shapes 1720. The capacitance between the first pair of tangent geometry 1715 is determined primarily by a first distance 1717 between adjacent geometry 1715 and the capacitance between the second pair of adjacent geometry 1720 is adjacent. Determined by a second distance 1722 between geometric shapes 1720.

  FIG. 17B shows a simulated result 1735 of the same pre-tabulation environment as FIG. 17A that takes into account one or more processing variations (such as lens defocus or lens defocus). FIG. 17B shows a simulated environment 1735 that varies from the simulated environment 1705 shown in FIG. 17A. Specifically, as shown in FIG. 17B, there is a third distance 1747 between the first pair of adjacent geometric shapes 1715 that is different from the first distance 1717 shown in FIG. 17A. There is also a fourth distance 1742 between the second pair of adjacent geometric shapes 1720 that is different from the second distance 1722 shown in FIG. 17A. These distance variations between the first and second pairs of adjacent geometries result from one or more process variations reflected by the simulation result 1735 of FIG. 17B.

In some embodiments, the capacitance (C) between two geometries in a changed environment that varies from the initial environment is represented by a first capacitance equation:
C = C ₀ + k ₁ ΔW
Using the first capacitance equation, the capacitance between the two geometries of the environment can be calculated taking into account the change in distance (ΔW) between the two geometries. However, the first capacitance equation does not represent capacitance as a function of process variation (which is a cause of distance change (ΔW)).

The capacitance between adjacent geometric shapes is affected by the distance between the geometric shapes, and one or more process variations affect the distance between the geometric shapes (the process variations are Capacitance between adjacent geometric shapes is a function of the distance between the geometric shapes and one or more processing variations (since the geometric shapes can cause thinning or thickening). It turns out that it is. In some embodiments, the capacitance between the two geometries of the changed environment that has changed from the initial environment by one or more process variations (PV) is represented by the second capacitance equation. R:
C = C ₀ + k ₁ ΔW + k ₂ ΔPV ₁ +. . .
Here, C ₀ is the capacitance (initial capacitance) of the initial environment reflecting no processing variation (that is, ΔW, ΔPV ₁ etc. are all equal to 0), and k ₁ , k _2, etc. are predetermined sensitivity coefficients. Yes, ΔW is the difference in distance between the two geometric shapes from the initial environment to the changed environment, and ΔPV ₁ is the difference in the value of the specific process variation reflected in the initial environment and the changed environment It is. For example, ΔW may be equal to the distance between the two geometric shapes of the changed environment minus the distance between the two geometric shapes of the initial environment. ΔPV ₁ can also be equal to the value of the specific process variation reflected in the environment after the change minus the value of the specific process variation reflected in the initial environment (some embodiments). Is always equal to 0). In some embodiments, the value of C ₀ (initial capacitance) is adjusted / shifted to correct or minimize errors in the capacitance equation, or set to a predetermined value.

In some embodiments, the capacitance (C) between the two geometries of the changed environment that has changed from the initial environment due to lens defocusing and light dose processing variation is a second capacitance equation of the form Represented by an example:
C = C ₀ + k ₁ ΔW + k ₂ ΔDF + k ₃ ΔDose where k ₁ , k ₂ , and k ₃ are predetermined sensitivity coefficients, and ΔDF is an out-of-focus value reflected in the initial environment and the changed environment. The Δ dose is a difference in the amount of light reflected in the initial environment and the changed environment.

Method of storing electrical property data in a model The interaction (capacitance) between the geometry of the environment is an important electrical property of the environment to be considered when designing an IC layout. Therefore, it would be highly advantageous to have data describing the electrical characteristics of an environment that is readily available without the need for further calculations. In some embodiments, the capacitance equation describing the capacitance characteristics of the environment is stored in a model that contains the environment, and the model is included in the pre-tabulated library of models. In some embodiments, the capacitance equation represents the capacitance between two geometries of the environment as a function of the distance between the two geometries. In some embodiments, the capacitance equation represents capacitance as a function of distance variation between two geometries and one or more process variations.

The library construction method 800 of FIG. 8 can be modified so that each model builds a library of pre-tabulation models that includes a pre-tabulation environment and a predetermined capacitance equation that describes the capacitance characteristics of the pre-tabulation environment. In some embodiments, the capacitance equation is of the form C = C ₀ + k ₁ ΔW, where the value of C ₀ and the coefficient k ₁ are predetermined. In some embodiments, the capacitance equation is in the form C = C ₀ + k ₁ ΔW + k ₂ ΔDF + k ₃ Δdose, where the value of C ₀ and the coefficients k ₁ , k ₂ , and k ₃ are given by Is.

Specifically, after stage 830 of library construction method 800, an alternative library construction method 1800 (shown as a flow diagram in FIG. 18) can be performed to generate a library that includes a predetermined capacitance equation. After step 825 of the library construction method 800, a current environment is created that generates a satisfactory simulated environment, which is referred to as an initial environment. Next, a model for storing data describing the current environment is created (at stage 830 of the library construction method 800).
An alternative library construction method 1800 begins (at 1805) when this initial environment is received. An example of the initial environment is shown in FIG. 17A. In some embodiments, the initial environment includes at least one pair of adjacent geometric shapes with a particular distance in between. In some embodiments, the initial environment includes two or more pairs of adjacent geometric shapes, each having a specific distance in between.

The method then performs a 3D electromagnetic simulation (3D simulation) on the initial environment to find the capacitance (C ₀ ) between a pair of adjacent geometric shapes in the initial environment (at 1807). In some embodiments, the method performs a 3D simulation on the initial environment to find an initial capacitance between two or more pairs of adjacent geometries in the initial environment. In some embodiments, the 3D simulation is performed by a three-dimensional electromagnetic simulator program that solves the Maxwell equations known in the art. In some embodiments, another type of simulation is performed to find the initial capacitance (C ₀ ).

Next, the number of iterations of the method is counted, and a counter used to stop the iteration is set to 0 when X predetermined iterations are completed (1810).
A re-simulation is then performed on the current environment to generate a changed environment (at 1815), which takes into account exemplary processing variations in defocus and dose. An example of the initial environment after the change is shown in FIG. 17B. In some embodiments, the re-simulation is performed by a simulator that takes into account specific exemplary values of lens defocus and light dose.

  In the changed environment, a pair of adjacent geometric shapes are different in appearance from the initial environment (eg, they will appear thin, thick, or different shapes). Thus, the distance between adjacent geometric pairs in the changed environment will likely be different from the distance between adjacent geometric pairs in the initial environment. In some embodiments, the initial environment and the changed environment include two or more pairs of adjacent geometric shapes, and the distance between the two or more pairs of geometric shapes. Changes from the initial environment to the changed environment.

  Next, the method determines (at 1820) the difference (at 1820) between the distance between the pair of adjacent geometric shapes in the changed environment and the initial environment. The method of finding the difference (ΔW) is a comparison of pairs of adjacent geometric shapes in the changed environment and the initial environment. For example, ΔW may be equal to the distance between the changed environment geometry pair minus the distance between the initial environment geometry pair. In some embodiments, the method determines the difference (ΔW) between two or more pairs of distances in the changed environment and the adjacent geometry of the initial environment.

The method then performs a 3D or other simulation on the changed environment to find the capacitance value (C) between the pair of adjacent geometric shapes of the changed environment (at 1825). In some embodiments, the method performs a 3D or other simulation on the changed environment to determine the capacitance for each of two or more pairs of adjacent geometric shapes of the changed environment. locate.
Next, the method includes, as exemplary results for adjacent geometry pairs, capacitance value (C) (determined at 1825), distance difference (ΔW) (determined at 1820), and lens defocus and ray dose. Of a particular value (used in re-simulation in step 1815). In some embodiments, the method stores capacitance values (C) and specific values of lens defocus and ray dose for two or more pairs of adjacent geometries.

  Next, the method determines (at 1840) whether the counter is equal to X. If not, the method increments the counter (at 1845) to determine new example defocus and dose values (at 1847). Next, a re-simulation taking into account the new exemplary defocus and dose values is performed in the initial environment (at 1815). If the method determines that the counter is equal to X (yes at 1840), the method proceeds to step 1850.

  At this point, the method has already stored a set of exemplary results (equal to X) each having capacitance (C), distance difference (ΔW), defocus, and dose value. Yes (at 1835). An exemplary set of results covers a certain range of capacitance (C), distance difference (ΔW), defocus, and dose values. Using this data, the method considers all the exemplary results of X and represents a capacitance equation that represents the capacitance between a geometric pair as a function of distance difference (ΔW), defocus, and dose. Judge (at 1850). In some embodiments, the method determines a capacitance equation for two or more pairs of geometric shapes. In some embodiments, the capacitance equation is automatically determined without the need for human intervention. In some embodiments, the method determines the capacitance equation using a mathematical modeling method or a computer learning method (described in Section V).

In some embodiments, the capacitance equation is of the form:
C = C ₀ + k ₁ ΔW + k ₂ ΔDF + k ₃ ΔDose Here, C ₀ is a predetermined capacitance value, k ₁ , k ₂ , and k ₃ are predetermined sensitivity coefficients, and ΔDF changes with the initial environment. The difference between the defocus values reflected in the later environment, and the Δ dose is the difference between the light amount values reflected in the initial environment and the changed environment. Note that since the initial environment is typically a simulated environment that does not reflect process variations, the initial environment generally reflects zero out-of-focus and dose values. Therefore, ΔDF is equal to the out-of-focus value reflected in the changed environment, and Δdose is equal to the dose value reflected in the changed environment.
The method then stores (at 1855) the determined capacitance equation in the model created at step 830 of FIG. In some embodiments, it stores two or more determined capacitance equations in the model. Next, the method ends.

In an alternative embodiment, the alternative library construction method 1800 is performed separately from the library construction method 800 of FIG. In this embodiment, the method 1800 receives (at 1085) an initial environment that is a simulated environment generated by another method, such as a conventional layout design method. The method 1800 receives a set of such simulated environments and generates a set of models in the library, each containing a predetermined capacitance equation.
By storing the capacitance equation for a pre-tabulated library environment, this reduces the end time required to later determine the capacitance equation for that environment. The capacitance equation can be used to determine the capacitance between a pair of adjacent geometric shapes in the environment given a specific value of lens defocus and ray dose.

Electrical Property Data: Alternative Embodiment In an alternative embodiment, the method 1800 considers one or more different process variations other than lens defocus and light dose. In these embodiments, the method 1800 takes into account one or more different process variations when performing re-simulation (at 1815) and is specific for one or more different process variations. The value is stored (1835) and a capacitance equation is determined (at 1850) that takes into account one or more different process variations.

In an alternative embodiment, the method 1800 does not determine (1850) the capacitance equation, but each has a capacitance (C), a distance difference (ΔW), an out-of-focus value, and a dose value. The example result set determined and stored at step 1847 from 1815 is stored (at 1855).
In an alternative embodiment, the method 1800 stores only the capacitance-distance difference (ΔW) value as an exemplary result (at 1835) and determines a capacitance equation of the form C = C ₀ + k ₁ ΔW ( 1850) and store this capacitance equation in the model (at 1855). In some embodiments, the capacitance equation is in a form other than C = C ₀ + k ₁ ΔW or C = C ₀ + k ₁ ΔW + k ₂ ΔDF + k ₃ Δdose.

In an alternative embodiment, the method 1800 does not perform a simulation of the initial environment (at 1815), but the distance difference (ΔW) between the initial environment and a pair of adjacent geometric shapes of the capacitance equation is predetermined. Create a changed environment with adjacent geometric pairs having a certain distance between them to be equal to the difference. Thus, through multiple iterations, the method 1800 creates a set of changed environments that produces a set of distance differences (ΔW). A set of distance differences (ΔW) can be determined in advance by a design engineer. The method also stores only the value of the difference between capacitance and distance (ΔW) as an exemplary result (at 1835) and determines a capacitance equation of the form C = C ₀ + k ₁ ΔW (at 1850), Store the capacitance equation in the model (at 1855).
In an alternative embodiment, the method 1800 determines and stores an equation describing the electrical characteristics of the environment other than capacitance. For example, the method 1800 may determine and store an inductance equation that describes the inductance of the environment, or may determine and store a resistance equation that describes the resistance of the environment.

Section V: Modifying the layout using a library of pre-tabulated models with equations or function-based methods As described above, the model in the model's pre-tabulated library contains a description of a pre-tabulated environment of a given size. . To keep the number of pre-tabulated environments in the library manageable, the predetermined size of the pre-tabulated environment is kept at a reasonable size (the larger the predetermined size of the pre-tabulated environment, the more Because the number of pre-tabulation environments required by the library to cover more variation in the dimensions and placement of possible geometries is large).

  In a layout correction method 700 (described above with reference to FIG. 7) that uses a library of pre-tabulation models to correct geometric shapes in an IC layout, the design layout depends on the predetermined size of the library's pre-tabulation environment. The size of the environment identified above is determined and the layout environment includes the form to be modified. However, geometric shapes outside the layout environment also affect how the shape will appear in the fabricated state, but to a lesser extent than geometric shapes inside the layout environment .

  In some embodiments, information related to the geometry outside the layout environment (outer geometry) is used to apply the model to be applied to the form in the layout environment (pre-tabulation that is compatible with the layout environment). Adjust modifications included in the environment). In other embodiments, information related to the geometry between the first radial distance and the second radial distance from the layout environment is used to adjust the modifications included in the model. In yet another embodiment, the modifications included in the model are adjusted according to a predetermined adjustment equation or function included in the model that uses the geometric range percentage of a particular area in the design layout.

  FIG. 19 is a flow diagram of an adjustment method 1900 that uses a library of pre-tabulated models with predetermined adjustment equations or functions to modify the geometry in the IC layout. Each model in the library includes a modification to be applied to the geometry or form in the IC layout and a predetermined adjustment equation or function used to adjust for the modification. The method 1900 can be implemented, for example, by an electronic design automation (EDA) application that creates, edits, or analyzes IC design layouts. Many of the steps of the adjustment method 1900 of FIG. 19 are similar to the layout modification method 700 of FIG. 7, so only the different steps will be described in detail here. FIG. 19 will be described with reference to FIG.

  The adjustment method 1900 includes stage 310 of the general design method 300 (FIG. 3). Accordingly, the method 1900 receives a design layout and generates a modified layout. Method 1900 begins (at 1905) when an IC design layout is received having one or more geometries, each containing zero or more features to be modified. Next, the method selects (at 1910) the current form in the layout for modification. Next, the method identifies (at 1915) the current environment in a layout having a predetermined size that contains the current form.

  Next, the method identifies (at 1920) a model containing a pre-tabulation environment that is included in the library of pre-tabulation models and that matches the current layout environment. Each model in the library includes data describing a pre-tabulation environment that includes morphologies, the primary geometry in which a particular morphology is located, and zero or more neighboring geometric shapes. Each model of the library also includes data describing the pre-tabulation correction for the pre-tabulation form and a predetermined adjustment equation or function used to adjust for the pre-tabulation correction. A method for building a library of pre-tabulated models, each containing a predetermined adjustment equation or function, is described below in connection with FIG.

  The method then retrieves (at 1915) from the fit model data describing the pre-tabulation correction and a predetermined adjustment equation or function for adjusting the pre-tabulation correction. In some embodiments, the adaptation model also includes other data in the pre-tabulated environment, such as simulated environment data, re-simulated environment data, and / or electrical property data (as described in Section IV). In these embodiments, the method retrieves (at 1925) any or all of the other types of data included in the fit model.

In some embodiments, the adjustment equation or function includes one or more predetermined coefficients and one or more variables that are a geometric range percentage of a particular area in the design layout. including. In some embodiments, the accommodation equation or function is of the form:
A = k ₁ F ₁ + k ₂ F ₂ +. . .
Here, A is an adjustment made to the pre-tabulation correction, k ₁ , k _2, etc. are predetermined coefficients, and F ₁ , F _2, etc. are the geometry of a specific area in the design layout. The percentage of the shape range. In other embodiments, the adjustment equation or function is in a different form.

  The method then determines (at 1930) the geometric range percentage of the particular area within the design layout specified by the adjustment equation or function. In some embodiments, the geometric range percentage specified in the adjustment equation or function is for areas of the design layout between the inner predetermined radial distance and the outer predetermined radial distance from the current configuration, and these areas Are called radial regions. The geometric range percentage in the radial region is equal to the area covered by the geometric shape in the radial region divided by the total area of the radial region and multiplied by 100.

  FIG. 20 shows a top view of a sub-region 2005 in a layout that includes various geometric shapes 2007, a current form 2015, and three radial regions 2020, 2025, 2030 surrounding the current form 2015. FIG. The first radial region 2020 extends from the first radial distance 2035 to the second radial distance 2040 from the current configuration 2015, and the second radial region 2025 from the second radial distance 2040 to the current configuration. The third radial distance 2045 from 2015 and the third radial region 2030 range from the third radial distance 2045 to the fourth radial distance 2050 from the current configuration 2015. A geometric range percentage can be determined for each radial region 2020, 2025, 2030.

Next, the method determines (at 1935) the adjustment equation or function and the adjustment to be made to the pre-tabulation using the geometric range percentage specified in the adjustment equation or function. In the example shown in FIG. 20, it is assumed that the predetermined equation is of the form:
A = k ₁ F ₁ + k ₂ F ₂ + k ₃ F ₃
Here, A is an adjustment performed for pre-tabulation correction, k ₁ , k ₂ , and k ₃ are predetermined coefficients, and F ₁ , F ₂ , and F ₃ are the first and second, respectively. , And the third radial region 2020, 2025, and 2030 in the geometric range percentage. After determining the values of the geometric shape range percentages F ₁ , F ₂ , F ₃ , these values are entered into the equation to determine the adjustment (A) to be made for pre-tabulation correction. The adjustment can be expressed, for example, as a percentage amount that the correction is increased or decreased, or a distance that each side of the correction is increased or decreased.

  The method then applies the calculated adjustment to the pre-tabulation correction (at 1940) (eg, by increasing or decreasing the correction by a computational amount) to produce an adjusted correction. The adjusted correction is then applied to the current form in the design layout (at 1945). Next, the method determines whether the current form is the final form of the design layout (1950). If so, the method ends. If not, the method proceeds to step 1910 where the next current form in the layout is selected for processing.

  As described above, the method 1900 identifies (at 1920) a model containing a pre-tabulation environment that is included in the library of pre-tabulation models and that matches the current layout environment. Each model of the library includes a pre-tabulation environment having pre-tabulation corrections and predetermined adjustment equations or functions used to adjust for the pre-tabulation corrections. In some embodiments, the adjustment equation or function includes one or more predetermined coefficients and one or more variables that are a geometric range percentage of a particular area in the design layout. including.

  The library of FIG. 8 so that each model builds a library of pre-tabulation models including a pre-tabulation environment having pre-tabulation corrections and a predetermined adjustment equation or function used to adjust for the pre-tabulation corrections. The construction method 800 can be modified. Specifically, after stage 830 of library construction method 800, an alternative library construction method 2100 (shown as a flow diagram in FIG. 21) can be performed to generate a library that includes predetermined adjustment equations or functions. .

  After step 825 of the library construction method 800, a current pre-tabulation environment with a form modification that produces a satisfactory simulated environment is achieved, and this modification is referred to as an initial modification. Next, a model for storing the current pre-tabulation environment is created (at stage 830 of the library construction method 800). The alternative library construction method 2100 begins (at 2105) when a current pre-tabulation environment with initial modifications is received. The counter is then set to 0 (at 2110), and the counter is used to count the number of iterations of the method, and the iteration is stopped when a predetermined number of X iterations are completed.

  Next, a simulation is performed (at 2115) in the current pre-tabulation environment that includes the morphological modification, which simulates one or more exemplary geometric range values for a particular region surrounding the morphologies. Consider. In some embodiments, the exemplary geometric range is in a region between the inner predetermined outer radial distance and the outer predetermined radial distance from the configuration. For example, three exemplary geometric ranges of three radial regions can be considered in the simulation (see FIG. 20). Through multiple iterations of method 2100 (determined by a predetermined number of iterations X), the exemplary geometric range will vary through a wide range of values. For example, when considering three exemplary geometric ranges of three radial regions, the geometric range is 5%, 5%, 5% for the first iteration, 5%, 5% for the second iteration, 5% %, 10%, 5%, 5%, 15% after the third repetition.

  The simulation can be performed, for example, by a simulator that receives a current pre-tabulation environment and one or more geometric shape range values as input and generates a current simulated environment. How the current simulated environment is as fabricated on the wafer, taking into account the modifications applied to the features currently in the pre-tabulation environment and one or more exemplary geometric range values This predicts whether a pre-tabulation environment will appear at this time.

  Next, the present method determines whether the simulation result is satisfactory, that is, the simulated environment is within the range of the predetermined dispersion threshold from the pre-tabulation form currently included in the pre-tabulation environment. (2120). If not, the method proceeds to step 2125 where the method adjusts the modifications to the features in the current pre-tabulation environment and performs another simulation on the current pre-tabulation environment. The method repeats steps 2115 through 2125 until a satisfactory simulated environment is created, which is created by final modification.

  If the method determines that the simulation results are satisfactory (yes at 2120), the method determines the total adjustment (received at step 2105) made to the initial correction (at 2130). ), This combination of total adjustment and initial correction is applied to the pre-tabulation form and produces a satisfactory simulated form. The determination of the total adjustment can be made, for example, by comparing the area of the final correction that produced a satisfactory simulation with the area of the initial correction, and the difference between the two corrections is the total adjustment made to the initial correction. It is. In some embodiments, the total adjustment is expressed as a numerical value, for example as a percentage amount.

  The method then stores (at 2135) the total adjustment and one or more geometric range values as exemplary results. Next, the method determines (at 2140) whether the counter is equal to X. If not, the method increments the counter (at 2145) and determines a new geometry range value (at 2147). Next, a simulation that considers one or more new geometry range values is performed in the current pre-tabulation environment (at 2115). If the method determines that the counter is equal to X (yes at 2140), the method proceeds to step 2150.

  At this point, the method has already stored (at 2135) several example results equal to X, each with a total adjustment value and one or more geometric range values. The method then considers all X exemplary results and an adjustment equation describing how the total adjustment value is derived from one or more geometric range values. Alternatively, the function is determined (at 2150). In other embodiments, other measurements of the area surrounding the feature are used in the method to determine an adjustment equation or function that explains how the total adjustment is derived. In some embodiments, the adjustment equation or function is automatically determined without the need for human intervention.

In some embodiments, the method uses a mathematical modeling method to determine the adjustment equation or function. For example, each of the X number of exemplary results can be in the form of the following equation:
A = k ₁ F ₁ + k ₂ F ₂ +. . .
Here, A is total adjustment, k ₁ , k _2, etc. are coefficients, and F ₁ , F _2, etc. are geometric shape range values. Next, conventional data fitting methods (such as least squares fitting methods) can be applied to X number of equations to determine the best values for the coefficients k ₁ , k _2, etc.

In other embodiments, the method uses computer learning methods to determine the adjustment equation or function. For example, each of the X exemplary results is a computer learning program (a neural network) that generates an adjustment function that explains how the total adjustment value is derived from one or more geometric range values. Network). In computer learning, there is no single mathematical model to assume (eg, linear, least squares fit, etc.), and the number of coefficients (k ₁ , k _2, etc.) included in the adjustment function is not predetermined. (As in the mathematical model method). Thus, the computer learning program considers any mathematical model and any number of coefficients in creating the adjustment function that describes the exemplary results. The resulting adjustment function can have the form of any equation, or it can be in the form of a flow diagram or internal model. Also, the resulting adjustment function includes the best value for every coefficient of the adjustment function.

With the value of the coefficient of the adjustment equation or function determined, the adjustment equation or function is determined. The adjustment equation or function can then be used, for example, by the adjustment method 1900 to determine adjustments made to the pre-tabulation model (at 1935). Since the coefficients of the adjustment equation or function are predetermined, the calculation of the adjustment can be performed by inputting the geometric shape range percentage specified by the adjustment equation or function.
Next, the method determines (at 2155) an adjustment equation or function for the model created in step 830 of FIG. 8 that includes data that currently describes the pre-tabulation environment. Next, the method ends.

Section VI: Modifying the layout of a layer on an IC using information related to another layer on the IC Traditionally, when the design of each layout proceeds primarily independently of the design of other layouts on other layers, Layouts are created for IC layers one layer at a time. However, the metal area of the lower layer of the IC affects the vertical level of the upper layer (upper layer), but the metal area of the layer depends on the IC element on the layer relative to the total area of the layer (IC component , The ratio of the area occupied by interconnect lines, via pads, etc.). The vertical level of the layer in turn affects the fabrication process of the IC elements on the layer.

  For purposes of explanation, assume that the upper layer is located above the lower layer at a vertical level that is considered “normal” when the metal coverage of the lower layer is considered “average”. However, if the metal coverage of the lower layer is above “average”, the upper layer is located above the lower layer at a vertical level that is below “normal”. Also, if the metal coverage of the lower layer is below “average”, the upper layer is above the lower layer at a vertical level above “normal”. This is due to the metal containing IC elements that are softer than the photoresist material surrounding the metal on the lower layer. In the IC fabrication process, after the IC elements are created on the lower layer, the lower layer passes through a polishing process where the metal and the photoresist material surrounding the metal are worn away. Since the metal is softer than the photoresist material, a layer with a relatively high metal area will wear to a lower height than a layer with a relatively low metal area.

  Thus, the upper layer sub-region located immediately above the lower layer sub-region having a metal range above the “average” is at a vertical level below “normal” and below the “average”. The upper layer sub-region located immediately above the lower layer sub-region with the metal extent is at a vertical level above "normal". Thus, depending on variations in the metal coverage of the lower layer, there may be variations in the vertical level of the upper layer across the layer (ie, vertical deviation from flatness or “normal” level).

  Variation in the vertical level at which the upper layer is located affects how the IC elements on the upper layer appear in the fabricated state. In the IC fabrication process, a light source and lens are used to focus the light passing through the photomask onto the photoresist layer and imprint the IC element onto the photoresist layer, and then etch away the weakened areas of the photoresist layer. Recall that an IC element is generated. If there is a variation in the vertical level at which the layer is located, light striking the layer during photomasking cannot be focused across the layer (since the distance to the lens at the time of focusing changes). Rather, the light will have varying levels of defocus across the layers. The defocus variation of light during photomask processing is substantial between the geometry designed on the layout and created on the photomask and the geometry actually created on the wafer (as an IC element). Cause inconsistencies.

  To illustrate the concept of light defocus, assume that light falling on a sub-region of a layer having a “normal” (flat) vertical level has a defocus value of zero (the sub-region is “ To be considered the “right” distance). Accordingly, it can be said that light falling on a sub-region of a layer having a vertical level above “normal” has an out-of-focus value of + DF, where DF is a real number. It can also be said that light falling on a sub-region of a layer having a vertical level below “normal” has an out-of-focus value of −DF.

In summary, fluctuations in the metal coverage of the IC bottom layer cause fluctuations in the vertical level where the IC top layer is located, which in turn causes fluctuations in the defocus level of light during photomask processing of the top layer. This in turn causes a large discrepancy between the geometry designed on the layout for the top layer and the geometry actually created on the wafer (as an IC element). However, if the geometry in the layout for the upper layer is designed and modified in consideration of the variation in the metal range of the lower layer and the vertical deviation data (undulation data) of the upper layer, the geometry designed in the layout for the upper layer The discrepancy between the shape and the geometry actually created in the upper layer can be reduced.
In some embodiments of the present invention, the geometry in the layout for a layer of the IC is modified based on the layer relief data (vertical deviation data). In some embodiments, a layout designed to be created on the top layer of the IC is modified with information related to the layout designed to be created on another layer of the IC.

  FIG. 22 is a flow diagram of a change method 2200 that uses information related to the IC lower layer layout to change the modification of the geometry in the layout for the upper layer of the IC. The method 2200 may be performed, for example, by an electronic design automation (EDA) application that creates, edits, or analyzes IC design layouts. 22 will be described with reference to FIG. Method 2200 begins when an IC top layer (ie, a layer to be fabricated on an IC other than the bottom layer) layout (top layout) is received (at 2205), where the layout is geometric, shape, And modifications to the form. In some embodiments, top layout generation is performed using a pre-tabulated library of models (described above in Section II). In other embodiments, the top layout is generated using a different method, such as a conventional layout design method.

  Next, the method 2200 retrieves (at 2210) data for the IC lower layer (ie, the layer to be fabricated on the IC that is lower in position than the upper layer) layout (lower layout). The lower layer data describes the geometric shape in the lower layout, and includes the size and arrangement data of the geometric shape. Using the lower layout data, the method then generates (at 2215) a lower layout density map that indicates the percentage of the geometric range in each subregion of the lower layout. The percentage of the geometric shape range in the sub-region is the area covered by the geometric shape in the sub-region divided by the geometric shape range in the sub-region and multiplied by 100. The percentage of the geometric range in the sub-region reflects the metal range of the sub-region when the geometric shape in the sub-region is later fabricated as an IC element on the wafer. In other embodiments, the method generates (at 2215) another description (other than the density map) of the properties of the underlying layout, such as functions, wavelets, etc.

  In some embodiments, the method includes: 1) dividing the lower layout into sub-regions; and 2) determining the percentage of the geometric shape range in the sub-region for each sub-region, thereby determining the density map of the lower layout. (At 2215). FIG. 23 shows a top view of a portion 2300 of a lower layout that includes a geometry 2305 that can represent various IC elements such as circuit modules, interconnect lines, or via pads to be fabricated on a wafer. Show. As shown in FIG. 23, the portion 2300 of the lower layout is divided into sub-regions 2310. In some embodiments, a geometric range percentage is determined for each sub-region 2310.

  After generating the density map of the lower layout, the method selects (at 2220) the current form (with modifications) in the upper layout for processing. The method retrieves (at 2225) the geometric range percentage in the sub-region of the lower layout designed to be created under the current form from the density map. Generally, the first area of the first layer of the IC having the same x and y coordinates as the second area of the second different layer of the IC is created immediately above or immediately below the second area. These first and second areas will be referred to as corresponding areas. Thus, the method 1) determines the x and y coordinates of the current form, and 2) the corresponding sub-layout of the lower layout having a span of x and y coordinates that encompasses the x and y coordinates of the current form. Step 2225 can be performed by determining the region and 3) retrieving the geometric shape range percentage in the corresponding sub-region.

  Using the geometric range percentage in the corresponding subregion of the lower layout, the method then uses the vertical deviation from the “normality” or flatness of the current form on the upper layout, ie the current form. Determines the estimated distance (at 2230) that is estimated to be at the vertical level away from the “normal” vertical level as fabricated on the wafer. The “normal” vertical level is located, for example, when the corresponding sub-region of the lower layout has a predetermined “average” geometric range percentage, eg, 25%, 50%, etc. (created Predetermined) by setting the “normal” vertical level to the estimated vertical level.

  In some embodiments, the method determines a vertical deviation estimate for the top layout current form using a set of rules in a predetermined look-up table. The look-up table shows the geometric range percentages in the sub-regions of the lower layout and correlates each geometric range percentage with a specific vertical deviation estimate for the corresponding form of the upper layout. For example, the look-up table may estimate 5% of the geometric range of the lower layout sub-region to an estimate of +10 nm within the vertical deviation for the corresponding configuration of the upper layout, and 20% of the geometric shape of the lower layout sub-region Range to an estimate of +2 nm within the vertical deviation for the corresponding form of the upper layout, and 75% geometric range of the sub-region of the lower layout to an estimate of −7 nm within the vertical deviation for the corresponding form of the upper layout , And the like.

  After determining the vertical deviation estimate for the top layout current form, the method 2200 determines (at 2235) a change in the current form modification based on the vertical deviation estimate for the current form. In some embodiments, the method uses a set of rules in a predetermined look-up table to determine changes to the current form modification. The look-up table enumerates various estimates of the vertical deviation for the form and correlates each estimate with a particular change applied to the form modification. The change can be expressed, for example, as a percentage amount to which the current form correction should be adjusted or as a distance to which each side of the current form correction should be adjusted. For example, the look-up table may include a +10 nm vertical deviation estimate for the feature to a 5% increase for the feature correction, a +5 nm vertical deviation estimate for the feature to a 2% increase for each side of the feature correction, and others. Can be correlated.

  The look-up table used in step 2235 can, for example, run simulations on various forms (with corrections) with various vertical deviations, and any changes in the effects of vertical deviation on the forms and form modifications to be made. Can be created by judging. For example, by simulation, it can be determined that if the feature deviates in the +10 nm vertical direction, the feature is pushed inward by 5 nm, and therefore 5 nm is required for a particular side of the feature correction. Therefore, these determination results are reflected in the lookup table. The above-described form of simulation can be performed by a simulator program that takes into account lens out-of-focus processing variations, where the level of lens out-of-focus is related to the level of form vertical deviation (as described above). .

  In some embodiments, the method does not determine an estimate of the vertical deviation (at 2230), but instead makes a modification change to the current form directly to the geometric range percentage in the corresponding subregion of the underlying layout. Judging from. This may, for example, enumerate a set of rules for a given lookup table that enumerate the various geometric range percentages of the underlying layout and correlate each geometric range percentage to a particular change to be applied to the shape modification. Can be done using. For example, a look-up table can correlate a 30% geometry range with a 2 nm correction increase.

  After the method 2200 determines a change to the current form modification (at 2235), the method 2200 then applies the change to the current form modification (at 2240). Next, the method determines (at 2245) whether the current form is the final form of the top layout. If not, the method proceeds to step 2220 and selects the next current form (with modifications) in the top layout for processing. If so, the method ends.

  Some methods of the present invention can be adapted to incorporate some of the processing features of the modified method 2200 of FIG. For example, a general design method 300 for designing an integrated circuit layout (described above in connection with FIG. 3) can be so adapted. For example, after step 325 of the general design method 300, a satisfactory layout that produces a satisfactory simulated layout is achieved, and the satisfactory layout has a form with modifications. Assuming that a satisfactory one is designed for the IC top layout, then the modification method 2200 of FIG. 22 can be used to change the form modification in the satisfactory layout, the change being Based on information related to the layout designed for the lower layer.

  A layout modification method 700 (described above in connection with FIG. 7) that uses a library of pre-tabulation models to modify the geometry in the IC layout can be adapted as such. For example, after step 735 of layout modification method 700, a design layout is generated having pre-tabulation modifications applied to features in the design layout. Next, assuming that the design layout is designed with respect to the IC upper layout, the pre-tabulation correction for the form in the design layout can be changed using the change method 2200 of FIG. , Based on information related to the lower layer of the IC.

  A library construction method 800 for constructing a library of pre-tabulation models (described above in connection with FIG. 8) can also be adapted to change the pre-tabulation modification of the pre-tabulation model. For this embodiment, it can be assumed that the pre-tabulation model of the library includes a form designed for the layout for the IC upper layer. After step 825 of the library construction method 800, a modification to the form that produces a satisfactory simulated form is achieved, and this modification is referred to as a pre-tabulation modification (at 830) stored in the model.

  In some embodiments, the library construction method 800 may include various examples of geometric range percentages (eg, 5%, 10%, etc.) that may exist in the layout designed for the IC bottom layer after step 825. %, 15%, etc.). For each example of the geometric shape range, a change in pre-tabulation correction is determined. This can be done by determining the vertical deviation resulting from each geometric shape range (eg, using a look-up table as described above in connection with FIG. 22) and then based on the vertical deviation. To determine the change (eg, using a look-up table as described above in connection with FIG. 22). Each pre-tabulation change is then stored in a separate model, along with the geometric range percentage to which the change applies.

  In this way, some or all of the model is partly related to the information related to the layout designed for the IC lower layer (ie, the layer that will be created in a lower layer than the form). A pre-tabulated library of models can be created that includes morphological modifications based on it. In some embodiments, the information related to the bottom layout is a geometric range percentage in the bottom layout. In some embodiments, a pre-tabulated library of models is created in which some or all models contain modifications to the morphology based in part on the morphology relief data (vertical deviation data).

FIG. 24 conceptually illustrates a computer system with which some embodiments of the invention are implemented. The computer system 2400 includes a bus 2405, a processor 2410, a system memory 2415, a read only memory 2420, a permanent storage device 2425, an input device 2430, and an output device 2435.
Bus 2405 collectively represents all system buses, peripheral buses, and chipset buses that support communication between internal devices of computer system 2400. For example, bus 2405 connects processor 2410 to read-only memory 2420, system memory 2415, and permanent storage 2425 for communication.

  From these various memory devices, the processor 2410 retrieves instructions to execute and data to process in order to perform the processing of the present invention. Read only memory (ROM) 2420 stores static data and instructions required by processor 2410 and other modules of the computer system. On the other hand, the permanent storage device 2425 is a read / write memory device. This device is a non-volatile memory device that stores instructions and data even when the computer system 2400 is off. In some embodiments of the present invention, a mass storage device (such as a magnetic disk or optical disk and a corresponding disk drive) is used as the permanent storage device 2425. In other embodiments, a removable storage device (such as a floppy or “zip” disk and its corresponding disk drive) is used as the permanent storage device.

  Similar to the permanent storage device 2425, the system memory 2415 is a read / write memory device. However, unlike the permanent storage device 2425, the system memory is a volatile read / write memory such as a random access memory. The system memory stores some of the instructions and data required by the processor during execution. In some embodiments, the processing of the present invention is stored in system memory 2415, permanent storage 2425, and / or read only memory 2420.

  Bus 2405 is also connected to input device 2430 and output device 2435. The input device allows a user to communicate information to the computer system or select instructions for the computer system. The input device 2430 includes an alphanumeric keyboard and a cursor controller. The output device 2435 displays an image generated by the computer system. For example, these devices display an IC design layout. Output devices include printers and display devices such as cathode ray tubes (CRT) or liquid crystal displays (LCD).

Finally, as shown in FIG. 24, bus 2405 also couples computer 2400 to network 2465 through a network adapter (not shown). In this way, the computer can be part of a network of computers (such as a local area network (LAN), a wide area network (WAN), or an “intranet”), or a network of networks (such as the Internet). Any or all of the components of computer system 2400 may be used with the present invention. However, those skilled in the art will appreciate that any other system configuration can be used with the present invention.
Although the invention has been described with reference to numerous specific details, those skilled in the art will recognize that the invention can be embodied in other specific forms without departing from the spirit of the invention. Let's go. That is, one of ordinary skill in the art appreciates that the invention is not limited by the illustrative details described above, but rather is defined by the claims.

FIG. 6 illustrates an example of variations that may occur between the initial geometry designed in the IC layout and the fabrication geometry actually generated on the wafer. FIG. 4 is a diagram illustrating an example of a correction geometry placed on an initial geometry and a fabrication geometry actually generated on a wafer. 2 is a flowchart of a general design method for designing an integrated circuit layout. FIG. 2 is a top view of a sub-region of a layout that includes geometric shapes representing various IC elements such as circuit modules, interconnect lines, or via pads that are to be fabricated on a wafer. FIG. 5 is a top view of a sub-region of a layout that includes a main geometry including a current form and an environment surrounding the current form. FIG. 6 is a conceptual diagram of a model that includes descriptive data of a pre-tabulation environment that conforms to the layout environment of FIG. 5 and is stored in a model pre-tabulation library. 6 is a flowchart of a layout correction method for correcting a geometric shape in an IC layout using a library of pre-tabulation models. It is a flowchart of the method of building the library of a pre-tabulation model. It is a figure which shows the example of the environment which can be produced with respect to a Manhattan priority wiring layout. It is a figure which shows the example of the environment which can be produced with respect to a Manhattan priority wiring layout. It is a figure which shows the example of the environment which can be produced with respect to a Manhattan priority wiring layout. It is a figure which shows the example of the environment which can be produced with respect to a Manhattan priority wiring layout. It is a figure which shows the example of the environment which can be produced with respect to a Manhattan priority wiring layout. It is a figure which shows the example of the environment which can be created for Manhattan priority wiring layout. It is a figure which shows the example of the environment which can be produced with respect to a diagonal priority wiring layout. It is a figure which shows the example of the environment which can be produced with respect to a diagonal priority wiring layout. It is a figure which shows the example of the environment which can be produced with respect to a diagonal priority wiring layout. It is a figure which shows the example of the environment which can be produced with respect to an analog design layout. It is a figure which shows the example of the environment which can be produced with respect to an analog design layout. It is a figure which shows the example of the environment which can be produced with respect to an analog design layout. FIG. 5 is a flow diagram of an adaptation method for identifying a model that accommodates a pre-tabulated environment that conforms to a layout environment. FIG. 6 illustrates one of eight different orientations of a layout environment 1305 where each orientation is equivalent. FIG. 6 illustrates one of eight different orientations of a layout environment 1305 where each orientation is equivalent. FIG. 6 illustrates one of eight different orientations of a layout environment 1305 where each orientation is equivalent. FIG. 6 illustrates one of eight different orientations of a layout environment 1305 where each orientation is equivalent. FIG. 6 illustrates one of eight different orientations of a layout environment 1305 where each orientation is equivalent. FIG. 6 illustrates one of eight different orientations of a layout environment 1305 where each orientation is equivalent. FIG. 6 illustrates one of eight different orientations of a layout environment 1305 where each orientation is equivalent. FIG. 6 illustrates one of eight different orientations of a layout environment 1305 where each orientation is equivalent. FIG. 6 is a flow diagram of an alternative layout modification method that uses a library of pre-tabulation models to modify geometric shapes in an IC layout. It is a conceptual diagram of the data stored in the model of a pre-tabulation library. FIG. 10 is a flow chart of an alternative library construction method for constructing a pre-tabulated library of models in which each model accommodates simulated environment data and / or re-simulated environment data. It is a figure which shows the simulation result of the prior tabulation environment which does not reflect any process fluctuations. It is a figure which shows the simulation result of the same pre-tabulation environment as FIG. 17A which considered one or more processing fluctuations. 3 is a flowchart of an alternative library construction method for generating a library including a predetermined capacitance equation. 5 is a flow diagram of an adjustment method for modifying a geometry in an IC layout using a library of pre-tabulated models with predetermined adjustment equations or functions. FIG. 4 is a top view of a sub-region of a layout that includes various geometric shapes and a current form and three radial regions surrounding the current form. Fig. 5 is a flow diagram of an alternative library construction method used to generate a library that includes predetermined adjustment equations or functions. FIG. 5 is a flow diagram of a change method for changing a modification to a geometry in a layout for an upper layer of an IC using information related to the layout for the lower layer of the IC. It is a top view of a part of the lower layout divided into sub-regions. FIG. 6 is a conceptual diagram of a computer system in which some embodiments of the present invention are implemented.

Explanation of symbols

405 Layout sub-region 410 Geometric shape 415 Form

Claims (38)

Use a library of models where each model in the library contains a pre-tabulation environment, a pre-tabulation modification to the pre-tabulation form, and a pre-tabulation environment consisting of one or more pre-tabulation geometries A method for modifying a layout including a plurality of geometric shapes each having a set of forms for modifying the layout,
a) selecting a current form in the layout;
b) identifying a current environment in the layout containing the current form;
c) identifying a model in the library having a pre-tabulated environment that matches the current environment;
d) retrieving a pre-tabulation correction from said conforming model;
e) applying the pre-tabulation correction to the current form;
Only contains the models in advance certain electrical characteristics of the tabulated environment includes a characteristic equation expressed as one or a function of many process variations than,
Further, wherein the free Mukoto the step of searching the characteristic equation from the correct model. Repeating steps a) to e) for each form in the layout;
The method of claim 1 further comprising:   The method of claim 1, wherein the pre-tabulation correction is designed to generate a production form that is within a predetermined variance from the current form.   The method according to claim 1, wherein the pre-tabulation modification generates a simulated form that is within a predetermined distribution from the pre-tabulation form. After selecting the current form, determining whether the current form is located within a processing region;
Selecting another current form in the layout when it is determined that the current form is located within a processing region;
Identifying a processing region with respect to the current form after applying the pre-tabulation correction to the current form;
The method of claim 1 further comprising:   The method of claim 1, wherein the current form is a geometric corner, bend, or line-point in the layout.   The method of claim 1, wherein the geometry in the layout represents an element to be created on a wafer. The current environment contains one or more geometric shapes;
Identifying the model in the library having a pre-tabulated environment that matches the current environment comprises:
Identifies a pre-tabulated environment containing one or more geometric shapes having dimensions and arrangements that match the dimensions and arrangements of one or more geometric shapes within the current environment Stage,
including,
The method according to claim 1.   The method of claim 1, wherein the adapted model includes a pre-tabulated environment that is within a predetermined distribution from the current environment. After identifying the current environment in the layout, determining whether any model in the library has a pre-tabulated environment that matches the current environment;
If any model in the library is determined not to have a pre-tabulated environment that is compatible with the current environment, using a rule-based approach to determine modifications to the current form;
The method of claim 1 further comprising: After identifying the current environment in the layout, determining whether any model in the library has a pre-tabulated environment that matches the current environment;
If it is determined that none of the models in the library has a pre-tabulated environment that matches the current environment, a pre-tabulated environment that duplicates the current environment and a prior that duplicates the current form Creating a new model in the library with pre-tabulation corrections to the tabulation form;
The method of claim 1 further comprising: The library of models is created and the layout is modified at the same time,
The library includes only models that have a pre-tabulated environment that duplicates the environment previously identified in the layout during modification of the layout;
The method according to claim 11. Each model further includes a simulated environment that is a simulation of the pre-tabulated environment reflecting one or more process variations;
Retrieving the simulated environment from the adapted model;
The method of claim 1 further comprising: Each model further includes a description of the electrical characteristics of the pre-tabulated environment,
Retrieving the electrical characteristics from the fitted model;
The method of claim 1 further comprising: Each model further includes a characteristic equation that represents a particular electrical characteristic of the pre-tabulated environment as a function of one or more process variations;
Retrieving the characteristic equation from the fitted model;
The method of claim 1 further comprising: Each model further includes a characteristic equation that represents specific electrical characteristics of the pre-tabulation environment as a function of the size and placement of the one or more geometric shapes within the pre-tabulation environment;
Retrieving the characteristic equation from the fitted model;
The method of claim 1 further comprising: Each model further includes an adjustment equation or function used to determine adjustments to the pre-tabulation correction in the model;
Retrieving the accommodation equation or function from the fitted model;
The method of claim 1 further comprising: The adjustment equation or function uses at least one geometric range percentage of a specific area in the layout;
Determining at least one geometric range percentage of an area in the layout specified by the adjustment equation or function after retrieving the pre-tabulation correction and the adjustment equation or function;
Determining an adjustment using the adjustment equation and the at least one geometric range extent;
Applying the adjustment to the pre-tabulation correction and applying the pre-tabulation correction to the current form includes applying the adjusted pre-tabulation correction to the current form. Stages,
The method of claim 17, further comprising:   The method of claim 18, wherein the area in the layout specified in the adjustment equation or function is a region between an inner predetermined radial distance and an outer predetermined radial distance from the current configuration. . Designed to have multiple forms and multiple modifications to the form and be fabricated on the first layer of the integrated circuit after repeating steps a) to e) for each form in the layout Modified layout is generated,
Changing the modified layout using data associated with a second layout designed to be fabricated on a second layer of the integrated circuit;
The method of claim 2, further comprising: The second layer is lower than the first layer in the integrated circuit;
The step of changing includes
Using the data associated with the second layout to generate a density map of the second layout indicating a geometric range percentage in a sub-region of the second layout;
Selecting a current form having a current modification in the modified layout;
Retrieving the geometric range percentage of the sub-region of the second layout designed to be created under the current form from the density map;
Determining a change to the current modification of the current form based on the geometric shape range percentage;
Applying the change to the current modification of the current form;
including,
21. The method of claim 20, wherein: Determining the change to the current modification includes
Determining an estimate of a vertical deviation of the current form based on the geometric shape range percentage;
Determining the change to the current correction based on the vertical deviation;
including,
The method according to claim 21, wherein: A method of creating a library of models used to modify a layout,
Creating a set of pre-tabulation environments each containing a pre-tabulation form and one or more pre-tabulation geometries, and for each pre-tabulation environment in the set ,
Creating a pre-tabulation correction for a pre-tabulation form in the pre-tabulation environment that generates a satisfactory simulation of the pre-tabulation environment; and the pre-tabulation form, the pre-tabulation correction, and the one Creating a model of said pre-tabulation environment consisting of or more pre-tabulation geometries; and
For each pre-tabulation environment in the set, the electricity of the pre-tabulation environment as a function of the size and placement of one or more pre-tabulated geometric shapes in the pre-tabulation environment A method comprising storing a characteristic equation representing a characteristic in the model created for the pre-tabulation environment .   24. The method of claim 23, wherein the set of pre-tabulation environments is adjusted to a layout having a specific preferred direction wiring.   25. The method of claim 24, wherein the priority direction wiring is Manhattan or oblique priority direction wiring.   24. The method of claim 23, wherein the set of pre-tabulation environments is adjusted to a layout that does not have a specific preferred direction wiring. Storing, for each pre-tabulated environment in the set, the satisfactory simulation of the pre-tabulated environment in the model created for the pre-tabulated environment;
24. The method of claim 23, further comprising: For each pre-tabulated environment in the set,
Generating a re-simulation of the pre-tabulation environment having the pre-tabulation modifications created for the pre-tabulation environment and reflecting one or more process variations;
Storing the re-simulation of the pre-tabulation environment in the model created for the pre-tabulation environment;
24. The method of claim 23, further comprising:   24. The method of claim 23, wherein the one or more process variations are lens defocus or light dose. For each pre-tabulated environment in the set, storing electrical property data of the pre-tabulated environment in the model created for the pre-tabulated environment;
24. The method of claim 23, further comprising:   The method of claim 30, wherein the electrical property data is related to capacitance, inductance, or resistance. The electrical characteristic is capacitance, and the characteristic equation is
C = C ₀ + k ₁ ΔW
Where C is the capacitance between two geometries in the re-simulation of the pre-tabulated environment that reflects one or more process variations, and C ₀ is The initial capacitance between the two geometries of the simulation of the pre-tabulated environment that does not reflect process variations, k ₁ is a predetermined factor, and ΔW is the 2 from the re-simulation to the simulation The method of claim 23, wherein the method is a difference in distance between two geometric shapes. For each pre-tabulation environment in the set, a characteristic equation was created for the pre-tabulation environment that represents the electrical properties of the pre-tabulation environment as a function of one or more process variations. Storing in the model;
24. The method of claim 23, further comprising: The electrical characteristic is capacitance, and the characteristic equation is
C = C ₀ + k ₁ ΔW + k ₂ ΔPV ₁ +. . .
Where C is the capacitance between two geometries in the re-simulation of the pre-tabulated environment that reflects one or more process variations, and C ₀ is The initial capacitance between the two geometries of the pre-tabulation environment simulation that does not reflect process variations, k ₁ and k ₂ are predetermined coefficients, and ΔW is from the re-simulation to the simulation 34. The method of claim 33, wherein the difference in distance between the two geometries is ΔPV ₁ is the difference in the values of process variations reflected in the re-simulation and the simulation. . The characteristic equation is
C = C ₀ + k ₁ ΔW + k ₂ ΔDF + k ₃ ΔDose form, where C is the two geometries in the re-simulation of the pre-tabulated environment reflecting one or more process variations C ₀ is the initial capacitance between the two geometries of the simulation of the pre-tabulated environment that does not reflect process variation, and k ₁ , k ₂ , and k ₃ are A predetermined coefficient, ΔW is the difference in distance between the two geometries from the re-simulation to the simulation, and ΔDF is the difference in defocus values reflected in the re-simulation and the simulation 34. The method of claim 33, wherein the [Delta] dose is a difference in light dose values reflected in the re-simulation and the simulation. For each pre-tabulation environment in the set, an adjustment equation or function used to determine adjustments to the pre-tabulation modification created for the pre-tabulation environment is stored in the pre-tabulation environment. Storing in the model created for,
24. The method of claim 23, further comprising:   The method of claim 36, wherein the adjustment equation or function determines the adjustment to the pre-tabulation correction using at least one geometric range percentage of a particular area in the layout. For each pre-tabulated environment in the set,
One or more geometric shape ranges of a specific area having the pre-tabulation modification created for the pre-tabulation environment and surrounding the pre-tabulation form in the pre-tabulation environment Generating a re-simulation of the pre-tabulated environment reflecting the percentage;
Determining a total adjustment applied to the pre-tabulation modification created for the pre-tabulation environment that generates a satisfactory re-simulation of the pre-tabulation environment;
Storing the total adjustment and the one or more geometric range percentages as exemplary results;
Determining all of the exemplary results and determining an adjustment equation or function that represents how the total adjustment is derived from the one or more geometric range values;
Storing the accommodation equation or function in the model created for the pre-tabulation environment;
24. The method of claim 23, further comprising:

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