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  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/28008—Making conductor-insulator-semiconductor electrodes
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  • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
  • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
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  • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
  • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
  • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
  • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
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  • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
  • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
  • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
  • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
  • H01L21/02192—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
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  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
  • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
  • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
  • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
  • H01L21/02194—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing more than one metal element
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  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
  • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
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  • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
  • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
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  • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
  • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials

Definitions

• This invention relates to devices used in and methods for making integrated circuits, and more particularly to high K dielectrics used in making integrated circuits.
• CMOS devices contain both n- and p- channel field effect transistors (FET) and form the basis of integrated circuits. These transistors are metal oxide-based semiconductor devices which include a source and drain region and an insulated gate in between. As the density of integrated circuits and performance increases, the dimensions of the transistors have to be reduced. As a result the thickness of the insulated gate dielectric layer has to be made smaller.
• FET field effect transistor
• one of the desirable features of the dielectric layer is that it couple the overlying gate electrode to the underlying channel so that the channel is responsive to the stimulus applied to the gate. In this regard it is desirable for that dielectric to have a high dielectric constant commonly known as high K. Silicon dioxide has been by far, the most common and effective gate insulator used in making integrated circuits.
• La-based oxide materials can potentially be used as a high K dielectric for Si CMOS devices. Such oxides have higher dielectric constant than Si0 2 and are predicted to be thermodynamically stable in contact with silicon.
• An alternative to amorphous is monocrystalline films. In theory, high K dielectric films can be made typically monocrystalline, although difficulties exist. One such difficulty is matching the crystalline structure of the film with that of the underlying semiconductor, typically silicon, as well as during the formation process that it be in fact perfectly formed. Epitaxial layers, that is layers that are monocrystalline, are known in the industry.
• Silicon can be made epitaxially.
• One of the techniques by which very thin films can be put down in a monocrystalline form is molecular beam epitaxy. Even with using MBE technology there is still the difficulty of ensuring defect free films.
• MBE technology Even with using MBE technology there is still the difficulty of ensuring defect free films.
• In developing new high K dielectrics there is also another potential problem of having too high of a dielectric constant. If the dielectric constant is too high, there is an effect that is called fringing field effect which adversely affects the performance of the transistor. This has to do with excessive coupling between the gate and the source/drain.
• the materials that are being developed desirably have a range typically between 20 and 40 for the dielectric constant. This range may change somewhat as the technology develops further.
• Another aspect of a desirable high K dielectric is in terms of its equivalent capacitance to that of a certain thickness of silicon oxide.
• Silicon oxide has been so commonly and effectively used that it has become a standard and the industry often describes certain characteristics in terms of its relationship to silicon oxide.
• the typical desirable silicon oxide equivalent thickness is between 5 and 15 angstroms but with silicon oxide of 5 to 15 angstroms it has problems with leakage, reliability, growth rate, and uniformity.
• the desirable coupling is to have a dielectric that has the equivalence of the thickness of 5 to 15 angstroms of silicon oxide but a greater actual thickness.
• High K dielectric films which include aluminum have been developed, yet aluminum is known to cause high interface state density and degraded mobility in silicon based devices.
• a dielectric film which has a dielectric constant within a desirable range, the ability to be made of high integrity, a thickness in a desirable range, does not degrade mobility or cause high interface state densities, and has the ability to be made in a manufacturing process.
• a semiconductor structure and method of fabricating the semiconductor structure which includes providing a semiconductor substrate; providing a dielectric layer comprising lanthanum, lutetium, and oxygen over the semiconductor substrate; and providing an electrode layer over the dielectric layer.
• FIG. 1 is a cross section of a portion of an integrated circuit according to a first embodiment of the invention
• FIG. 2 is a cross section of a portion of an integrated circuit according to a second embodiment of the invention.
• FIG. 3 is a cross section of a portion of an integrated circuit according to a third embodiment of the invention.
• FIG. 4 is a cross section of a portion of an integrated circuit according to a fourth embodiment of the invention.
• FIG. 5 is a cross section of a portion of an integrated circuit according to a fifth embodiment of the invention.
• FIG. 6 is a cross section of a portion of an integrated circuit according to a sixth embodiment of the invention.
• Fig. 7 is a transmission electron micrograph of a 5 ⁇ A LaLu0 3 layer deposited on silicon according to the present invention after annealing at 700 degrees C;
• Fig. 8 shows a Rutherford Backscattering Spectra of a 50A as deposited LaLu0 3 layer deposited at 200 degree C on silicon according to the present invention;
• Fig. 9 illustrates graphically the C-V curves for a 5 ⁇ A LaLu0 3 layer deposited on silicon at 200 degree C.
• a high K dielectric film comprising lanthanum, lutetium, and oxygen provides an excellent candidate material for replacement of silicon dioxide. It combines the advantages of having a desirable range of dielectric constant, the ability to remain amorphous at high temperatures, and provides for low leakage.
• FIG. 1 Shown in FIG. 1 is a portion 10 of an integrated circuit having a substrate 12 of semiconductor material, a dielectric film 14 and a conductive film 16.
• Substrate 12 has a semiconductor region at least at a surface thereof.
• the underlying portion can either be also semiconductive material or it can be insulative material which is typical for SOI. Examples of semiconductive material include monocrystalline silicon, and gallium arsenide.
• Over and on substrate 12 is dielectric layer 14.
• conductive film 16 which functions as a gate electrode.
• Dielectric layer 14 operates as a gate insulator or gate dielectric.
• Substrate 12, as shown here at the area near the surface at the interface with dielectric film 14, is a channel of a transistor.
• Gate dielectric 14 comprises lanthanum lutetium oxide which is a compound comprising lanthanum, lutetium, and oxygen.
• the formula is written as LaLu0 3 with the concentration of lanthanum and lutetium being the same.
• the formula is written as La(Al) x Lu ⁇ . x 0 3 where x>0.
• Lanthanum lutetium oxide is disclosed as having a dielectric constant of approximately 25 and a bandgap of more than 5eV. As a result, successful deposition of lanthanum lutetium oxide on substrate 14, such as a silicon substrate, makes this material suitable for gate dielectric application.
• Gate dielectric 14, as disclosed herein, is preferably formed using molecular beam epitaxy (MBE) in which the individual elements are evaporated from thermal sources.
• MBE molecular beam epitaxy
• the elements can be generated using e-beam deposition, atomic layer chemical vapor deposition (ALCVD), physical vapor deposition, organometallic chemical vapor deposition, and pulsed laser deposition.
• ACVD atomic layer chemical vapor deposition
• the preferred approach is MBE which allows for precise control of the formation of the layer including thickness, which in this case is not less than about 15 angstroms and preferably in the range of 20 to 100 angstroms.
• 16 in current integrated circuit technology is typically polysilicon but can be other conductors such as a metal including, but not limited to, tungsten, Ti-nitride, tantalum nitride, or any conductor useful as a gate conductor.
• the gate dielectric 14 being deposited by MBE is also useful in ensuring that the film is deposited in an amorphous condition.
• the surface of substrate 12 is either initially cleaned so that it is free of the native silicon oxide layer, or a thin layer of silicon oxide or silicon oxynitride may be present (discussed presently). It is anticipated by this disclosure that the surface of substrate 12 is cleaned and thermally heated to remove contaminants, prior to the deposition of the lanthanum lutetium oxide, thereby providing for less process steps by maintaining the silicon substrate and silicon oxide interface.
• the native oxide may be thermally removed prior to deposition of the lanthanum lutetium oxide by heating in UHV conditions or alternatively by using a Si-assisted desorption process or a Sr-assisted desorption process.
• a clean surface increases the capacitance of the dielectric stack and results in an increased ability to scale the device to lesser dimensions
• the native oxide may be removed and the surface treated by oxygen and nitrogen to form a silicon oxynitride on the surface of substrate 12, prior to deposition of the lanthanum lutetium oxide.
• This formation of a silicon oxynitride on the surface provides for an interface between the substrate and gate dielectric 14 having a higher dielectric constant than an interface with Si0 2 .
• molecular oxygen is controllably introduced into a reaction chamber using an orifice or a plasma source where it is possible to use activated oxygen atomic species.
• the introduction of lanthanum and lutetium with the oxygen thus forms a single layer of lanthanum lutetium oxide as dielectric layer 14, overlying substratel2.
• This lanthanum lutetium oxide provides benefit in the area of optimizing the dielectric coefficient for low leakage and increased capacitance.
• Some other materials have identifiable deficiencies.
• a binary compound of lanthanum oxide has a dielectric constant that is in the right range but it absorbs water. The absorption of water is very detrimental to desirable manufacturing of integrated circuits.
• the absorption of water by lanthanum oxide results in structural integrity problems making it unusable in forming an integrated circuit structure.
• the introduction of lutetium provides for a very stable gate dielectric, that remains amorphous and does not recrystallize at high temperature and thus remains stable when in contact with substrate 12.
• lanthanum lutetium oxide provides for a high band gap, being greater than 5eV, with reasonable band offset, a dielectric constant of approximately 25, and a coefficient of thermal expansion that is similar to silicon.
• dielectric constant can be varied based upon the extent of the lanthanum content and the lutetium content.
• an optimized dielectric constant is achieved somewhere between 10 and 25. Even somewhat greater coefficients can be obtained where the lanthanum content relative to the lutetium content is varied, but this may result in problems associated with water absorption.
• the lanthanum lutetium oxide advantageously remains amorphous even at temperatures up to 1,025 and perhaps even more. 1,025 degrees Celsius is a typical highest temperature for current manufacturing processes. Thus, lanthanum lutetium oxide has been found to withstand the highest temperature that will be received during processing of an integrated circuit that is made by many typical processes for the most advanced geometries and remain amorphous. The desire is for maximum processing temperatures to drop some, but maximum temperatures will likely remain fairly high because the activation of dopants in the source/drains requires a high temperature and such activation is expected to be a requirement for the foreseeable future. Maximum temperatures may drop somewhat below 1,025 but will still be expected to be over 900 degrees Celsius for at least quite some time.
• the amorphous lanthanum lutetium oxide provides the desirable high K characteristics and high integrity over anticipated temperature ranges.
• Another benefit of being able to deposit the effective high K dielectric film of amorphous lanthanum lutetium oxide is that it can be very effective, not just on silicon, but also on gallium arsenide.
• One of the problems in effectively implementing gallium arsenide CMOS technology thus taking advantage of its higher mobility, is that the gate dielectrics used in gallium arsenide are very difficult to match the integrity of those of silicon, which are achieved by growing silicon oxide at high temperature.
• FIG. 2 Shown in FIG. 2 is a portion 18 of an integrated circuit comprising a substrate 20, a barrier dielectric 22, a high K dielectric 24, and a conductor 26.
• high K dielectric 24 is similar or analogous to film 14 of FIG. 1 in that it is lanthanum lutetium oxide.
• Conductor 26 is analogous to conductor 16 and substrate 20 is analogous to substrate 12 in FIG. 1 having one of a clean surface, a remaining native oxide on the surface, or oxynitride present on the surface, as previously described.
• Barrier dielectric 22, which may also be referred to as an interfacial layer, is chosen for its desirable characteristics as an insulator. This may be, for example, lanthanum oxide, lutetium oxide, silicon oxide or silicon oxynitride. Barrier dielectric 22 is present to insure that the combination of high K dielectric 24 and barrier dielectric 22 have sufficient insulation characteristics to prevent unwanted current flow. For example, the combination would have a high bandgap and would have a sufficiently high dielectric constant.
• barrier dielectric 22 is as a diffusion barrier if the material chosen for substrate 20 has a problem or reaction with lanthanum lutetium oxide.
• FIG. 3 Shown in FIG. 3 is a portion 28 of an integrated circuit comprising a substrate 30, a dielectric film 32, and a conductor 34.
• substrate 30 is analogous to substrates 20 and 12 and conductor 34 is analogous to conductors 26 and 16.
• Dielectric film 32 substitutes for dielectric 14 and for the combination of dielectrics 22 and 24. In this case dielectric film
• lanthanum or lutetium has a graded concentration of lanthanum or lutetium, meaning a binary material, namely lanthanum oxide or lutetium oxide, is formed adjacent the interface of substrate 30 and dielectric film 32 and graded to a ternary material, namely lanthanum lutetium oxide, as the layer interfaces with conductor 24 through the addition of either lanthanum or lutetium.
• a binary material namely lanthanum oxide or lutetium oxide
• a ternary material namely lanthanum lutetium oxide
• the concentration of lutetium continuously increases until there is a 1 to 1 ratio between lanthanum and lutetium in the dielectric film 32 near the interface with conductor 34.
• the concentration of lanthanum continuously increases until there is a 1 to 1 ratio between lanthanum and lutetium in the dielectric film 32 near the interface with conductor 34.
• the resulting dielectric constant can be adjusted as well by controlling the rate at which the concentration is increased, that is the 1 to 1 ratio between lanthanum and lutetium can be achieved well before the interface with conductor 34.
• An alternative is for the grading to continue past the one to one ratio so that the concentration of lanthanum exceeds the concentration of lutetium, or vice versa.
• Shown in FIG. 4 is a portion 36 of an integrated circuit comprising a substrate 40, a barrier dielectric 42, a high K dielectric 44, a barrier dielectric 46 and a conductor 48.
• the substrate 40 is analogous to substrates 12, 20 and 30.
• Barrier dielectric 42 is analogous to barrier dielectric 22.
• High K dielectric 44 is analogous to high K dielectrics 14 and 24.
• Conductor 48 is analogous to conductors 16, 26 and 34.
• Barrier layer 46 provides a barrier between high K dielectric 44 and conductor 48.
• Barrier 46 is for the case in which conductor 48 has a compatibility problem with high K dielectric 44.
• Barrier 46 would be chosen most likely also among lanthanum oxide, lutetium oxide, silicon oxide, and silicon oxynitride.
• barrier dielectric 46 would be to provide a diffusion barrier between conductor 48 and high K dielectric 44.
• barrier layer 46 it would be desirable for barrier layer 46 to have a high dielectric constant, but its purpose is to prevent problems between conductor 48 and high K dielectric 44.
• a preferred choice is likely to be either lanthanum oxide or lutetium oxide because they have higher dielectric constants than silicon oxide.
• FIG. 5 Shown in FIG. 5 is a portion 50 of an integrated circuit comprising a conductor 52, a high K dielectric 54 and a conductor 56.
• the applicability of the high K dielectric is between two conductors. This arises primarily in the case where conductor 52 is a floating gate for storing charge. It can also come up in situations where 52 and 56 comprise capacitor plates which are utilized for storing charge.
• conductor 52 is a floating gate for storing charge. It can also come up in situations where 52 and 56 comprise capacitor plates which are utilized for storing charge.
• One such example is the memory cell of a dynamic random access memory.
• high K dielectric 54 is lanthanum lutetium oxide having a graded concentration.
• concentration of lanthanum is maximized in the middle whereas pure or nearly pure lutetium oxide is at the interface with conductor 52 and at the interface of conductor 56.
• This provides for the relatively high dielectric constant and for high band gap at both the interface with conductor 52 and the interface with conductor 56 so that it is both a high K dielectric and an excellent insulator.
• the sharp interfaces between insulator types is avoided. Sharp transitions between material types tend to be places where charge can be trapped. With a graded concentration the sharp interfaces are avoided.
• FIG. 6 Shown in FIG. 6 is a portion 60 of an integrated circuit comprising a conductor 62, a barrier dielectric 64, a high K dielectric 66, a barrier dielectric 68 and a conductor 70. This is an analogous structure to FIG. 5.
• Conductor 62 is analogous to conductor 52 and conductor
• dielectric layers 64 and 68 operate both to provide high band gap and as a diffusion barrier between conductors 62 and 70 and high K dielectric 66.
• barrier layers 64 and 68 may be necessary both for sufficient insulation quality as well as providing diffusion barrier to high K dielectric 66.
• Conductors 62 and 70 may have different characteristics. One may be polysilicon. The other may be a metal in which case the type of barrier dielectric may be desirably different.
• High K dielectric 66 comprises lanthanum lutetium oxide having the benefits described for lanthanum lutetium oxide for film for the structures of FIGS. 1-5.
• the likelihood that barriers will be required in the case of two conductors as distinct from the formation of a transistor is increased because it is, in fact, desirable for injection to occur between conductors 62 and 70 in some circumstances.
• the likelihood of needing barriers 64 and 68, or grading as in FIG. 5, so that such injection does not occur when it is undesirable for it to occur is more likely to be a situation that actually happens.
• the likelihood of needing barriers 64 and 68, or the grading shown in FIG. 5 is greater in the case where there is a storage of charge by injection.
• the primary purpose of a capacitor is storing charge so that the importance of having high band gap at the interface to the conductor may be more important than even for a transistor.
• the following example illustrates a method, in accordance with one embodiment of the invention, for fabricating a semiconductor structure such as structure 10 depicted in FIG.
• the method starts by providing a monocrystalline semiconductor substrate comprising a material selected from Group IV or Group ⁇ i-V of the periodic table.
• the semiconductor substrate is a silicon wafer having a (100) orientation. At least a portion of the semiconductor substrate has a bare surface, although other portions of the substrate, as described below, may encompass other structures.
• bare in this context means that the surface in the portion of the substrate has been cleaned to remove any oxides, contaminants, or other foreign material.
• bare silicon is highly reactive and readily forms a native oxide.
• the term “bare” is intended to encompass such a native oxide.
• the following process is preferably carried out by molecular beam epitaxy (MBE), although other deposition processes including physical vapor deposition, atomic layer deposition or metalorganic chemical vapor deposition may also be used in accordance with the present invention.
• MBE molecular beam epitaxy
• the native oxide is removed by heating the substrate to temperatures greater than 800 degrees C in the MBE chamber.
• a clean silicon surface displays a (2x1) surface reconstruction as monitored by reflection high energy electron diffraction (RHEED).
• the native oxide is removed by depositing a thin layer (preferably 1-3 monolayers) of strontium, barium, a combination of strontium and barium, or other alkaline earth metals or combinations of alkaline earth metals in an MBE apparatus and heating it to temperatures in excess of 750 degrees C.
• a thin layer preferably 1-3 monolayers of strontium, barium, a combination of strontium and barium, or other alkaline earth metals or combinations of alkaline earth metals in an MBE apparatus and heating it to temperatures in excess of 750 degrees C.
• the temperature of the substrate is lowered to between room temperature and 500 degrees C, preferably 50 to 400 degrees C.
• Oxygen in then introduced into the MBE chamber directed towards the cleaned substrate.
• the shutters on the effusion sources are opened to allow atoms of lanthanum and lutetium to impinge upon the semiconductor substrate forming layer 14 of lanthanum lutetium oxide.
• aluminum can be introduced to form a layer of lanthanum aluminum lutetium oxide.
• a gate electrode is deposited by physical vapor deposition or by any other deposition techniques as is known in the art. Shown in FIG.
• FIG. 7 is a transmission electron micrograph 80 of a 5 ⁇ A thick LaLu0 3 layer deposited on Si at 200 degrees C. As depicted, subsequent to fabrication of the dielectric layer, a layer of TaN is deposited and annealed at 700 degrees C. The interface between the dielectric layer and the substrate appears to be extremely flat with a thin interfacial layer present. Heating this layer to a temperature of 900 degrees C does not cause any re- crystallization.
• FIG. 8 shows a RBS spectra 90 of a LaLu0 3 dielectric layer deposited on silicon showing the presence of La and Lu. An analysis of the spectra revealed that the La to Lu ratio is close to 1:1. The electrical properties of the oxide layer are determined by fabricating capacitors and measuring the capacitance with respect to the applied voltage.
• FIG. 9 shows a capacitance-voltage curve 100 for a capacitor fabricated using the LaLu0 3 dielectric layer on silicon, showing well behaved characteristics.
• the silicon substrate can be covered with a thermally grown silicon dioxide layer (not shown) in structure 10 of FIG. 1.
• the surface of the silicon can be covered with a layer of silicon oxynitride.
• the silicon dioxide can be prepared using chemical means that leaves an oxide no greater than 10 angstrom.
• the silicon substrate can be cleaned in-situ as described above to leave a clean well reconstructed surface.
• This surface is then exposed to a flux of oxygen, in the form of molecular oxygen, activated oxygen as generated in a plasma source or ozone.
• the exposure conditions can be controlled so that a desired thickness in the range of 1 to 15 angstrom, preferably 3-8 angstrom, of the silicon dioxide can be achieved.
• the clean silicon surface can be exposed to a flux of oxygen and nitrogen to form an silicon oxynitride layer.
• the nitrogen can be supplied in a gaseous form including nitrous oxide or activated nitrogen as generated in a plasma source. Following the preparation of the interface layer of silicon dioxide or silicon oxynitride, the deposition of the high-k dielectric layer can be deposited.
• the high K dielectric can be of a form La(Al) x Lu ⁇ -x 0 N y where y > 0. This is accomplished by depositing the high K dielectric layer in the presence of nitrogen as describe above. Nitrogen incorporation into the high K dielectric film can potentially increase the thermal stability and reduce trap densities. While the invention has been described in various embodiments, there may be other embodiments and other materials that may be used in combination that will provide the benefit or some of the benefits that are associated with this invention. Other materials than those mentioned may be used.

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