WO2005036613A2 - Ultra high-speed si/sige modulation-doped field effect transistors on ultra thin soi/sgoi substrate - Google Patents

Ultra high-speed si/sige modulation-doped field effect transistors on ultra thin soi/sgoi substrate Download PDF

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WO2005036613A2
WO2005036613A2 PCT/US2004/028045 US2004028045W WO2005036613A2 WO 2005036613 A2 WO2005036613 A2 WO 2005036613A2 US 2004028045 W US2004028045 W US 2004028045W WO 2005036613 A2 WO2005036613 A2 WO 2005036613A2
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layer
ranging
siι
mobility
electron
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PCT/US2004/028045
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French (fr)
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WO2005036613A3 (en
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Jack O. Chu
Qiqing C. Ouyang
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International Business Machines Corporation
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Priority to EP04809631A priority Critical patent/EP1685590A2/en
Priority to JP2006524911A priority patent/JP5159107B2/en
Publication of WO2005036613A2 publication Critical patent/WO2005036613A2/en
Publication of WO2005036613A3 publication Critical patent/WO2005036613A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure

Definitions

  • the present invention relates generally to silicon and silicon germanium based semiconductor transistor devices, and more specifically, to a device design including a grown epitaxial field effect transistor structure capable of ultra high-speed, low-noise for a variety of communication applications including RF, microwave, sub-millimeter- wave and millimeter- wave.
  • the epitaxial field effect transistor structure includes the critical device scaling and layer structure design for a high mobility strained n-channel transistor incorporating silicon and silicon germanium layers to form the optimum modulation-doped heterostructure on an ultra thin SOI or SGOI substrate in order to achieve f max in excess of 200GHz.
  • SiGe MODFETs when compared to RF bulk Si CMOS device, SiGe MODFETs still have lower noise characteristics, and higher maximum oscillation frequency (f ma ⁇ )- Consequently, Si/SiGe MODFETs are becoming more and more attractive devices for high speed, low noise, and low power communication applications, where low cost and compatibility with CMOS logic technology are required and often essential. Recently, n-channel MODFETs with long channel lengths ranging from 0.2 ⁇ m to 0.5 ⁇ m have demonstrated encouraging device performances.
  • a Si/SiGe MODFET device have an undoped, tensile strained silicon (nFET) or a compressively strained SiGe (pFET) quantum well channels whereby the induced strain is used to increase the carrier mobility in the channel, in addition to providing carrier confinement.
  • the synergistic addition of modulation doping further improves the carrier mobility in the channel by reducing the ionized impurity scattering from the dopants and further reducing the surface roughness scattering in a buried channel.
  • Record high room temperature' mobilities of 2800 cm 2 /Vs have been achieved for electron mobilities in a tensile strained silicon channel grown on a relaxed Sio. 7 Ge 0.3 buffer.
  • FIG. 6 illustrates a graph 200 of the Phosphorus (P) doping profile for a Gl (generation) layer structure and the steady- state P doping 201 problem and transient P doping problems 202 associated with the Phosphorus doping in a CVD growth system.
  • P Phosphorus
  • the invention is directed to a high-electron-mobility n-channel MODFET device that is properly scaled and constructed on a thin SGOI/SOI substrate that exhibits greatly improved RF performance.
  • the present invention is directed to a MODFET device and method of manufacture that addresses the prior art limitations and achieves vertical scaling of the nMODFET layer structure and the source/drain junction and lateral scaling of the device structure to unprecedented degrees, resulting in a device exhibiting ultra-high speed performance (i.e. f ⁇ ⁇ f max > 300GHz) with acceptable voltage gain and good turn-off characteristics.
  • the MODFET device is built on an ultra-thin SiGe-on-insulator (SGOI) substrate, such that the body is fully depleted. Due to the suppressed short channel effects, the output conductance (gd) may be thus be reduced.
  • SGOI ultra-thin SiGe-on-insulator
  • the DC voltage gain (gm/gd), the linearity and f max is significantly improved.
  • the provision of ultra-thin SiGe buffer layers also reduces the self-heating due to the low thermal conductivity of SiGe, which reduces the drive current.
  • a fully-depleted SGOI MODFET exhibits better noise figures and lower soft error rate.
  • the epitaxial field effect transistor structure of the invention includes the critical device scaling and layer structure design for a high mobility strained n-channel transistor incorporating silicon and silicon germanium layers to form the optimum modulation-doped heterostructure on an ultra thin SOI or SGOI substrate in order to achieve f max of > 300GHz.
  • the invention further is directed to a high-hole-mobility p-channel MODFET that is properly scaled and constructed on a thin SGOI/SOI substrate will also have very high RF performance.
  • Figures 1(a)- 1(e) are schematic cross-sectional views showing the inventive Si/SiGe n-type MODFET structure on thin SGOI substrate (G1-G4) properly scaled in accordance with the invention;
  • Figure 1 (f) illustrates a Si/SiGe p-type MODFET structure on thin SGOI substrate; i [0017]
  • Figure 2 illustrates a graph providing simulated I d -V gs curves for the devices in
  • Figure 3 depicts the simulated Id-Vd S curves for a G4 device of Figures 1(a)- 1(f);
  • Figure 4 depicts the simulated gm-V gs curves for a G4 device of Figures 1(a)- 1(f);
  • Figure 5 depicts the simulated r and f max vs. V gs curves for a G4 device of Figures l(a)-l(f);
  • Figure 6 depicts a SIMS profile of the Phosphorus (P) doping profile for a Gl
  • Figure 7 illustrates a graph 160 depicting the steady-state P concentration vs. growth
  • Figure 8 depicts the method for calibrating growth rate reduction 170 for a SiGe (Ge content of 30%) according to the invention
  • Figure 9 illustrates an example plot indicating the steady state P concentration as a function of reduced growth rate
  • Figure 10 is a graph illustrating the profile of transient P incorporation as a function of reduced growth rates
  • Figure 11 depicts a SIMS profile of the Phosphorus P doping and Ge concentration exhibited in a G2 layer structure
  • Figure 12 depicts a SIMS profile of the Phosphorus P doping and Ge concentration exhibited in a G3 layer structure
  • Figure 13 depicts a XTEM for the Gl layer structure on bulk corresponding to the SIMS profiles shown in Figure 6;
  • Figure 14 depicts a XTEM for a G2 layer structure on bulk corresponding to the SIMS profiles shown in Figure 11;
  • Figure 15 depicts a XTEM for a G3 layer structure on a SGOI substrate with thin re- growth
  • Figure 16 depicts a XTEM for a G2 layer structure on a SGOI substrate.
  • Figures l(a)-l(e) are schematic cross-sectional views showing the inventive Si/SiGe n-type MODFET structures on thin SiGe-on-Insulator (SGOI) substrate (generation G1-G4 devices) properly scaled in accordance with the invention.
  • Figure 1(f) illustrates a Si/SiGe p- type MODFET structure on thin SGOI substrate properly scaled in accordance with the invention.
  • Figure 1(a) particularly depicts a MODFET device according to a first embodiment.
  • a top doped nMODFET device 10 comprising a Si substrate layer 5, a buried dielectric layer 8 formed on top of the substrate 5 which may range up to 200 nm in thickness and comprise an oxide, nitride, oxynitride of silicon; and a channel region 25 formed between n+ -type doped source and drain regions 11, 12 respectively, and a gate structure 20 including a gate dielectric layer 22 separating the gate conductor 18 from the channel 25.
  • the gate dielectric layer may comprise an oxide, nitride, oxynitride of silicon, and oxides and silicates of Hf, Al, Zr, La, Y, Ta, singly or in combinations. It is important to realize that according to the invention, the dimensions of the device including drain, source, gate and channel regions have been scaled.
  • the composition of the channel region 25 of device 10 in Figure 1(a) is as follows: A relaxed SiGe layer 30 having a p-type dopant is provided on a buried dielectric layer 8 having Ge content ranging between 30 - 50% and ranging in thickness between 20 nm -30 nm.
  • the p-type doping concentration ranges between lel4 cm “ - 5el7cm " using one of: ion implantation or in- situ doping.
  • the relaxed SiGe layer may be predoped to a concentration level of lei 4 cm "3 - 5el7 cm “3 .
  • the relaxed SiGe layer and other layers comprising the channel 25 is grown according to a UHVCVD technique, however other techniques such as MBE, RTCVD, LPCVD processes may be employed.
  • a five percent (5%) SiGe seed layer 31 (Sio. 95 Geo.o 5 ) is then epitaxially grown on top of the relaxed SiGe layer 30 and an intrinsic Si 1-x Ge x regrown buffer layer 32 is formed on top of the formed SiGe seed layer 31.
  • the thickness of epitaxially grown SiGe seed layer ranges from 0 nm - 5nm and the thickness of the intrinsic SiGe regrown buffer layer 32 ranges between 20nm - 30nm and having Ge content "x" ranging between 10%- 40%.
  • An epitaxial tensile strained Si layer 33 is then grown on top of the SiGe buffer layer 32 and ranges in thickness between 5 nm - 7 nm.
  • An epitaxial Si 1-y Ge y spacer layer 34 is then formed on top of the strained Si layer and ranging in thickness between 3 nm - 5nm and having Ge content "y" ranging between 30 - 40%>.
  • an epitaxial Si ⁇ -z Ge z supply layer 35 is grown on top of the spacer layer ranging in thickness between 2 mn - 8nm and having a n-type doping concentration ranging between 2el 8cm " - 5el9cm " and having Ge content "z” ranging between 35 - 50%.
  • the Si ⁇ -z Ge z supply layer may be grown in a temperature range between 425° C - 550°C and in-situ doped using phosphine gas as a dopant precursor singly or in a mixture including one or more elements including but not limited to: H2, He, Ne, Ar, Kr, Xe, N 2 .
  • the flow rate of the phosphine gas dopant precursor is a linear ramp or a graded profile such that said in-situ doping is performed without disrupting an epitaxial growth process. It is understood that a precursor such as AsH 3 or SbH 3 may be used as well.
  • a small amount of carbon may be incoiporated during the epitaxial growth of the SiGe supply layer 34, e.g., a SiGeC layer, having a C content of about 0.1-2%, preferably about 1 - 1.5%.
  • an epitaxial tensile strained Si cap layer 36 is grown on top of the supply layer 35 ranging in thickness between Onm - 3nm and having a n-type doping concentration ranging between 5el7 cm " - 5el9cm " .
  • the gate dielectric layer 22 is formed on top of the strained Si cap layer and is having an equivalent oxide thickness in a range of 0-1 nm.
  • the gate conductor 18 may have a T-gate geometry, rectangular geometry or a multi-finger geometry formed on top of the gate dielectric layer 22 and may comprise Pt, Ir, W, Pd, Al, Au, Cu, Ti, Co either, singly or in combinations, at lengths ranging between 30nm-100nm.
  • the formed drain region 12 has an n-type doping concentration greater than 5el9cm "3 ; and the formed source region 11 has a n-type doping concentration greater than 5el9cm "3 .
  • the distance between the gate conductor 18 and either drain or source region ranges from about 20nm - lOOnm.
  • the device may further comprise a passivation layer surrounding the gate electrode 20, the passivation layer having a permittivity ranging between 1-4.
  • the depth of the quantum well, d QW of the formed nMODFET includes the spacer layer of intrinsic SiGe 34, the layer of n+ -type doped SiGe 35 and the layer of n+ - type doped Si cap layer 36 totaling approximately 10 nm in depth according to the dimensions depicted in Figure 1(a).
  • Figure 1 (a) depicts a high-electron-mobility device 40 that is identical to the top-doped nMODFET of Figure 1(a), however, does not include the seed layer.
  • Figure 1 (c) illustrates a second embodiment of the invention drawn to a high-electron-mobility nMODFET device 50 that is bottom doped.
  • the device 50 includes a Si substrate layer 5, a buried dielectric layer 8 formed on top of the substrate 5 comprising an oxide, nitride, oxynitride of silicon, for example, and a channel region 55 formed between n+ -type doped source and drain regions 11, 12 respectively, and a gate structure 20.
  • the channel structure 55 includes a relaxed SiGe layer 60 on insulator 8 ranging in thickness between 10 nm and 50nm, an epitaxial Sio .95 Ge 0.
  • o 5 seed layer 61 grown on top of the SiGe layer 60 and ranging in thickness between 0 nm - 5nm; an epitaxial Si ⁇ -z Ge z supply layer 62 grown on top of the seed layer ranging in thickness between 2 nm - 8nm and having a n-type doping concentration ranging between lei 8 cm "3 - 5el9cm "3 ; an epitaxial Si ⁇ -y Ge y spacer layer 63 grown on top of the supply layer and ranging in thickness between 3 nm - 5nm; and, an epitaxial tensile strained Si channel layer 64 grown on top of the spacer layer and ranging in thickness between 3 nm - 10 nm; an epitaxial Si ⁇ _ y Ge y spacer layer 65 grown on top of the strained Si layer and ranging in thickness between 1 nm - 2 nm; and, an epitaxial tensile strained Si cap layer 66 grown on top of the spacer layer ranging in thickness
  • a small amount of carbon may be incorporated during the epitaxial growth of the SiGe supply layer 61, e.g., a SiGeC layer, having a C content of about 0.1-2%, preferably' about 1 - 1.5%.
  • the SiGe supply layer 61 e.g., a SiGeC layer, having a C content of about 0.1-2%, preferably' about 1 - 1.5%.
  • all the gate conductor geometries and distances to respective source/drain regions, the dopant concentrations of the source/drain regions, and the composition of the gate conductor metal and gate dielectric are the same as in the first embodiment ( Figure 1(a)).
  • the depth of the quantum well, d Q of the formed nMODFET includes the layer of n+ -type doped Si cap layer 66 totaling a depth of approximately 2 nm.
  • the seed layer may be omitted.
  • a resulting structure is a high-electron-mobility device that is identical to the bottom-doped nMODFET of Figure 1(c), however, does not include the seed layer.
  • an SGOI substrate comprises: a relaxed SiGe layer on insulator having Ge content ranging between 30 - 40% and ranging in thickness between 20 nm -30 nm; an epitaxial Si ⁇ -z Ge z supply layer grown on top of the relaxed SiGe layer ranging in thickness between 2.5 nm - 8nm and having a n-type doping concentration "z" ranging between 2el8 cm “3 - 2el9cm "3 and having Ge content ranging between 35 - 50%; an epitaxial Si ⁇ -y Ge y spacer layer grown on top of the supply layer and ranging in thickness between 3 nm - 5nm and having Ge content "y" ranging between 30 - 40%; an epitaxial tensile strained Si channel layer grown on top of the spacer layer ranging in thickness between 5 nm - 7 nm and having a doping concentration less than lei 6cm "3 ; an epitaxial Si ⁇ -y Ge y spacer layer grown on
  • Figure 1 (d) illustrates a third embodiment of the invention drawn to a high-electron- mobility nMODFET device 70 that is bottom doped and including a doped transferred layer.
  • the device 70 includes an SGOI substrate comprising a Si ⁇ -z Ge z supply layer 71 ranging in thickness between 2 nm - 8nm and having a n-type doping concentration ranging between lei 8 cm " - 5el9cm " by ion implantation or in-situ doping; an epitaxial Si ⁇ -y Ge y spacer layer 72 grown on top of the supply layer and ranging in thickness between 3 nm - 5nm; an epitaxial tensile strained Si channel layer 73 grown on top of spacer layer 72 and ranging in thickness between 3 nm - 10 nm; an epitaxial Si ⁇ -y Gey spacer layer 74 grown on top of the strained Si layer 73 and ranging in thickness between 1 nm
  • the Si ⁇ -z Ge z supply layer may be predoped to a concentration level of Iel8-5el9 atoms/cm3 before a layer transfer in forming the SGOI substrate.
  • all the gate conductor geometries and distances to respective source/drain regions, the dopant concentrations of the source/drain regions, and the composition and thicknesses of the gate conductor metal and gate dielectric are as depicted in the first embodiment ( Figure 1(a)).
  • the depth of the quantum well, dow of the formed nMODFET includes the layer of n+ -type doped Si cap layer 75 and spacer layer 74 having a depth of less than approximately 4 nm.
  • Figure 1 (e) illustrates a fourth embodiment of the invention drawn to a high-electron- mobility nMODFET device 80 that is both bottom and top doped and including a SiGe regrown buffer layer.
  • the nMODFET device 80 includes an SGOI substrate having: a relaxed SiGe layer 81 on insulator 8 ranging in thickness between 10 nm -50nm, having a n-type doping concentration ranging between lei 7cm " - 5el9cm " and a Ge content ranging between 30-50%; a Si ⁇ -x Ge x regrown buffer layer 82 grown on top of the SiGe layer 81 and ranging in thickness between lOnm - 50nm and serving as a bottom spacer layer and including a Ge content "x" ranging between 10% -35%; an epitaxial tensile strained Si layer 83 grown on top of the regrown buffer layer and ranging in thickness between 3 nm - 10
  • the depth of the quantum well, dow of the formed nMODFET includes the layer of n+ -type doped Si cap layer 86, the epitaxial Si ⁇ -z Ge z supply layer 85, and spacer layer 84 for a depth totaling less than or equal to approximately 16 nm.
  • Figure 1 (f) illustrates a fifth embodiment of the invention drawn to a high-hole- mobility MODFET device 80 that is bottom doped and including a doped transferred layer.
  • the pMODFET device 90 includes an SGOI (SiGe layer 91 on insulator 8) substrate having: a relaxed epitaxial Sii- j G ⁇ j supply layer ranging in thickness between 5 nm -25 nm, and having ion-implanted or in-situ p-type doping of a concentration ranging between lei 8- 5el9cm "3 and serving as a supply layer.
  • SGOI SiGe layer 91 on insulator 8
  • the relaxed Sii- j G ⁇ j layer may be predoped p-type to a concentration level of Iel8-5el9 boron atoms/cm3 before a layer transfer in forming the SGOI substrate; an epitaxial Sii.
  • the Sii. j Ge j supply layer 91 includes a Ge content "j" ranging between 30-70%.
  • the Sii- Ge spacer layer 92 includes a Ge content "k” ranging between 30-70% and, the Si ⁇ -m Ge m channel layer 93 includes a Ge content "m” ranging between 60-100% and the strained Si ⁇ -n Ge n cap layer 94 includes a Ge content n ranging between 0% - 30%.
  • a gate dielectric layer 95 is formed on top of the strained SiGe cap layer 94 and is having an equivalent oxide thickness in a range of 0-1 nm.
  • the gate conductor 18 may have a T-gate geometry, rectangular geometry or a multi-finger geometry formed on top of the gate dielectric layer 95 and may comprise Pt, Ir, W, Pd, Al, Au, Cu, Ti, Co either, singly or in combinations, at lengths ranging between 30nm- lOOnm.
  • a formed drain region 97 has a p-type doping concentration greater than 5el9cm "3 ; and the formed source region 96 has a p-type doping concentration greater than 5el9cm "3 .
  • the distance between the gate conductor 18 and either drain or source region ranges from about 20rrm - lOOnm.
  • the device may further comprise a passivation layer surrounding the gate electrode 20, the passivation layer having a permittivity ranging between 1- 4.
  • the depth of the quantum well, dow of the formed pMODFET 90 includes the SiGe cap layer 94 with a range from approximately between 2nm - 1 Onm.
  • Completed devices comprising embodiments depicted in Figures 1(a)- 1(e) having the different layer structures and design were grown by UHVCVD under growth temperature conditions ranging between 400-600 °C, and preferably in a range of 500-550 °C and in a pressure ranging from 1 mTorr - 20 mTorr.
  • Figure 17 shows the performance (measured fx vs. V gs ) curves 100 with the device scaling (i.e., for Gl and G2 devices).
  • the device has to be further scaled, both in the horizontal and vertical dimensions as in the G2 example shown in Figure 17.
  • Figures 2-5 depict simulated device characteristics for the properly scaled devices of Figures 1(a)- 1(f).
  • Figure 3 depicts the simulated I d -V s curves 110 for the G4 device of Figure 1 and
  • Figure 5 there is depicted the simulated fx and f max vs.
  • FIG. 7 illustrates a graph 160 depicting the steady-state P concentration 161 vs. growth rate in a UHVCVD 162 system.
  • the transient incorporation for P doping depicted by curves 165 is controlled by the Ge content 167 in a SiGe film.
  • the steady state P concentration is controlled by the associated growth rate of the SiGe film.
  • the key process for achieving the abruptness of P profile is to use high Ge content but at a reduced growth rate, which is difficult since it is well known that high Ge is associated with enhanced or high growth rate.
  • the growth rate calibration 170 for a SiGe (Ge content of 30%) is shown in Figure 8, for example, with a Ge concentration profile exhibiting successively smaller peaks 171, 172 as shown in the figure.
  • the enhanced steady- state P concentration 175 is shown in Figure 9 as a function of reduced SiGe growth rate depicted as curve 174.
  • the transient P incorporation rate is also increased as shown by the profile curve 178 in Figure 10.
  • FIG. 15 particularly depicts the XTEM for a G3 layer structure on a SGOI substrate with a transferred SiGe layer of 50nm, where the regrown SiGe on transferred SiGe is thick (e.g., about 134.1nm) in order to minimize the effects of carbon and oxygen at the regrowth interface.
  • the regrown SiGe layer is thick (e.g., about 134.1nm) in order to minimize the effects of carbon and oxygen at the regrowth interface.
  • MODFETs on thin SGOI one task is to make the regrown SiGe layer as thin as possible.
  • a growth process has been developed using a 5% SiGe seed layer as described in the herein incorporated co-pending U.S. Patent Application 10/389,145.
  • Figure 16 depicts a XTEM for a G2 layer structure on a SGOI substrate with a thin regrown SiGe layer (e.g., about 19.7nm) on a SGOI substrate with a 73nm thick transferred SiGe layer. It is advantageous to begin with a thin SGOI substrate which can be formed by a wafer bonding and thinning process as described in co-pending U.S. Patent Application 10/389,145.

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Abstract

A silicon and silicon germanium based semiconductor MODFET device design and method of manufacture. The MODFET design includes a high-mobility layer structure capable of ultra high-speed, low-noise for a variety of communication applications including RF, microwave, sub-millimeter-wave and millimeter-wave. The epitaxial field effect transistor layer structure includes critical (vertical and lateral) device scaling and layer structure design for a high mobility strained n-channel and p-channel transistor incorporating silicon and silicon germanium layers to form the optimum modulation-doped heterostructure on an ultra thin SOI or SGOI substrate capable of achieving greatly improved RF performance.

Description

ULTRA HIGH-SPEED ST/SIGE MODULATION-DOPED FIELD EFFECT TRANSISTORS ON ULTRA THIN SOI/SGOI SUBSTRATE
Background of the Invention Field of the Invention
[0001 ] The present invention relates generally to silicon and silicon germanium based semiconductor transistor devices, and more specifically, to a device design including a grown epitaxial field effect transistor structure capable of ultra high-speed, low-noise for a variety of communication applications including RF, microwave, sub-millimeter- wave and millimeter- wave. Preferably, the epitaxial field effect transistor structure includes the critical device scaling and layer structure design for a high mobility strained n-channel transistor incorporating silicon and silicon germanium layers to form the optimum modulation-doped heterostructure on an ultra thin SOI or SGOI substrate in order to achieve fmax in excess of 200GHz.
Description of the Prior Art
[0002] The attractiveness of substantial electron mobility enhancement (i.e. 3-5 times over bulk silicon) in modulation-doped tensile-strained Si quantum wells has inspired a long history of device development on Si/SiGe n-channel modulation doped filed-ef ect transistors (MODFETs). Subsequently, it has been demonstrated that SiGe MODFETs consume lower power and have lower noise characteristics compared to SiGe Heterojunction Bipolar Transistors (HBTs). Similarly, when compared to RF bulk Si CMOS device, SiGe MODFETs still have lower noise characteristics, and higher maximum oscillation frequency (fmaχ)- Consequently, Si/SiGe MODFETs are becoming more and more attractive devices for high speed, low noise, and low power communication applications, where low cost and compatibility with CMOS logic technology are required and often essential. Recently, n-channel MODFETs with long channel lengths ranging from 0.2μm to 0.5μm have demonstrated encouraging device performances. [0003] Typically, a Si/SiGe MODFET device have an undoped, tensile strained silicon (nFET) or a compressively strained SiGe (pFET) quantum well channels whereby the induced strain is used to increase the carrier mobility in the channel, in addition to providing carrier confinement. The synergistic addition of modulation doping further improves the carrier mobility in the channel by reducing the ionized impurity scattering from the dopants and further reducing the surface roughness scattering in a buried channel. Record high room temperature' mobilities of 2800 cm2/Vs have been achieved for electron mobilities in a tensile strained silicon channel grown on a relaxed Sio.7Ge0.3 buffer. Conversely, very high hole mobility of 1750 cm2/V-s in a pure Ge channel grown on a Sio.35Geo.65 buffer has been achieved [R. Hammond, et al, DRC, 1999]. The highest fτ that has been achieved for a strained silicon nMODFET is 90 GHz [M. Zeuner, 2002], and the highest fmax is 190 GHz [Koester, et al to be published]. So far, neither fτ nor fmax has reached 200 GHz with Si/SiGe MODFETs.
[0004] As described in a simulation study conducted by the inventors, in order to achieve higher speed, the MODFET has to be scaled properly, both in the vertical dimensions and the horizontal (or lateral) dimensions. However, it turns out that the scaling of MODFETs is even more challenging than for CMOS scaling due to the following: 1) the horizontal scaling brings the source and drain closer, and, like the case in the CMOS, short-channel effects and bulk punchthrough become the major hurdles preventing the lateral scaling; and, 2) the vertical scaling of the layer structure turns out to be crucial. The lateral scaling alone cannot keep the scaling of the performance. However, the vertical scaling of the MODFET structures to reduce the depth of the quantum well (dς>w) is quite challenging, particularly due to the scaling and abruptness of the n+ supply layer, which is typically doped with Phosphorus as explained in the Annual Review of Materials Science, vol. 30, 2000, pp. 348-355. Figure 6 illustrates a graph 200 of the Phosphorus (P) doping profile for a Gl (generation) layer structure and the steady- state P doping 201 problem and transient P doping problems 202 associated with the Phosphorus doping in a CVD growth system. [0005] It would be highly desirable to provide a scaling technique for MODFET device structures that overcomes the lateral and vertical scaling challenges in the manufacture of MODFET device structures. t
[0006] It has been further been demonstrated in commonly-owned, co-pending United States Patent Application patent application 10/389,145 entitled "Dual Strain State SiGe Layers for Microelectronics" by J. Chu, et al, filed March 15, 2003, the contents and disclosure of which is incorporated by reference as if fully set forth herein, that MODFETs on a thick Silicon- Germanium-on- Insulator (SGOI) substrate will behave like MODFET on a bulk substrate. Co- pending U.S. Patent Application 10/389,145 particularly describes a generic MODFET layer structure on a SGOI substrate without specifying the critical layer structure for high performance.
[0007] It would be further highly desirable to provide a scaled MODFET device structure that is built on an ultra-thin SiGe-on-insulator (SGOI) substrate, wherein the MODFET device structure exhibits ultra-high speed device performance (e.g., fχ5 fmax > 300GHz) with better noise figures, acceptable voltage gain and good turn-off characteristics.
Summary of the Invention
[0008] The invention is directed to a high-electron-mobility n-channel MODFET device that is properly scaled and constructed on a thin SGOI/SOI substrate that exhibits greatly improved RF performance.
[0009] The present invention is directed to a MODFET device and method of manufacture that addresses the prior art limitations and achieves vertical scaling of the nMODFET layer structure and the source/drain junction and lateral scaling of the device structure to unprecedented degrees, resulting in a device exhibiting ultra-high speed performance (i.e. fχ} fmax > 300GHz) with acceptable voltage gain and good turn-off characteristics. [0010] In the method of manufacturing the MODFET device of the invention, the MODFET device is built on an ultra-thin SiGe-on-insulator (SGOI) substrate, such that the body is fully depleted. Due to the suppressed short channel effects, the output conductance (gd) may be thus be reduced. Therefore, the DC voltage gain (gm/gd), the linearity and fmax is significantly improved. In addition, the provision of ultra-thin SiGe buffer layers also reduces the self-heating due to the low thermal conductivity of SiGe, which reduces the drive current. Compared to a bulk MODFET, a fully-depleted SGOI MODFET exhibits better noise figures and lower soft error rate. Preferably, the epitaxial field effect transistor structure of the invention includes the critical device scaling and layer structure design for a high mobility strained n-channel transistor incorporating silicon and silicon germanium layers to form the optimum modulation-doped heterostructure on an ultra thin SOI or SGOI substrate in order to achieve fmax of > 300GHz.
[0011] As studies have shown that the Phosphorus incorporation rate can be controlled by the growth rate (See aforementioned Annual Review of Materials Science, vol. 30, 2000, pp. 348-355), it is thus a further object of the present invention to provide a novel MODFET device structure method of achieving thin SiGe epitaxial layer with an abrupt P doping. In this objective, a novel low temperature growth technique is implemented for achieving abrupt phosphorous doping profiles in order to accommodate and to match the proper vertical scaling or design of the MODFET layer structure required for ultra-high speed performances.
[0012] In order to prevent the Phosphorus diffusion during the fabrication process, a small amount of carbon maybe incorporated during the epitaxial growth of the SiGe supply layer in the manner as described in commonly-owned, co-pending United States Patent Application patent application 09/838,892 (Docket YOR920010308US1) entitled "Epitaxial and Polycrystalline Growth of Siι-x-yGexCy and Siι-yCy Alloy Layers on Si by UHV-CVD", the contents and disclosure of which is incorporated by reference as if fully set forth herein.
[0013] The invention further is directed to a high-hole-mobility p-channel MODFET that is properly scaled and constructed on a thin SGOI/SOI substrate will also have very high RF performance. Brief Description of the Drawings
[0014] Further features, aspects and advantages of the apparatus and methods of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where:
[0015] Figures 1(a)- 1(e) are schematic cross-sectional views showing the inventive Si/SiGe n-type MODFET structure on thin SGOI substrate (G1-G4) properly scaled in accordance with the invention;
[0016] Figure 1 (f) illustrates a Si/SiGe p-type MODFET structure on thin SGOI substrate; i [0017] Figure 2 illustrates a graph providing simulated Id-Vgs curves for the devices in
Figures l(a)-l(f) (Lgs=Lg=Lgd=50nm);
[0018] Figure 3 depicts the simulated Id-VdS curves for a G4 device of Figures 1(a)- 1(f);
[0019] Figure 4 depicts the simulated gm-Vgs curves for a G4 device of Figures 1(a)- 1(f);
[0020] Figure 5 depicts the simulated r and fmax vs. Vgs curves for a G4 device of Figures l(a)-l(f);
[0021] Figure 6 depicts a SIMS profile of the Phosphorus (P) doping profile for a Gl
(generation) layer structure and the steady-state and transient P doping exhibited in a Gl layer structure;
[0022] Figure 7 illustrates a graph 160 depicting the steady-state P concentration vs. growth
UHV CVD system according to the invention;Figure 8 depicts the method for calibrating growth rate reduction 170 for a SiGe (Ge content of 30%) according to the invention;Figure 9 illustrates an example plot indicating the steady state P concentration as a function of reduced growth rate;Figure 10 is a graph illustrating the profile of transient P incorporation as a function of reduced growth rates;
[0026] Figure 11 depicts a SIMS profile of the Phosphorus P doping and Ge concentration exhibited in a G2 layer structure;
[0027] Figure 12 depicts a SIMS profile of the Phosphorus P doping and Ge concentration exhibited in a G3 layer structure;
[0028] Figure 13 depicts a XTEM for the Gl layer structure on bulk corresponding to the SIMS profiles shown in Figure 6;
[0029] Figure 14 depicts a XTEM for a G2 layer structure on bulk corresponding to the SIMS profiles shown in Figure 11;
[0030] Figure 15 depicts a XTEM for a G3 layer structure on a SGOI substrate with thin re- growth;
[0031] Figure 16 depicts a XTEM for a G2 layer structure on a SGOI substrate; and,
[0032] Figure 17 illustrates a measured f"χ vs. Vgs for a Gl device with dQ = 25 nm, Lg=250nm and a G2 device with dQ = 15nm, Lg=70nm.
Detailed Description of the Preferred Embodiment
[0033] Figures l(a)-l(e) are schematic cross-sectional views showing the inventive Si/SiGe n-type MODFET structures on thin SiGe-on-Insulator (SGOI) substrate (generation G1-G4 devices) properly scaled in accordance with the invention. Figure 1(f) illustrates a Si/SiGe p- type MODFET structure on thin SGOI substrate properly scaled in accordance with the invention.
[0034] Figure 1(a) particularly depicts a MODFET device according to a first embodiment. As shown in Figure 1(a), there is depicted a top doped nMODFET device 10 comprising a Si substrate layer 5, a buried dielectric layer 8 formed on top of the substrate 5 which may range up to 200 nm in thickness and comprise an oxide, nitride, oxynitride of silicon; and a channel region 25 formed between n+ -type doped source and drain regions 11, 12 respectively, and a gate structure 20 including a gate dielectric layer 22 separating the gate conductor 18 from the channel 25. As shown in the figure, the gate dielectric layer may comprise an oxide, nitride, oxynitride of silicon, and oxides and silicates of Hf, Al, Zr, La, Y, Ta, singly or in combinations. It is important to realize that according to the invention, the dimensions of the device including drain, source, gate and channel regions have been scaled.
[0035] The composition of the channel region 25 of device 10 in Figure 1(a) is as follows: A relaxed SiGe layer 30 having a p-type dopant is provided on a buried dielectric layer 8 having Ge content ranging between 30 - 50% and ranging in thickness between 20 nm -30 nm. The p-type doping concentration ranges between lel4 cm" - 5el7cm" using one of: ion implantation or in- situ doping. The relaxed SiGe layer may be predoped to a concentration level of lei 4 cm"3 - 5el7 cm"3. Preferably, the relaxed SiGe layer and other layers comprising the channel 25 is grown according to a UHVCVD technique, however other techniques such as MBE, RTCVD, LPCVD processes may be employed. A five percent (5%) SiGe seed layer 31 (Sio.95Geo.o5) is then epitaxially grown on top of the relaxed SiGe layer 30 and an intrinsic Si1-xGex regrown buffer layer 32 is formed on top of the formed SiGe seed layer 31. The thickness of epitaxially grown SiGe seed layer ranges from 0 nm - 5nm and the thickness of the intrinsic SiGe regrown buffer layer 32 ranges between 20nm - 30nm and having Ge content "x" ranging between 10%- 40%. An epitaxial tensile strained Si layer 33 is then grown on top of the SiGe buffer layer 32 and ranges in thickness between 5 nm - 7 nm. An epitaxial Si1-yGey spacer layer 34 is then formed on top of the strained Si layer and ranging in thickness between 3 nm - 5nm and having Ge content "y" ranging between 30 - 40%>. Then, an epitaxial Siι-zGez supply layer 35 is grown on top of the spacer layer ranging in thickness between 2 mn - 8nm and having a n-type doping concentration ranging between 2el 8cm" - 5el9cm" and having Ge content "z" ranging between 35 - 50%. The Siι-zGez supply layer may be grown in a temperature range between 425° C - 550°C and in-situ doped using phosphine gas as a dopant precursor singly or in a mixture including one or more elements including but not limited to: H2, He, Ne, Ar, Kr, Xe, N2. Preferably, the flow rate of the phosphine gas dopant precursor is a linear ramp or a graded profile such that said in-situ doping is performed without disrupting an epitaxial growth process. It is understood that a precursor such as AsH3 or SbH3 may be used as well. As mentioned herein, in order to prevent the P diffusion during the fabrication process, a small amount of carbon may be incoiporated during the epitaxial growth of the SiGe supply layer 34, e.g., a SiGeC layer, having a C content of about 0.1-2%, preferably about 1 - 1.5%. Finally, an epitaxial tensile strained Si cap layer 36 is grown on top of the supply layer 35 ranging in thickness between Onm - 3nm and having a n-type doping concentration ranging between 5el7 cm" - 5el9cm" .
[0036] To form the transistor device of Figure 1(a), the gate dielectric layer 22 is formed on top of the strained Si cap layer and is having an equivalent oxide thickness in a range of 0-1 nm. The gate conductor 18 may have a T-gate geometry, rectangular geometry or a multi-finger geometry formed on top of the gate dielectric layer 22 and may comprise Pt, Ir, W, Pd, Al, Au, Cu, Ti, Co either, singly or in combinations, at lengths ranging between 30nm-100nm. The formed drain region 12 has an n-type doping concentration greater than 5el9cm"3; and the formed source region 11 has a n-type doping concentration greater than 5el9cm"3. The distance between the gate conductor 18 and either drain or source region ranges from about 20nm - lOOnm. Although not shown, the device may further comprise a passivation layer surrounding the gate electrode 20, the passivation layer having a permittivity ranging between 1-4. As indicated in Figure 1(a), the depth of the quantum well, dQW of the formed nMODFET includes the spacer layer of intrinsic SiGe 34, the layer of n+ -type doped SiGe 35 and the layer of n+ - type doped Si cap layer 36 totaling approximately 10 nm in depth according to the dimensions depicted in Figure 1(a).
[0037] In an alternate embodiment the seed layer 31 of Figure 1 (a) may be omitted. Figure 1(b) depicts a high-electron-mobility device 40 that is identical to the top-doped nMODFET of Figure 1(a), however, does not include the seed layer.Figure 1 (c) illustrates a second embodiment of the invention drawn to a high-electron-mobility nMODFET device 50 that is bottom doped. As shown in Figure lc), the device 50 includes a Si substrate layer 5, a buried dielectric layer 8 formed on top of the substrate 5 comprising an oxide, nitride, oxynitride of silicon, for example, and a channel region 55 formed between n+ -type doped source and drain regions 11, 12 respectively, and a gate structure 20. The channel structure 55 includes a relaxed SiGe layer 60 on insulator 8 ranging in thickness between 10 nm and 50nm, an epitaxial Sio.95Ge0.o5 seed layer 61 grown on top of the SiGe layer 60 and ranging in thickness between 0 nm - 5nm; an epitaxial Siι-zGez supply layer 62 grown on top of the seed layer ranging in thickness between 2 nm - 8nm and having a n-type doping concentration ranging between lei 8 cm"3 - 5el9cm"3; an epitaxial Siι-yGey spacer layer 63 grown on top of the supply layer and ranging in thickness between 3 nm - 5nm; and, an epitaxial tensile strained Si channel layer 64 grown on top of the spacer layer and ranging in thickness between 3 nm - 10 nm; an epitaxial Siι_ yGey spacer layer 65 grown on top of the strained Si layer and ranging in thickness between 1 nm - 2 nm; and, an epitaxial tensile strained Si cap layer 66 grown on top of the spacer layer ranging in thickness between On - 2nm. As in the first embodiment, a small amount of carbon may be incorporated during the epitaxial growth of the SiGe supply layer 61, e.g., a SiGeC layer, having a C content of about 0.1-2%, preferably' about 1 - 1.5%. Further, with respect to the second embodiment of Figure lc) all the gate conductor geometries and distances to respective source/drain regions, the dopant concentrations of the source/drain regions, and the composition of the gate conductor metal and gate dielectric are the same as in the first embodiment (Figure 1(a)). As indicated in Figure 1(c), the depth of the quantum well, dQ of the formed nMODFET includes the layer of n+ -type doped Si cap layer 66 totaling a depth of approximately 2 nm. [0039] In an alternate embodiment of the structure 50 of Figure 1 (c), the seed layer may be omitted. Thus a resulting structure is a high-electron-mobility device that is identical to the bottom-doped nMODFET of Figure 1(c), however, does not include the seed layer. In this alternate embodiment, an SGOI substrate comprises: a relaxed SiGe layer on insulator having Ge content ranging between 30 - 40% and ranging in thickness between 20 nm -30 nm; an epitaxial Siι-zGez supply layer grown on top of the relaxed SiGe layer ranging in thickness between 2.5 nm - 8nm and having a n-type doping concentration "z" ranging between 2el8 cm"3 - 2el9cm"3 and having Ge content ranging between 35 - 50%; an epitaxial Siι-yGey spacer layer grown on top of the supply layer and ranging in thickness between 3 nm - 5nm and having Ge content "y" ranging between 30 - 40%; an epitaxial tensile strained Si channel layer grown on top of the spacer layer ranging in thickness between 5 nm - 7 nm and having a doping concentration less than lei 6cm"3; an epitaxial Siι-yGey spacer layer grown on top of the Si channel layer and ranging in thickness between 1 nm - 2nm and having Ge content ranging between 30 - 40%; and, an epitaxial tensile strained Si cap layer grown on top of the spacer layer ranging in thickness between Onm - 2nm. A transistor device is completed with the drain source and gate conductor regions as shown and explained with respect to Figure 1(c).
[0040] Figure 1 (d) illustrates a third embodiment of the invention drawn to a high-electron- mobility nMODFET device 70 that is bottom doped and including a doped transferred layer. As shown in Figure 1(d), the device 70 includes an SGOI substrate comprising a Siι-zGez supply layer 71 ranging in thickness between 2 nm - 8nm and having a n-type doping concentration ranging between lei 8 cm" - 5el9cm" by ion implantation or in-situ doping; an epitaxial Siι-yGey spacer layer 72 grown on top of the supply layer and ranging in thickness between 3 nm - 5nm; an epitaxial tensile strained Si channel layer 73 grown on top of spacer layer 72 and ranging in thickness between 3 nm - 10 nm; an epitaxial Siι-yGey spacer layer 74 grown on top of the strained Si layer 73 and ranging in thickness between 1 nm - 2 nm; and, an epitaxial tensile strained Si cap layer 75 grown on top of the spacer layer ranging in thickness between Onm - 2nm. Preferably, the doped transferred Si1-zGez supply layer 71 has a Ge content z = x+a, where "a" ranges between about 0-30%, "x" ranges between 30-50%, and may be formed by a wafer bonding and smart-cut process. Alternatively, the Siι-zGez supply layer may be predoped to a concentration level of Iel8-5el9 atoms/cm3 before a layer transfer in forming the SGOI substrate. The doped transferred Siι-zGez supply layer may further comprise a Siι-m-nGemCn layer, where m=x+b, and "b" ranges between 0-30%, and "n" ranges between 0.1-2%. The Siι_ yGey spacer layers 72, 74 includes a Ge content y = x+c, where "c" ranges between 0 - 20%. Further, with respect to the third embodiment of Figure 1(d), all the gate conductor geometries and distances to respective source/drain regions, the dopant concentrations of the source/drain regions, and the composition and thicknesses of the gate conductor metal and gate dielectric are as depicted in the first embodiment (Figure 1(a)). As indicated in Figure 1(d), the depth of the quantum well, dow of the formed nMODFET includes the layer of n+ -type doped Si cap layer 75 and spacer layer 74 having a depth of less than approximately 4 nm.
[0041] Figure 1 (e) illustrates a fourth embodiment of the invention drawn to a high-electron- mobility nMODFET device 80 that is both bottom and top doped and including a SiGe regrown buffer layer. As shown in Figure 1(e), the nMODFET device 80 includes an SGOI substrate having: a relaxed SiGe layer 81 on insulator 8 ranging in thickness between 10 nm -50nm, having a n-type doping concentration ranging between lei 7cm" - 5el9cm" and a Ge content ranging between 30-50%; a Siι-xGex regrown buffer layer 82 grown on top of the SiGe layer 81 and ranging in thickness between lOnm - 50nm and serving as a bottom spacer layer and including a Ge content "x" ranging between 10% -35%; an epitaxial tensile strained Si layer 83 grown on top of the regrown buffer layer and ranging in thickness between 3 nm - 10 nm; an epitaxial Siι-yGey spacer layer 84 grown on top of the strained Si layer 83 and ranging in thickness between 3 nm - 5nm; an epitaxial Siι-zGez supply layer 85 grown on top of the spacer layer 84 ranging in thickness between 2 nm - 8nm and having a n-type doping concentration ranging between lei 8 cm" - 5el9cm" ; and, an epitaxial tensile strained Si cap layer 86 grown on top of the supply layer 85 ranging in thickness between Onm - 3nm and having a n-type doping concentration ranging between 5el7 cm" - 5el9cm" . The Siι-yGey spacer layer 84 includes a Ge content y = x+a, where "a" ranges between 0 - 20% and the Si1-2Gez supply layer includes a Ge content z = x+b, where "b" ranges between 0-30%. As in the other embodiments, the Siι-zGez supply layer comprises a Si1-m-nGemCn layer, where m=x+c, and "c" ranges between 0-20%, and "n" ranges between 0.1-2%. Further, with respect to the fourth embodiment of Figure 1(e), all the gate conductor geometries and distances to respective source/drain regions, the dopant concentrations of the source/drain regions, and the composition and thicknesses of the gate conductor metal and gate dielectric are as depicted in the first embodiment (Figure 1(a)). As indicated in Figure 1(e), the depth of the quantum well, dow of the formed nMODFET includes the layer of n+ -type doped Si cap layer 86, the epitaxial Siι-zGez supply layer 85, and spacer layer 84 for a depth totaling less than or equal to approximately 16 nm.
[0042] Figure 1 (f) illustrates a fifth embodiment of the invention drawn to a high-hole- mobility MODFET device 80 that is bottom doped and including a doped transferred layer. As shown in Figure 1(f), the pMODFET device 90 includes an SGOI (SiGe layer 91 on insulator 8) substrate having: a relaxed epitaxial Sii-jGβj supply layer ranging in thickness between 5 nm -25 nm, and having ion-implanted or in-situ p-type doping of a concentration ranging between lei 8- 5el9cm"3 and serving as a supply layer. Alternately, the relaxed Sii-jGβj layer may be predoped p-type to a concentration level of Iel8-5el9 boron atoms/cm3 before a layer transfer in forming the SGOI substrate; an epitaxial Sii. Get spacer layer 92 grown on top of the supply layer 91 and ranging in thickness between 3nm - 7nm; an epitaxial compressively strained Siι_mGem channel layer 93 grown on top of the spacer layer and ranging in thickness between 5 nm - 20 mn; and, an epitaxial strained Si1-nGen cap layer 94 grown on top of the strained Siι-mGem channel layer and ranging in thickness between 2nm - lOnm. In the high-hole-mobility layer semiconductor structure 90 the Sii.jGej supply layer 91 includes a Ge content "j" ranging between 30-70%. The Sii- Ge spacer layer 92 includes a Ge content "k" ranging between 30-70% and, the Siι-mGem channel layer 93 includes a Ge content "m" ranging between 60-100% and the strained Siι-nGen cap layer 94 includes a Ge content n ranging between 0% - 30%.
[0043] To form the pMODFET transistor device of Figure 1(f), a gate dielectric layer 95 is formed on top of the strained SiGe cap layer 94 and is having an equivalent oxide thickness in a range of 0-1 nm. The gate conductor 18 may have a T-gate geometry, rectangular geometry or a multi-finger geometry formed on top of the gate dielectric layer 95 and may comprise Pt, Ir, W, Pd, Al, Au, Cu, Ti, Co either, singly or in combinations, at lengths ranging between 30nm- lOOnm. A formed drain region 97 has a p-type doping concentration greater than 5el9cm"3; and the formed source region 96 has a p-type doping concentration greater than 5el9cm"3. The distance between the gate conductor 18 and either drain or source region ranges from about 20rrm - lOOnm. Although not shown, the device may further comprise a passivation layer surrounding the gate electrode 20, the passivation layer having a permittivity ranging between 1- 4. As indicated in Figure 1(f), the depth of the quantum well, dow of the formed pMODFET 90 includes the SiGe cap layer 94 with a range from approximately between 2nm - 1 Onm.
[0044] Completed devices comprising embodiments depicted in Figures 1(a)- 1(e) having the different layer structures and design were grown by UHVCVD under growth temperature conditions ranging between 400-600 °C, and preferably in a range of 500-550 °C and in a pressure ranging from 1 mTorr - 20 mTorr.
[0045] Figure 17 shows the performance (measured fx vs. Vgs) curves 100 with the device scaling (i.e., for Gl and G2 devices). For example, Figure 17 shows the fx curve for a Gl device with dow= 25 nm, Lg=250nm as compared to a G2 device with dQ = 15nm, Lg=70nm. As shown, in order to further improve the performance, the device has to be further scaled, both in the horizontal and vertical dimensions as in the G2 example shown in Figure 17.
[0046] Figures 2-5 depict simulated device characteristics for the properly scaled devices of Figures 1(a)- 1(f). Figure 2 depicts the simulated Id-Vgs curves 105 for the G4 device of Figure 1 where Lgs=Lg=Lgd =50nm. Figure 3 depicts the simulated Id-V s curves 110 for the G4 device of Figure 1 and Figure 4 depicts the simulated gm-Vgs curves 120 for the G4 device in Figure 1 (Lgs=Lg=Lgd =50nm). As shown in Figure 5, there is depicted the simulated fx and fmax vs. Vgs curves 130 for the device in Figure 1 where fχ=230 GHz and
Figure imgf000015_0001
GHz can be achieved according to device simulations.
[0047] As mentioned hereinabove, experimentally it has been found that Phosphorus (P) doping can be controlled by the Ge content and its associated growth rate in a UHV CVD system. Figure 7 illustrates a graph 160 depicting the steady-state P concentration 161 vs. growth rate in a UHVCVD 162 system.
[0048] As shown in the steady-state P concentration vs. growth rate graph of Figure 7, in particular, the transient incorporation for P doping depicted by curves 165 is controlled by the Ge content 167 in a SiGe film. Likewise, the steady state P concentration is controlled by the associated growth rate of the SiGe film. The key process for achieving the abruptness of P profile is to use high Ge content but at a reduced growth rate, which is difficult since it is well known that high Ge is associated with enhanced or high growth rate.
[0049] The growth rate calibration 170 for a SiGe (Ge content of 30%) is shown in Figure 8, for example, with a Ge concentration profile exhibiting successively smaller peaks 171, 172 as shown in the figure. Using the same calibration with the addition of PH3, the enhanced steady- state P concentration 175 is shown in Figure 9 as a function of reduced SiGe growth rate depicted as curve 174. Similarly, as shown in the graph depicting transient P incorporation vs. reduced growth rates in Figure 10, for the higher Ge content 177, the transient P incorporation rate is also increased as shown by the profile curve 178 in Figure 10.
[0050] Using a reduced flow combination of SiH4 to GeH4 of (15sccm/17sccm), a Gl doping profile has been obtained just like secondary ion mass spectroscopy (SIMS) profiles 201, 202 as shown in Figure 6. The corresponding cross-sectional transmission electron micrograph (XTEM) is shown in Figure 13.
[0051] Using a lower flow combination SiH4 to GeH4 of (10/17), a G2 doping profile has been achieved as shown in the SIMS profiles P doping and Ge concentration profiles shown in Figure 11. The corresponding XTEM is shown in Figure 14.
[0052] Using an even lower flow combination SiH4 to GeH4 of (8/10), a G3 doping profile has been achieved as shown in the SIMS profiles P doping and Ge concentration profiles shown in Figure 12. The corresponding XTEM is shown in Figure 15. Figure 15 particularly depicts the XTEM for a G3 layer structure on a SGOI substrate with a transferred SiGe layer of 50nm, where the regrown SiGe on transferred SiGe is thick (e.g., about 134.1nm) in order to minimize the effects of carbon and oxygen at the regrowth interface. However, in order to make MODFETs on thin SGOI, one task is to make the regrown SiGe layer as thin as possible. A growth process has been developed using a 5% SiGe seed layer as described in the herein incorporated co-pending U.S. Patent Application 10/389,145.
[0053] Figure 16 depicts a XTEM for a G2 layer structure on a SGOI substrate with a thin regrown SiGe layer (e.g., about 19.7nm) on a SGOI substrate with a 73nm thick transferred SiGe layer. It is advantageous to begin with a thin SGOI substrate which can be formed by a wafer bonding and thinning process as described in co-pending U.S. Patent Application 10/389,145.
[0054] While the invention has been particularly shown and described with respect to illustrative and preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention that should be limited only by the scope of the appended claims.

Claims

CLAIMS:Having thus described our invention, what we claim as new, and desire to secure by Letters Patent is:
1. A high-electron-mobility layer semiconductor structure comprising:
an SGOI substrate comprising a SiGe layer on insulator having Ge content ranging between 30 - 40%) and ranging in thickness between 20 nm -30 nm, and having a p-type doping concentration ranging between lel4 cm" - 5el7cm" ;
an epitaxial Sio.95Geo.05 seed layer grown on top of said SiGe layer and ranging in thickness between 0 nm - 5nm;
a regrown Si1-xGex buffer layer grown on top of said seed layer and ranging in thickness between 20nm - 30nm and having Ge content x ranging between 10%-40%;
an epitaxial tensile strained Si layer grown on top of said buffer layer and ranging in thickness between 5 nm - 7 nm;
an epitaxial Siι-yGey spacer layer grown on top of said strained Si layer and ranging in thickness between 3 nm - 5nm and having Ge content y ranging between 30 - 40%;
an epitaxial Siι-2Gez supply layer grown on top of said spacer layer ranging in thickness between 2 nm - 8mn and having a n-type doping concentration ranging between 2el 8 cm"3 - 2el 9cm"3 and having Ge content ranging between 35 - 50%; and,
an epitaxial tensile strained Si cap layer grown on top of said supply layer ranging in thickness between Onm - 3nm and having a n-type doping concentration ranging between 5el7 cm"3 - 5el9cm"3.
2. The high-electron-mobility layer semiconductor structure as claimed in claim 1 , wherein said Siι-yGey spacer layer includes a Ge content y = x+a, where "a" ranges between 0 - 20%.
3. The high-electron-mobility layer semiconductor structure as claimed in claim 1, wherein said Siι-zGez supply layer includes a Ge content z = x+b, where "b" ranges between 0-30%).
4. The high-electron-mobility layer semiconductor structure as claimed in claim 1, wherein said Siι-zGez supply layer comprises a Siι-ιn-nGemCn layer, where m=x+c, and "c" ranges between 0- 20%, and "n" ranges between 0.1-2%.
5. The high-electron-mobility layer semiconductor structure as claimed in claim 1, further comprising:
a gate dielectric layer formed on top of said strained Si cap layer and having an equivalent oxide thickness in a range of 0-1 nm;
a gate conductor formed on top of said gate dielectric layer;
a drain region having a n-type doping concentration greater than 5el9cm" ; and,
a source region having a n-type doping concentration greater than 5el9cm"3, wherein said structure forms a high-electron-mobility field effect transistor.
6. The high-electron-mobility field effect transistor as claimed in claim 5, wherein said Siι-zGez supply layer ranges from about 5 nm - 8 nm in thickness and has a sheet doping density of about 3el2cm"2.
7. The high-electron-mobility field effect transistor as claimed in claim 5, wherein said Si1-zGez supply layer is about 4 nm in thickness and has a sheet doping density of about 2.4el2cm"2.
8. The high-electron-mobility field effect transistor as claimed in claim 6, wherein said Siι-zGez supply layer comprises a SiGeC layer having a C content of about 1 - 1.5%.
9. The high-electron-mobility field effect transistor as claimed in claim 5, wherein said gate dielectric layer is selected from a group comprising: an oxide, nitride, oxynitride of silicon, and oxides and silicates of Hf, Al, Zr, La, Y, Ta, singly or in combinations thereof.
10. The high-electron-mobility field effect transistor as claimed in claim 5, wherein said gate conductor is selected from a group comprising: Pt, Ir, W, Pd, Al, Au, Cu, Ti, Co, singly or in combinations thereof.
11. The high-electron-mobility field effect transistor as claimed in claim 5, wherein said gate conductor is one of: a T-gate geometry, rectangular geometry or a multi-finger geometry.
12. The high-electron-mobility field effect transistor as claimed in claim 5, wherein a gate length ranges between 30nm-100nm.
13. The high-electron-mobility field effect transistor as claimed in claim 5, wherein a distance between said gate conductor and either said drain or source region ranges from about 20nm - lOOnm.
14. The high-electron-mobility field effect transistor as claimed in claim 5, further comprising a passivation layer surrounding the gate electrode, said passivation layer having a permittivity ranging between 1-4.
15. A high-electron-mobility field effect transistor comprising: an SGOI substrate comprising a SiGe layer on insulator having Ge content ranging between 30 - 40%) and ranging in thickness between 20 mn -30 nm, and having a p-type doping concentration ranging between lel4 cm"3 - 5el7cm"3;
a regrown Siι-xGex buffer layer grown on top of said SiGe layer and ranging in thickness between 20nm - 3 Onm, and having a Ge content x of 30-40%;
an epitaxial tensile strained Si layer grown on top of said buffer layer and ranging in thickness between 5 nm - 7 nm;
an epitaxial Siι_yGey spacer layer grown on top of said strained Si layer and ranging in thickness between 3 nm - 5nm and having Ge content ranging between 30 - 40%;
an epitaxial Siι-zGez supply layer grown on top of said spacer layer ranging in thickness between 2 nm - 8nm and having a n-type doping concentration ranging between 2el8 cm"3 - 2el9cm"3 and having Ge content ranging between 35 - 50%;
an epitaxial tensile strained Si cap layer grown on top of said supply layer ranging in thickness between Onm - 3nm and having a n-type doping concentration ranging between 5el7 cm"3 - 5el9cm"3;
a gate dielectric layer formed on top of said strained Si cap layer and having an equivalent oxide thickness in a range of 0- lnm;
a gate conductor formed on top of said gate dielectric layer;
a drain region having a n-type doping concentration greater than 5el9cm"3; and,
a source region having a n-type doping concentration greater than 5el9cm"3.
16. A high-electron-mobility layer semiconductor structure comprising:
an SGOI substrate comprising a Siι-xGex layer on insulator ranging in thickness between 10 nm - 5 Onm,
an epitaxial Sio.95Geo.05 seed layer grown on top of said SiGe layer and ranging in thickness between 0 nm - 5nm;
an epitaxial Siι_zGez supply layer grown on top of said seed layer ranging in thickness between 2 mn - 8nm and having a n-type doping concentration ranging between lei 8 cm"3 - 5el9cm"3; and,
an epitaxial Siι-yGey spacer layer grown on top of said supply layer and ranging in thickness between 3 nm - 5nm;
an epitaxial tensile strained Si layer grown on top of said spacer layer and ranging in thickness between 3 nm - 10 nm; , ,
an epitaxial Si1-yGey spacer layer grown on top of said strained Si layer and ranging in thickness between 1 nm - 2 nm; and,
an epitaxial tensile strained Si cap layer grown on top of said spacer layer ranging in thickness between Onm - 2nm.
17. The high-electron-mobility layer semiconductor structure as claimed in claim 16, wherein said SGOI substrate includes a Siι-xGex layer with a Ge content x ranging between 30-50%.
18. The high-electron-mobility layer structure as claimed in claim 16, wherein said Siι_zGez supply layer has a Ge content z = x+a, where "a" ranges between about 0-30% and x ranges between 30-50%.
19. The high-electron-mobility layer semiconductor structure as claimed in claim 16, wherein said Siι-zGez supply layer comprises a Siι-m-nGemCn layer, where m=x+b, and "b" ranges between 0-30%, and "n" ranges between 0.1-2%.
20. The high-electron-mobility layer semiconductor structure as claimed in claim 16, wherein said Siι-yGey spacer layer includes a Ge content y = x+c, where "c" ranges between 0 - 20%>.
21. The high-electron-mobility layer semiconductor structure as claimed in claim 16, further comprising:
a gate dielectric layer formed on top of said strained Si cap layer and having an equivalent oxide thickness in a range of 0-1 nm;
a gate conductor formed on top of said gate dielectric layer;
a drain region having a n-type doping concentration greater than 5el9cm"3; and,
a source region having a n-type doping concentration greater than 5el9cm"3, wherein said structure forms a high-electron-mobility field effect transistor.
22. The high-electron-mobility layer semiconductor structure as claimed in claim 21, wherein said Siι-zGez supply layer is about 5nm - 8 nm in thickness and has a sheet doping density of about 3el2cm"2.
23. The high-electron-mobility layer semiconductor structure as claimed in claim 21, wherein said Si1-zGez supply layer is about 4 nm in thickness and has a sheet doping density of about 2.4el2cm"2.
24. The high-electron-mobility layer semiconductor structure as claimed in claim 21, wherein said Sii-zGez supply layer comprises a SiGeC layer having a C content of about 1 - 1.5%.
25. The high-electron-mobility layer semiconductor structure as claimed in claim 21, wherein said gate dielectric layer is selected from a group comprising: an oxide, nitride, oxynitride of silicon, and oxides and silicates of Hf, Al, Zr, La, Y, Ta, singly or in combinations thereof.
26. The high-electron-mobility layer semiconductor structure as claimed in claim 21, wherein said gate conductor is selected from a group comprising: Pt, Ir, W, Pd, Al, Au, Cu, Ti, Co, singly or in combinations thereof.
27. The high-electron-mobility layer semiconductor structure as claimed in claim 21, wherein said gate conductor is one of: a T-gate geometry, rectangular geometry or a multi-finger geometry.
28. The high-electron-mobility layer semiconductor structure as claimed in claim 21, wherein a gate length ranges between 30nm-100nm.
29. The high-electron-mobility layer semiconductor structure as claimed in claim 21, wherein a distance between said gate conductor and either said drain or source region ranges from about 20nm - 100nm.
30. The high-electron-mobility layer semiconductor structure as claimed in claim 21, further comprising a passivation layer surrounding the gate electrode, said passivation layer having a permittivity ranging between 1-4.
31. A high-electron-mobility field effect transistor comprising:
an SGOI substrate comprising a SiGe layer on insulator having Ge content ranging between 30 - 40% and ranging in thickness between 20 nm -30 nm; an epitaxial Siι-zGez supply layer grown on top of said SiGe layer ranging in thickness between 2.5 nm - 8nm and having a n-type doping concentration ranging between 2el8 cm"3 - 2el9cm"3 and having Ge content ranging between 35 - 50%;
an epitaxial Siι-yGey spacer layer grown on top of said supply layer and ranging in thickness between 3 nm - 5nm and having Ge content ranging between 30 - 40%;
an epitaxial tensile strained Si channel layer grown on top of said spacer layer ranging in thickness between 5 nm - 7 mn and having a doping concentration less than lei 6cm"3;
an epitaxial Siι-yGey spacer layer grown on top of said Si channel layer and ranging in thickness between 1 nm - 2nm and having Ge content ranging between 30 - 40%;
an epitaxial tensile strained Si cap layer grown on top of said spacer layer ranging in thickness between Onm - 2nm;
a gate dielectric layer formed on top of said strained Si cap layer and having an equivalent oxide thickness in a range of 0-1 nm;
a gate conductor formed on top of said gate dielectric layer;
a drain region having a n-type doping concentration greater than 5el9cm"3; and,
a source region having a n-type doping concentration greater than 5el9cm"3.
32. A high- electron-mobility layer semiconductor structure comprising:
an SGOI substrate comprising a Siι-zGez supply layer ranging in thickness between 2 nm - 8nm and having a n-type doping concentration ranging between lei 8 cm"3 - 5el9cm"3; and, an epitaxial Siι-yGey spacer layer grown on top of said supply layer and ranging in thickness between 3 nm - 5nm;
an epitaxial tensile strained Si layer grown on top of said spacer layer and ranging in thickness between 3 nm - 10 nm;
an epitaxial Si1-yGey spacer layer grown on top of said strained Si layer and ranging in thickness between 1 mn - 2 nm; and,
an epitaxial tensile strained Si cap layer grown on top of said spacer layer ranging in thickness between Onm - 2nm.
33. The high-electron-mobility layer semiconductor structure as claimed in claim 32, wherein said SGOI substrate includes a Ge content "x" ranging between 30-50%.
34. The high-electron-mobility layer semiconductor structure as claimed in claim 32, wherein said doped transferred Siι-zGez supply layer has a Ge content z = x+a, where "a" ranges between about 0-30% and may be formed by a wafer bonding and smart-cut process.
35. The high-electron-mobility layer semiconductor structure as claimed in claim 32, wherein said doped transferred Siι-zGez supply layer comprises a Siι-m-nGemCn layer, where m=x+b, and "b" ranges between 0-30%, and "n" ranges between 0.1-2%).
36. The high-electron-mobility layer semiconductor structure as claimed in claim 32, wherein said Siι-yGey spacer layer includes a Ge content y = x+c, where "c" ranges between 0 - 20%.
37. The high-electron-mobility layer semiconductor structure as claimed in claim 32, further comprising: a gate dielectric layer formed on top of said strained Si cap layer and less than lnm in thickness;
a gate conductor formed on top of said gate dielectric layer;
a drain region having a n-type doping concentration greater than 5el9cm"3; and,
a source region having a n-type doping concentration greater than 5el9cm"3.
38. The high-electron-mobility layer semiconductor structure as claimed in claim 37, wherein said doped transferred Siι-zGez supply layer is about 5 nm - 8 nm in thickness and has a sheet doping density of about 3el2cm-2.
39. The high-electron-mobility layer semiconductor structure as claimed in claim 37, wherein said doped transferred Siι-zGez supply layer is about 4 nm in thickness and has a sheet doping density of about 2.4el2cm-2.
40. The high-electron-mobility layer semiconductor structure as claimed in claim 32, wherein said doped transferred Siι-zGez supply layer comprises a SiGeC layer having a C content of about 1 - 1.5%.
41. The high-electron-mobility layer semiconductor structure as claimed in claim 37, wherein said gate dielectric layer is selected from a group comprising: an oxide, nitride, oxynitride of silicon, and oxides and silicates of Hf, Al, Zr, La, Y, Ta, singly or in combinations thereof.
42. The high-electron-mobility layer semiconductor structure as claimed in claim 37, wherein said gate conductor is selected from a group comprising: Pt, Ir, W, Pd, Al, Au, Cu, Ti, Co, singly or in combinations thereof.
43. The high-electron-mobility layer semiconductor structure as claimed in claim 37, wherein said gate conductor is one of: a T-gate geometry, rectangular geometry, or a multi-finger geometry.
44. The high-electron-mobility layer semiconductor structure as claimed in claim 37, wherein a gate length ranges between 30nm-100mn.
45. The high-electron-mobility layer semiconductor structure as claimed in claim 37, wherein a distance between said gate conductor and either said drain or source region ranges from about 20mn - lOOmn.
46. The high-electron-mobility layer semiconductor structure as claimed in claim 37, further comprising a passivation layer surrounding the gate electrode, said passivation layer having a permittivity ranging between 1-4.
47. A high-electron-mobility layer semiconductor structure comprising:
an SGOI substrate comprising a SiGe layer on insulator ranging in thickness between 10 nm - 50nm, and having a n-type doping concentration ranging between lel7cm"3 - 5el9cm"3;
a Siι-xGex regrown buffer layer grown on top of said SiGe layer and ranging in thickness between lOnm - 50nm and serving as a bottom spacer layer;
an epitaxial tensile strained Si layer grown on top of said regrown buffer layer and ranging in thickness between 3 nm - 10 nm;
an epitaxial Siι-yGey spacer layer grown on top of said strained Si layer and ranging in thickness between 3 nm - 5nm; an epitaxial Siι-zGez supply layer grown on top of said spacer layer ranging in thickness between 2 nm - 8nm and having a n-type doping concentration ranging between lei 8 cm"3 - 5el9cm"3; and,
an epitaxial tensile strained Si cap layer grown on top of said supply layer ranging in thickness between Onm - 3nm and having a n-type doping concentration ranging between 5el7 cm"3 - 5el9cm"3.
48. The high-electron-mobility layer semiconductor structure as claimed in claim 47, wherein said SGOI substrate includes a Ge content ranging between 30-50%.
49. The high-electron-mobility layer semiconductor structure as claimed in claim 47, wherein said Siι-xGex regrown buffer layer includes a Ge content x ranging between 10-35%.
50. The high-electron-mobility layer semiconductor structure as claimed in claim 47, wherein said Siι-yGey spacer layer includes a Ge content y = x+a, where "a" ranges between 0 - 20%.
51. The high-electron-mobility layer semiconductor structure as claimed in claim 47, wherein said Siι_zGez supply layer includes a Ge content z = x+b, where "b" ranges between 0-30%o.
52. The high-electron-mobility layer semiconductor structure as claimed in claim 47, wherein said Siι-zGez supply layer comprises a Siι_m-nGemCn layer, where m=x+c, and "c" ranges between 0-20%, and "n" ranges between 0.1-2%.
53. The high-electron-mobility layer semiconductor structure as claimed in Claim 47, further comprising:
a gate dielectric layer formed on top of said strained Si cap layer and having an equivalent oxide thickness in a range of 0-1 nm; a gate conductor formed on top of said gate dielectric layer;
a drain region having a n-type doping concentration greater than 5el9cm -"3 ;. and,
a source region having a n-type doping concentration greater than 5el9cm" .
54. The high-electron-mobility layer semiconductor structure as claimed in claim 53, wherein said Siι-zGez supply layer is about 5nm - 8 nm in thickness and has a sheet doping density of about 3el2cm-2.
55. The high-electron-mobility layer semiconductor structure as claimed in claim 53, wherein said Siι-zGez supply layer is about 4 mn in thickness and has a sheet doping density of about 2.4el2cm-2.
56. The high-electron-mobility layer semiconductor structure as claimed in claim 54, wherein said Siι-zGez supply layer comprises a SiGeC layer having a C content of about 1 - 1.5%.
57. The high-electron-mobility layer semiconductor structure as claimed in claim 53, wherein said gate dielectric layer is selected from a group comprising: an oxide, nitride, oxynitride of silicon, and oxides and silicates of Hf, Al, Zr, La, Y, Ta, singly or in combinations thereof.
58. The high-electron-mobility layer semiconductor structure as claimed in claim 53, wherein said gate conductor is selected from a group comprising: Pt, Ir, W, Pd, Al, Au, Cu, Ti, Co, singly or in combinations thereof.
59. The high-electron-mobility layer semiconductor structure as claimed in claim 53, wherein said gate conductor is one of: a T-gate, rectangular, or multi-finger geometry.
60. The high-electron-mobility layer semiconductor structure as claimed in claim 53, wherein a gate length ranges between 30nm-100nm.
61. The high-electron-mobility layer semiconductor structure as claimed in claim 53, wherein a distance between said gate conductor and either said source or drain region ranges from about 20nm - lOOnm.
62. The high-electron-mobility layer semiconductor structure as claimed in claim 53, further comprising a passivation layer surrounding the gate electrode, said passivation layer having a permittivity ranging between 1 -4.
63. A high-hole-mobility layer semiconductor structure comprising:
an SGOI substrate comprising an epitaxial Sii.jGej supply layer ranging in thickness between 5 nm -25nm, and having a p-type doping concentration ranging between 1 el 8-5el9cm"3;
an epitaxial Sii- Gβk spacer layer grown on top of said supply layer and ranging in thickness between 3nm - 7nm;
an epitaxial compressively strained Siι-mGem channel layer grown on top of said spacer layer and ranging in thickness between 5 nm - 20 nm; and,
an epitaxial strained Siι-nGen cap layer grown on top of said strained Siι-mGem channel layer and ranging in thickness between 2nm - 1 Onm.
64. The high-hole-mobility layer semiconductor structure as claimed in claim 63, wherein said Sii.jGej supply layer includes a Ge content j ranging between 30-70%.
65. The high-hole-mobility layer semiconductor structure as claimed in claim 63, wherein said Sii-kGe spacer layer includes a Ge content k ranging between 30-70%.
66. The high-hole-mobility layer semiconductor structure as claimed in claim 63, wherein said Siι-mGem channel layer includes a Ge content m ranging between 60-100%.
67. The high-hole-mobility layer semiconductor structure as claimed in claim 63, wherein said strained Siι-nGen cap layer includes a Ge content n ranging between 0% - 30%.
68. The high-hole-mobility layer semiconductor structure as claimed in claim 63, further comprising:
a gate conductor formed on top of said gate dielectric layer;
a drain region having a p-type doping concentration greater than 5el9cm"3; and,
a source region having a p-type doping concentration greater than 5el9cm"3.
69. The high-hole-mobility layer semiconductor structure as claimed in claim 68, wherein said gate dielectric layer is selected from a group comprising: an oxide, nitride, oxynitride of silicon, and oxides and silicates of Hf, Al, Zr, La, Y, Ta, singly or in combinations thereof.
70. The high-hole-mobility layer semiconductor structure as claimed in claim 68, wherein said gate conductor is selected from a group comprising: Pt, Ir, W, Pd, Al, Au, Cu, Ti, Co, singly or in combinations thereof.
71. The high-hole-mobility layer semiconductor structure as claimed in claim 68, wherein said gate conductor is one of: a T-gate, rectangular, or multi-finger geometry.
72. The high-hole-mobility layer semiconductor structure as claimed in claim 68, wherein a gate length ranges between 30nm-100nm.
73. The high-hole-mobility layer semiconductor structure as claimed in claim 68, wherein a distance between said gate conductor and either said drain or source region ranges from about 20nm - lOOnm.
74. The high-hole-mobility layer semiconductor structure as claimed in claim 68, further comprising a passivation layer surrounding the gate electrode, said passivation layer having a permittivity ranging between 1-4.
75. A method of preparing a high-electron-mobility layer structure comprising the steps of:
a) providing a SGOI substrate having a relaxed Siι-xGex layer on insulator;
b) forming a Si0.95Ge0.05 seed layer on top of said Siι-xGex layer;
c) forming a regrown Siι-xGex buffer layer on top of said Si0.95Ge0.05 seed layer;
d) forming a strained silicon channel layer on top of said regrown Siι-xGex layer,
e) forming a Siι-yGey spacer layer on top of said strained silicon layer; f) forming a Siι-zGez supply layer on top of said Siι-yGey spacer layer, doping said Siι-zGez supply layer n-type to a concentration level in a range of Iel8-5el9 atoms/cm3; and,
g) forming a silicon cap layer on top of said Siι-zGez supply layer.
76. The method according to claim 75, wherein said forming steps b) - g) comprise implementing a UHVCVD process.
77. The method according to claim 75, wherein said forming steps b) - g) comprise implementing one of MBE, RTCVD, LPCVD processes.
78. The method according to claim 75, wherein said layer forming steps b) - g) comprise growing the layers in a temperature range between 450° C - 600°C.
79. The method according to claim 75, wherein said layer forming steps b) - g) comprise growing the layers in a pressure range from 1 mTorr - 20 mTorr.
80. The method according to claim 75, wherein said step a) of providing a SGOI substrate having a relaxed Siι-xGex layer on insulator further includes the step of: doping the relaxed Siι-xGex layer on insulator p-type to a concentration level of lei 4 cm"3 - 5el7cm"3 using one of: ion implantation or in-situ doping.
81. The method according to claim 75, wherein said step a) of providing a SGOI substrate having a relaxed Siι-xGex layer on insulator further includes the step of: predoping the relaxed Siι-xGex layer to a concentration level of lel4 cm"3 - 5el7 cm"3 prior to transferring said layer in forming the SGOI substrate.
82. The method according to claim 75, wherein said step f) of forming a Siι-zGez supply layer further includes the step of: in-situ doping said Siι-zGez supply layer using phosphine gas as a dopant precursor singly or in a mixture thereof including one or more elements selected from the group comprising: H2, He, Ne, Ar, Kr, Xe, N2.
83. The method according to claim 75, including growing said Siι-zGe2 supply layer at a reduced growth rate for a higher P steady state concentration and transient incorporation by reducing the SiH4 and GeH4 gas flow rate by a factor of greater than 3 while keeping the SiH :GeH4 gas flow ratio constant.
84. The method according to claim 82, wherein a flow rate for said phosphine gas dopant precursor is a linear ramp or a graded profile such that said in-situ doping is performed without disrupting the epitaxial growth process.
85. The method according to claim 82, wherein the phosphine doped Siι-zGez layer is grown in a temperature range between 425° C - 550°C.
86. The method according to claim 82, further including doping the Siι-zGez supply layer with carbon at 1-2% level in a temperature range of 425° C - 550°C.
87. The method according to claim 75, wherein said step f) of forming a n-type Si ι-zGez supply layer further includes the step of using a precursor of one of: AsH or SbH3.
88. A method of preparing a high-electron-mobility layer structure comprising the steps of:
a) providing a SGOI substrate having a relaxed Siι-xGex layer on insulator;
b) forming a regrown Siι-xGex buffer layer on top of said relaxed Siι_xGex layer;
c) forming a strained silicon channel layer on top of said regrown Siι-xGeχ layer,
d) forming a Siι-yGey spacer layer on top of said strained silicon layer;
e) forming a Siι-zGez supply layer on top of said Siι-yGey spacer layer, doping said Siι-zGez supply layer n-type to a concentration level in a range of Iel8-5el9 atoms/cm3; and,
f) forming a silicon cap layer on top of said Siι-zGez supply layer.
89. A method of preparing a high-electron-mobility layer structure comprising the steps of:
a) providing a SGOI substrate having a relaxed Siι-xGex layer on insulator;
b) forming an epitaxial Sio.c15Geo.05 seed layer on top of said SiGe layer; c) forming an epitaxial Siι-zGez supply layer on top of said spacer layer and doping said supply layer with n-type dopant concentration ranging between lei 8 cm" - 5el9cm" ;
d) forming an epitaxial Siι-yGey spacer layer on top of said supply layer and ranging in thickness between 3 nm - 5nm;
e) forming an epitaxial tensile strained Si layer on top of said spacer layer;
f) forming an epitaxial Siι-yGey spacer layer on top of said strained Si layer and ranging in thickness between 1 nm - 2 nm; and,
g) forming an epitaxial tensile strained Si cap layer grown on top of said supply layer ranging in thickness between Onm - 2nm.
90. A method of preparing a high-electron-mobility layer structure comprising steps of:
a) providing a SGOI substrate having a Siι-xGex supply layer on insulator, and doping the Siι_ xGex supply layer n-type to a concentration level ranging between 1 el 8-5el9 atoms/cm3;
b) forming an epitaxial Siι-yGey spacer layer over above doped Siι-xGex layer,
c) forming an epitaxial tensile strained Si channel layer on top of said spacer layer;
d) forming an epitaxial Siι-yGey spacer layer on top of said strained Si channel layer; and,
e) forming an epitaxial strained Si cap layer on top of said spacer layer.
91. The method as claimed in claim 90, further including the step of doping the Siι-xGex layer on insulator n-type to a concentration level of Iel8-5el9 atoms/cm using ion implantation or in-situ doping.
92. The method as claimed in claim 90, further including the step of predoping the Siι-xGex layer to a concentration level of lei 8-5el9 atoms/cm3 before a layer transfer in forming the SGOI substrate.
93. A method of preparing a higli-electron-mobility layer structure comprising the steps of:
a) providing a SGOI substrate comprising a relaxed SiGe layer on insulator ranging in thickness between 10 nm -50nm, and doping said relaxed SiGe layer with n-type doping concentration ranging between lel4cm" - 5el7cm" ;
b) forming a Siι-xGex regrown buffer layer grown on top of said SiGe layer and ranging in thickness between lOnm - 50nm;
c) forming an epitaxial tensile strained Si layer on top of said regrown buffer layer and ranging in thickness between 3 nm - 10 nm;
d) forming an epitaxial Siι-yGey spacer layer on top of said strained Si layer and ranging in thickness between 3 nm - 5nm;
e) forming an epitaxial Si1-zGez supply layer on top of said spacer layer ranging in thickness between 2 nm - 8nm and having a n-type doping concentration ranging between lei 8 cm"3 - 5el9cm"3; and,
f) forming an epitaxial tensile strained Si cap layer grown on top of said supply layer ranging in thickness between Onm - 3nm and having a n-type doping concentration ranging between 5el7 cm"3 - 5el9cm"3.
94. A method of preparing a high-hole-mobility layer structure comprising steps of: a) providing a SGOI substrate having a relaxed Siι_jGej layer on insulator;
b) forming a Sii-kGβk spacer layer on top of said doped Sii.jGβj layer;
c) forming a compressively strained Siι-mGem channel layer on top of said Si1-kGek spacer layer; and,
d) forming a Siι-nGen spacer layer on top of said compressively strained Si1-mGem channel layer.
95. The method as claimed in claim 94, further including the step of doping the Siι_jGej layer p- type to a concentration level ranging between lei 8-5el9 atoms/cm using ion implantation or in- situ doping.
96. The method as claimed in claim 94, whereby the relaxed Sii-jGβj layer may be predoped p- type to a concentration level of Iel8-5el9 boron atoms/cm3 before a layer transfer in forming the SGOI substrate.
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Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7166528B2 (en) * 2003-10-10 2007-01-23 Applied Materials, Inc. Methods of selective deposition of heavily doped epitaxial SiGe
US7132338B2 (en) * 2003-10-10 2006-11-07 Applied Materials, Inc. Methods to fabricate MOSFET devices using selective deposition process
US7224007B1 (en) * 2004-01-12 2007-05-29 Advanced Micro Devices, Inc. Multi-channel transistor with tunable hot carrier effect
US20060151787A1 (en) * 2005-01-12 2006-07-13 International Business Machines Corporation LOW CONCENTRATION SiGe BUFFER DURING STRAINED Si GROWTH OF SSGOI MATERIAL FOR DOPANT DIFFUSION CONTROL AND DEFECT REDUCTION
US7465972B2 (en) 2005-01-21 2008-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. High performance CMOS device design
US7470972B2 (en) * 2005-03-11 2008-12-30 Intel Corporation Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress
US20080050883A1 (en) * 2006-08-25 2008-02-28 Atmel Corporation Hetrojunction bipolar transistor (hbt) with periodic multilayer base
US20060292809A1 (en) * 2005-06-23 2006-12-28 Enicks Darwin G Method for growth and optimization of heterojunction bipolar transistor film stacks by remote injection
US20070054460A1 (en) * 2005-06-23 2007-03-08 Atmel Corporation System and method for providing a nanoscale, highly selective, and thermally resilient silicon, germanium, or silicon-germanium etch-stop
US8039880B2 (en) * 2005-09-13 2011-10-18 Raytheon Company High performance microwave switching devices and circuits
US7176504B1 (en) * 2005-09-28 2007-02-13 United Microelectronics Corp. SiGe MOSFET with an erosion preventing Six1Gey1 layer
US8530934B2 (en) 2005-11-07 2013-09-10 Atmel Corporation Integrated circuit structures containing a strain-compensated compound semiconductor layer and methods and systems related thereto
US20070102834A1 (en) * 2005-11-07 2007-05-10 Enicks Darwin G Strain-compensated metastable compound base heterojunction bipolar transistor
US20070148890A1 (en) * 2005-12-27 2007-06-28 Enicks Darwin G Oxygen enhanced metastable silicon germanium film layer
US7323392B2 (en) * 2006-03-28 2008-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. High performance transistor with a highly stressed channel
US20070262295A1 (en) * 2006-05-11 2007-11-15 Atmel Corporation A method for manipulation of oxygen within semiconductor materials
US7772060B2 (en) * 2006-06-21 2010-08-10 Texas Instruments Deutschland Gmbh Integrated SiGe NMOS and PMOS transistors
US7569913B2 (en) * 2006-10-26 2009-08-04 Atmel Corporation Boron etch-stop layer and methods related thereto
US7495250B2 (en) * 2006-10-26 2009-02-24 Atmel Corporation Integrated circuit structures having a boron- and carbon-doped etch-stop and methods, devices and systems related thereto
US7550758B2 (en) 2006-10-31 2009-06-23 Atmel Corporation Method for providing a nanoscale, high electron mobility transistor (HEMT) on insulator
US7893475B2 (en) * 2007-01-24 2011-02-22 Macronix International Co., Ltd. Dynamic random access memory cell and manufacturing method thereof
US7791063B2 (en) * 2007-08-30 2010-09-07 Intel Corporation High hole mobility p-channel Ge transistor structure on Si substrate
CN100570823C (en) * 2007-11-06 2009-12-16 清华大学 A kind of method of using the necking down extension to obtain the low-dislocation-density epitaxial film
US8293608B2 (en) * 2008-02-08 2012-10-23 Freescale Semiconductor, Inc. Intermediate product for a multichannel FET and process for obtaining an intermediate product
US8222657B2 (en) * 2009-02-23 2012-07-17 The Penn State Research Foundation Light emitting apparatus
KR101087939B1 (en) 2009-06-17 2011-11-28 주식회사 하이닉스반도체 Semiconductor Device and Method for Manufacturing the same
CN102623487B (en) * 2011-01-26 2015-04-08 中国科学院微电子研究所 Semiconductor device and method for manufacturing the same
US10490697B2 (en) 2011-12-03 2019-11-26 Sensor Electronic Technology, Inc. Epitaxy technique for growing semiconductor compounds
US10158044B2 (en) 2011-12-03 2018-12-18 Sensor Electronic Technology, Inc. Epitaxy technique for growing semiconductor compounds
WO2013082592A1 (en) * 2011-12-03 2013-06-06 Sensor Electronic Technology, Inc. Epitaxy technique for growing semiconductor compounds
CN104160479B (en) 2012-02-01 2019-04-30 传感器电子技术股份有限公司 For reducing the epitaxy technology of the threading dislocation in stressed semiconductor compound
US8648388B2 (en) 2012-02-15 2014-02-11 International Business Machines Corporation High performance multi-finger strained silicon germanium channel PFET and method of fabrication
US8891573B2 (en) 2012-05-14 2014-11-18 Arizona Board Of Regents 6.1 angstrom III-V and II-VI semiconductor platform
US9525053B2 (en) 2013-11-01 2016-12-20 Samsung Electronics Co., Ltd. Integrated circuit devices including strained channel regions and methods of forming the same
US9419082B2 (en) * 2014-04-23 2016-08-16 Globalfoundries Inc. Source/drain profile engineering for enhanced p-MOSFET
KR102155327B1 (en) 2014-07-07 2020-09-11 삼성전자주식회사 Field effect transistor and methods for manufacturing the same
US9570590B1 (en) 2015-12-10 2017-02-14 International Business Machines Corporation Selective oxidation of buried silicon-germanium to form tensile strained silicon FinFETs
US9917154B2 (en) 2016-06-29 2018-03-13 International Business Machines Corporation Strained and unstrained semiconductor device features formed on the same substrate
TWI732925B (en) * 2016-08-23 2021-07-11 美商克若密斯股份有限公司 Electronic power devices integrated with an engineered substrate
CN106549039A (en) * 2016-11-03 2017-03-29 浙江大学 A kind of Low Power High Performance germanium raceway groove quantum well field effect transistor
CN107221583B (en) * 2017-05-17 2019-01-29 福建海佳彩亮光电科技有限公司 A kind of vertical structure LED and its preparation process
CN111863955A (en) * 2019-04-25 2020-10-30 世界先进积体电路股份有限公司 Semiconductor structure

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000031491A (en) * 1998-07-14 2000-01-28 Hitachi Ltd Semiconductor device, its manufacture, semiconductor substrate and its manufacture
US6350993B1 (en) * 1999-03-12 2002-02-26 International Business Machines Corporation High speed composite p-channel Si/SiGe heterostructure for field effect devices
KR100441469B1 (en) * 1999-03-12 2004-07-23 인터내셔널 비지네스 머신즈 코포레이션 High speed ge channel heterostructures for field effect devices
US6573126B2 (en) * 2000-08-16 2003-06-03 Massachusetts Institute Of Technology Process for producing semiconductor article using graded epitaxial growth
US6890835B1 (en) * 2000-10-19 2005-05-10 International Business Machines Corporation Layer transfer of low defect SiGe using an etch-back process
WO2002047168A2 (en) * 2000-12-04 2002-06-13 Amberwave Systems Corporation Cmos inverter circuits utilizing strained silicon surface channel mosfets
US6593625B2 (en) 2001-06-12 2003-07-15 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
US6515335B1 (en) * 2002-01-04 2003-02-04 International Business Machines Corporation Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same
US6953736B2 (en) * 2002-07-09 2005-10-11 S.O.I.Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ANNUAL REVIEW OF MATERIALS SCIENCE, vol. 30, 2000, pages 348 - 355

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