WO2005036244A1 - Module for reflection liquid crystal display and its manufacturing method, and reflection liquid crystal display - Google Patents

Module for reflection liquid crystal display and its manufacturing method, and reflection liquid crystal display Download PDF

Info

Publication number
WO2005036244A1
WO2005036244A1 PCT/JP2003/012943 JP0312943W WO2005036244A1 WO 2005036244 A1 WO2005036244 A1 WO 2005036244A1 JP 0312943 W JP0312943 W JP 0312943W WO 2005036244 A1 WO2005036244 A1 WO 2005036244A1
Authority
WO
WIPO (PCT)
Prior art keywords
liquid crystal
crystal display
film
insulating film
gas
Prior art date
Application number
PCT/JP2003/012943
Other languages
French (fr)
Japanese (ja)
Inventor
Toyoaki Sakai
Naoya Nakamura
Atsushi Kuwashima
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2003/012943 priority Critical patent/WO2005036244A1/en
Publication of WO2005036244A1 publication Critical patent/WO2005036244A1/en

Links

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1335Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133553Reflecting elements
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1343Electrodes
    • G02F1/13439Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136277Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon

Definitions

  • Reflective liquid crystal display module Description Reflective liquid crystal display module, method of manufacturing the same, and reflective liquid crystal display
  • the present invention relates to a reflection type liquid crystal display device module, a method for manufacturing the same, and a reflection type liquid crystal display device. More specifically, the present invention relates to a reflective liquid crystal display module having good display quality, a method for manufacturing the same, and a reflective liquid crystal display device.
  • a reflection type liquid crystal display device called a silicon chip-based liquid crystal has been attracting attention as a head mounted display or a projection type display.
  • a method for manufacturing the reflection type liquid crystal display device according to the conventional example will be described.
  • an interlayer insulating film 101 is formed above a silicon wafer (not shown) on which MOS transistors are formed on the surface, and then the first interlayer insulating film 101 is formed on the interlayer insulating film 101 by a photolithography method and an etching step.
  • the second holes 101a and 101b are formed.
  • the first and second conductive plugs 102 a and 102 b connected to the source / drain regions of the MOS transistor are connected to the first and second holes 101 a and 100 lb.
  • the metal film is patterned to form each conductive plug.
  • the first reflective electrode 103a and the second reflective electrode 103b are left on 102a and 102b.
  • an insulating film is formed on the entire surface, and the insulating film is polished by CMP method or etched back. , Gear between each reflective electrode 103a, 103b The insulating film remaining in the gap is a buried insulating film 104.
  • the LCOS (Liquid Crystal on Silicon) substrate 105 is completed.
  • a liquid crystal panel 106 formed in another step is bonded onto the LCOS substrate 105 by a sealing material (not shown).
  • a liquid crystal layer 108 is sealed between the lower liquid crystal alignment layer 107 and the upper liquid crystal alignment layer 109, and a transparent liquid crystal is formed on the upper liquid crystal alignment layer 109.
  • the common electrode 110 is formed, and the surface glass 111 for protecting the surface of the liquid crystal panel 106 from external impact is provided on the common electrode 110.
  • the basic structure of the reflective liquid crystal display device 115 according to the conventional example is completed.
  • pixels are defined by the first and second reflective electrodes 103a and 103b, and the voltage value of each reflective electrode 103a and 103b is not changed.
  • the potential difference between the common electrode 110 and each of the reflective electrodes 103 a and 103 b is controlled by individually changing the MOS transistors shown in the figure, and the liquid crystal layer 106 is controlled according to the potential difference. Is controlled for each pixel.
  • the buried insulating film 104 is left in the gap between the reflective electrodes 103a and 103b by the CMP method or the etch-back method.
  • the buried insulating film 104 is excessively polished, and the upper surface of the buried insulating film 104 0 3 a, 1 0 3 It becomes easier to sink than the upper surface of b, and the flatness of the upper surface of the LCOS substrate 105 becomes worse.
  • An object of the present invention is to provide a reflection type liquid crystal display module capable of preventing a decrease in contrast and poor color tone, a method for manufacturing the same, and a reflection type liquid crystal display device.
  • a semiconductor substrate comprising: Is done.
  • a step of forming a first insulating film above a semiconductor substrate a step of forming a second insulating film on the first insulating film; Forming an insulating spacer having an opening for each pixel by patterning the film; and forming the insulating spacer on the insulating spacer and in the opening in the opening.
  • a method for manufacturing a module for a reflection type liquid crystal display device comprising:
  • the conductive film is polished to such an extent that the insulating spacer is exposed, and the conductive film remaining in the opening of the insulating spacer is used as the reflective electrode, so that the upper surface of the reflective electrode is flat. And the upper surface is at the same height as the upper surface of the insulating spacer. Therefore, even if the liquid crystal panel is pasted on the reflective electrode, Since a gap is not formed between the insulating spacer and the insulating spacer as in the related art, scattering of incident light due to the gap is prevented. As a result, a combination of the liquid crystal panel and the liquid crystal panel realizes a reflection type liquid crystal display module in which the color tone is improved and the contrast is enhanced.
  • the interval between adjacent reflective electrodes becomes extremely short due to the narrow upper surface of the insulating spacer.
  • the reflection electrodes are arranged at a very high density, so that the incident light scattered by the insulating spacer is reduced, and most of the incident light is reflected by the reflection electrode. The reflectance of the entire display module is improved.
  • a resist pattern is formed on the second insulating film, and the etching gas and the flow rate are higher than the etching gas.
  • the second insulating film may be etched using the resist pattern as a mask.
  • a resist pattern is formed on the second insulating film, and the resist pattern is heated and melted to break the cross-sectional shape of the resist pattern, and the resist pattern and the second insulating film Also, by etching simultaneously, an insulating spacer having a tapered cross section can be formed.
  • the aluminum film is formed as a conductive film serving as a reflective electrode
  • the aluminum film is formed by a sputtering method in which the substrate temperature is kept at a low temperature of room temperature (20 ° C.) to 350 ° C.
  • the substrate temperature is kept at a low temperature of room temperature (20 ° C.) to 350 ° C.
  • the grains of the aluminum film do not grow large, the irregularities on the surface of the aluminum film are reduced, and a reflective electrode having a high reflectance can be obtained.
  • FIGS. 1 (a) and 1 (b) are cross-sectional views for explaining a method of manufacturing a reflection type liquid crystal display device according to a conventional example
  • Figure 2 shows a reflective liquid crystal display using silicon chip-based liquid crystal. It is a principle diagram schematically showing
  • FIGS. 3 (a) and 3 (b) are cross-sectional views (part 1) showing a method of manufacturing a reflective liquid crystal display module according to the first embodiment of the present invention in the order of steps;
  • FIG. 5 (a) and 5 (b) are cross-sectional views (part 2) showing a method of manufacturing the reflective liquid crystal display device module according to the first embodiment of the present invention in the order of steps;
  • FIGS. FIGS. 6A and 6B are cross-sectional views showing a method of manufacturing a module for a reflection type liquid crystal display device according to the first embodiment of the present invention in the order of steps;
  • FIGS. FIG. 7 is a cross-sectional view (part 4) showing a method for manufacturing a module for a reflective liquid crystal display device according to the first embodiment in the order of steps;
  • FIG. 7 is a reflective liquid crystal display device according to the first embodiment of the present invention.
  • Sectional drawing (No. 5) showing the manufacturing method of the module for use in the order of steps;
  • FIG. 8 is a cross-sectional view (part 6) illustrating a method for manufacturing a module for a reflective liquid crystal display device according to the first embodiment of the present invention in the order of steps;
  • FIG. 9 is a sectional view (No. 7) showing the method of manufacturing the module for the reflective liquid crystal display device according to the first embodiment of the present invention in the order of steps;
  • FIG. 10 is a sectional view (No. 8) showing a method for manufacturing a module for a reflective liquid crystal display device according to the first embodiment of the present invention in the order of steps;
  • FIG. 11 is a cross-sectional view (No. 9) showing a method for manufacturing a module for a reflective liquid crystal display device according to the first embodiment of the present invention in the order of steps;
  • FIG. 12 is a cross-sectional view (No. 10) showing a method of manufacturing a module for a reflective liquid crystal display device according to the first embodiment of the present invention in the order of steps;
  • FIG. 13 is a cross-sectional view (No. 11) showing a method for manufacturing a module for a reflective liquid crystal display device according to the first embodiment of the present invention in the order of steps;
  • FIG. 14 is a cross-sectional view illustrating the method of manufacturing the reflective liquid crystal display device according to the first embodiment of the present invention.
  • FIG. 15 is a perspective view (No. 1) showing the method of manufacturing the module for a reflective liquid crystal display device according to the first embodiment of the present invention
  • FIG. 16 is a perspective view (part 2) showing the method of manufacturing the module for a reflective liquid crystal display device according to the first embodiment of the present invention
  • FIG. 17 shows a module for a reflective liquid crystal display device according to the second embodiment of the present invention.
  • FIG. 18 is a cross-sectional view (No. 1) showing a method of manufacturing a module in the order of steps;
  • FIG. 18 is a cross-sectional view showing a method of manufacturing a module for a reflective liquid crystal display device according to the second embodiment of the present invention in the order of steps. (Part 2);
  • FIG. 19 is a cross-sectional view (No. 3) illustrating a method for manufacturing a module for a reflective liquid crystal display device according to the second embodiment of the present invention in the order of steps.
  • 3 to 13 are cross-sectional views illustrating a method of manufacturing a module for a reflective liquid crystal display device according to the present embodiment in the order of steps.
  • an SiO 2 film is formed as an element isolation insulating film 2 on a part of the surface of a p-type silicon (semiconductor) substrate 1 by a LOCOS (Local Oxidation of Silicon) method.
  • LOCOS Local Oxidation of Silicon
  • an element isolation structure other than LOCOS for example, STI (Shallow Trench Isolation) may be adopted.
  • a p-type impurity is introduced into the silicon substrate 1 exposed between the element isolation insulating films 2 to form a p-well 3, and then the exposed silicon substrate 1 is thermally oxidized to form a silicon oxide film 4. .
  • a polysilicon film is formed as the first conductive film 5 on the entire surface to a thickness of about 18 O nm by low-pressure CVD using silane (SiH 4 ) gas at a substrate temperature of 62 ° C. I do.
  • the dielectric film 6 is formed to a thickness of about 28 nm.
  • a polysilicon film is formed to a thickness of about 10 O nm as the second conductive film 7 on the dielectric film 6 by a low-pressure CVD method using silane gas at a substrate temperature of about 530. I do.
  • the first register in the shape of the upper electrode After the strike pattern 8 is formed on the second conductive film 7, the second conductive film 7 is etched using the first resist pattern 8 as a mask, and the remaining second conductive film 7 is a.
  • This etching is performed by, for example, RIE (Reactive Ion Etching) using a mixed gas of Cl 2 and O 2 as an etching gas.
  • the first resist pattern 8 is removed.
  • a second resist pattern 9 having a capacitor dielectric film shape and covering the upper surface and side surfaces of the upper electrode 7a is formed, and the second resist pattern 9 is formed.
  • the dielectric film 6 made of Si0 2 while using as a mask Uetsu preparative etched with HF (hydrofluoric acid) solution, the dielectric film 6 remaining below the upper electrode 7 a and the capacitor dielectric film 6 a. After this, the second resist pattern 9 is removed.
  • a third resist pattern 10 having a pattern covering the capacitor dielectric film 6a and the upper electrode 7a and a gate electrode-shaped pattern is formed as a first conductive film.
  • the third resist pattern 10 is etched by, for example, RIE using a mixed gas of Cl 2 and O 2 as an etching gas.
  • the first conductive film 5 under the capacitor dielectric film 6a is left as the lower electrode 5a, and the capacitor formed by the lower electrode 5a, the capacitor dielectric film 6a, and the upper electrode 7a.
  • Q is formed on the element isolation insulating film 2.
  • the first conductive film 5 remains as the gate electrode 5 b under the third resist pattern 10.
  • the silicon oxide film 4 is etched with an HF aqueous solution to leave the silicon oxide film 4 as a gate insulating film 4a under the gate electrode 5b.
  • the resist pattern used for ion implantation is removed.
  • steps required until a sectional structure shown in FIG. First formed by a CVD method using an oxidizing agent and a silane gas such as N 2 0 as a reaction gas, under conditions of a substrate temperature of 8 0 0 ° C, to about Si0 2 film having a thickness of about 1 0 O nm on the entire surface I do. Then, the Si0 2 film is anisotropically etched, leaving the Si0 2 film only on each side of the gate electrodes 5 b and the upper electrode 7 a, remaining the Si0 2 film first, second sidewall insulating films 1 and 13, respectively.
  • a silane gas such as N 2 0 as a reaction gas
  • first and second n-type impurity diffusion regions 11 a and 11 b are LDD (lightly-lighted) by implanting phosphorus again into the p-well 3 using the first side wall insulating film 12 as a mask. Doped Drain) structure.
  • a cobalt film is formed as a refractory metal film to a thickness of about 9 nm on the entire surface by sputtering. Then, in a N 2 atmosphere, the cobalt film is annealed at a substrate temperature of 520 ° C. for about 30 seconds, so that the cobalt film reacts with silicon on the p-well 3, and the first and second n-types are formed. First and second cobalt silicide layers 14a and 14b are formed in the surface layer of the impurity diffusion regions 11a and 11b. Thereafter, the unreacted cobalt film is removed by etching.
  • the MOS transistor TR having the gate electrode 5b and the first and second impurity diffusion regions 11a and lib functioning as the source / drain regions is formed on the p-well 3.
  • the HF frequency is 13.56 MHz
  • the noise power is 210 W.
  • the frequency of the LF is 400 KHz and the power is 300 W.
  • the flow rate of each gas for example silane gas is 8 0 sccm
  • Ar gas is set to 4 4 O sccm
  • 0 2 force SI 1 5 sccm the pressure during film formation is 1 0 mTorr
  • the first buried insulating film 15 formed by such an HDPCVD method has an extremely good burying property, so that a narrow portion sandwiched between the MOS transistor TR, the capacitor Q, etc. can be formed without generating a void. Can be embedded, and its surface shape reflects the shape of the base.
  • the Si0 approximately 2 film thickness of about 8 0 O nm as the first sacrificial insulating film 1-6 is formed on the Si0 approximately 2 film thickness of about 8 0 O nm as the first sacrificial insulating film 1-6 by a plasma CVD method using TEOS as reactive gas.
  • the first sacrificial insulating film 16 is polished by a CMP (Chemical Mechanical Polishing) method to flatten its surface, and is composed of the first buried insulating film 15 and the first sacrificial insulating film 16.
  • the thickness of the first interlayer insulating film 17 is set to about 100 O nm.
  • the first and second contact holes 17a and 17b which reach the first and second n-type impurity diffusion regions 1 la and lib, are first interlayer insulating.
  • a third contact hole 17c having a depth reaching the upper electrode 7a is formed on the capacitor Q while being formed on the film 17.
  • a ⁇ film is formed to a thickness of about 5 O nm as a glue film on the inner surfaces of the contact holes 17 a to 17 c and the upper surface of the first interlayer insulating film 17 by sputtering.
  • a tungsten film is formed on the glue film by a CVD method using tungsten hexafluoride gas, and the contact holes 17a to 17c are completely filled with the tungsten film.
  • the excess glue film and the tungsten film formed on the upper surface of the first interlayer insulating film 17 are removed by the CMP method, and the dull film remaining in each of the contact holes 17a to 17c is removed.
  • the tungsten film are referred to as first to third conductive plugs 18a to 18c.
  • the first and second conductive plugs 18a and 18b are electrically connected to the first and second n-type impurity diffusion regions 11a and lib.
  • the third conductive plug 18 c is electrically connected to the upper electrode 7 a of the capacitor Q.
  • a metal laminated film is formed on the first interlayer insulating film 17 and the first to third conductive plugs 18a to 18c by a sputtering method.
  • the metal laminated film includes, for example, a Ti film having a thickness of 40 nm, a TiN film having a thickness of 30 nm, an Al film containing Cu having a thickness of 500 nm, a Ti film having a thickness of 5 nm, and a thickness of 5 nm. It is formed by laminating 100 nm TiN films in this order.
  • the metal laminated film is patterned to form first and second metal wirings 19a and 19b.
  • the second metal wiring 19 b is formed on the second and third conductive plugs 18 b and 18 c, and the upper electrode 7 a of the capacitor Q and the second n-type impurity diffusion region 1 Functions to electrically connect 1b.
  • the metal wirings 19a and 19b are formed on the metal wirings 19a and 19b.
  • a SiO 2 film is formed on the interlayer insulating film 17 to a thickness of about 80 O nm, and is used as a second buried insulating film 20.
  • the conditions for forming the second buried insulating film 20 are the same as those for forming the first buried insulating film 15.
  • a SiO 2 film having a thickness of about 13 was formed as a second sacrificial insulating film 21 on the second buried insulating film 20 by the same plasma CVD method as used for forming the first sacrificial insulating film 16. Form at 0 O nm. Then, the second sacrificial insulating film 21 is polished by the CMP method, and the second interlayer insulating film 22 composed of the insulating films 20 and 21 is formed on the metal wirings 19 a and 19 b. The thickness is about 100 O nm.
  • a metal laminated film is formed on the second interlayer insulating film 22 by a sputtering method, and the metal laminated film is patterned to form a light shielding film 23. Constructing the light shielding film 23 ⁇
  • the metal laminated film for example, an aluminum film is adopted.
  • the shading film 2 3 and on the third buried insulating film 2 4 as Si0 2 forms film to a thickness of about 8 0 O nm on the second interlayer insulating film 2 2 above,
  • the space between the adjacent light shielding films 23 is buried by the third buried insulating film 24.
  • the film forming conditions for the third buried insulating film 24 the same film forming conditions as for the first buried insulating film 17 are employed.
  • a SiO 2 film is formed on the third buried insulating film 24 to a thickness of about 130 nm, This is referred to as a third sacrificial insulating film 25.
  • the third interlayer insulating film (first insulating film) 26 composed of the insulating films 24 and 25 is polished by the CMP method, and the thickness of the third interlayer insulating film 26 on the light shielding film 23 is increased. To about 95 O nm.
  • a hole 27 having a depth reaching the second metal wiring 19 b is formed in the second and third interlayer insulating films 22 and 26, and the inner surface of the hole 27 and the third interlayer insulating film 26 are formed.
  • a TiN film with a thickness of about 5 O nm is formed on the upper surface as a glue film.
  • a tungsten film having a thickness completely burying the hole 27 is formed on the glue film by a CVD method, and then an excess dull film and a tungsten film formed on the upper surface of the third interlayer insulating film 26 are formed.
  • the fourth conductive plug 28 is electrically connected to the second metal wiring 19b.
  • the fourth resist pattern 37 is formed along the boundary between adjacent pixels, and has a width W of about 0.5 m.
  • a silicon substrate 1 in a chamber (not shown) for performing plasma etching is placed, and a deposition CHF 3 gas and an etching CF 4 gas are supplied as etching gases into the chamber.
  • the etching gas 0 2 is also added.
  • the flow rate of the etching gas is adjusted so that the deposition gas is higher than the etching gas.
  • the flow rate of the CHF 3 gas is more than 1 and less than twice the flow rate of the CF 4 gas. .
  • the spacer insulating film 29 is isotropically etched as shown in FIG. As a result, the spacer insulating film 29 is left under the fourth resist pattern 37 as an insulating spacer 29 a having a tapered cross section. Thereafter, the fourth register pattern 37 is removed.
  • FIG. 15 An enlarged perspective view after the completion of this step is as shown in FIG. 15, and FIG. 11 corresponds to a cross-sectional view taken along the line II of FIG.
  • the insulating spacer 29a has an opening 29b for each pixel, and the upper surface of the fourth conductive plug 28 is exposed in the opening 29b.
  • an aluminum film is formed as a third conductive film 30 on the third interlayer insulating film 26 in the opening 29 b and on the insulating spacer 29 a by a sputtering method.
  • the opening 29 b of the spacer 29 is filled with the third conductive film 30.
  • the third conductive film 30 is formed by aluminum sputter. However, if the substrate temperature during sputtering is high, the aluminum grain size increases, and the third conductive film 30 becomes a reflective electrode later. (3) The reflectance of the conductive film 30 is reduced.
  • the substrate temperature during the formation of the third conductive film 30 is preferably set as low as possible.
  • the substrate temperature is set at room temperature (20 ° C.) to 350 ° C., preferably. Is 260 ° C.
  • the third conductive film 30 was polished by the CMP method to the extent that the insulating spacer 29a was exposed, using SSW2000 (trade name, manufactured by CABOT) as a slurry. As shown, the third conductive film 30 is left as the reflective electrode 30a in the opening 29b.
  • your polishing rate of the third conductive film 3 0 and the insulating spacer 2 9 a have the same value of about 300 n m / min Both the third conductive film 3 0 and the insulating spacer 2 Either one of 9a will not be polished excessively more than the other.
  • the polishing amount of the CMP is controlled by time.
  • the LCOS substrate according to the present embodiment (reflective liquid crystal display) Module for device) 40 basic structure is completed.
  • An enlarged perspective view of the LCOS substrate 40 is as shown in FIG. 16, and FIG. 13 corresponds to a cross-sectional view taken along a line II-III of FIG.
  • the process proceeds to a step of attaching the liquid crystal panel manufactured in a different process from the above to the LCOS substrate 40.
  • the liquid crystal panel 31 is adhered to the LCOS substrate 40 by a sealing material (not shown), and is provided between the lower liquid crystal alignment film 32 and the upper liquid crystal alignment film 34. It has a liquid crystal layer 33 arranged. Then, a common electrode 35 made of a transparent conductive material such as ITO (Indium Titan Oxide) is formed on the upper liquid crystal alignment film 34, and the liquid crystal layer 33 is formed on the common electrode 35 from external impact. Is provided with a surface glass for protecting the glass.
  • ITO Indium Titan Oxide
  • the transistor TR is turned on, and the voltage of the first metal wiring 19a is applied to the reflective electrode 30a, so that a pixel is formed on the liquid crystal layer 33 on the reflective electrode 30a.
  • a voltage is applied every time.
  • the incident light obliquely incident from the surface glass 36 is polarized in a predetermined direction according to the voltage value of the reflective electrode 30a, and is reflected by the reflective electrode 30a and emitted to the outside again.
  • a predetermined display is provided to the user by passing through an analyzer 114 as shown in FIG.
  • the display screen does not change even if the transistor TR is turned off, and the display state can be held.
  • the third conductive film 30 is formed on the insulating spacer 29 a and in the opening 29 b. Then, the third conductive film 30 is polished by the CMP method and left as the reflective electrode 30a in the opening 28b, so that the upper surface of the reflective electrode 30a becomes flat, and the upper surface becomes an insulating spacer. It is the same height as the upper surface of 29a. As a result, as shown in FIG. 14, even when the liquid crystal panel 31 is attached on the reflective electrode 30a, a gap is formed between the liquid crystal panel 31 and the insulating spacer 29a. Because it is not Thus, it is possible to provide a reflection type liquid crystal display device in which scattering of incident light is prevented, color tone is good, and contrast is enhanced.
  • the cross-sectional shape of the insulating spacer 29a is tapered, so that the upper surface where the width of the insulating spacer 29a is narrow allows adjacent reflections.
  • the distance d between the electrodes 30a is extremely short. Therefore, the reflection electrodes 30a are arranged at a very high density, so that the incident light scattered by the insulating spacer 29a is reduced, and most of the incident light is reflected by the reflection electrodes 30a. Reflected by a, the reflectance of the entire LCOS substrate 40 is improved, and the contrast is improved.
  • the substrate temperature is kept at a low temperature of about room temperature to about 350 ° C., so that the grains of the aluminum film do not grow significantly. Irregularities on the surface of the aluminum film are reduced, and the reflectance of the reflective electrode 30a itself can be improved.
  • This embodiment is different from the first embodiment in a method of forming a tapered insulating spacer 29a, and is otherwise the same as the first embodiment.
  • 17 to 19 are cross-sectional views illustrating a method of manufacturing the module for a reflective liquid crystal display device according to the present embodiment in the order of steps.
  • members already described in the first embodiment are denoted by the same reference numerals as in the first embodiment.
  • the silicon substrate 1 is placed on a hot plate, and the substrate temperature is set to 120 ° C. to 130 ° C. in an atmosphere of N 2 ( : The silicon substrate 1 is heated so as to become: When the silicon substrate 1 is heated in this way, the fourth resist pattern 37 is melted by heat and its shape collapses, as shown in FIG.
  • Etsuchin grayed is, CHF 3 to a mixed gas of gas and CF 4 gas, the mixed flow rate is not multi than gas 0 2, for example about 5 0 0 sccm flow rate of 0 2 etching gas obtained by adding Can be performed by using plasma etching.
  • the cross-sectional shape of the tapered fourth resist pattern 37 is transferred to the spacer insulating film 29, and an insulating spacer 29a having a tapered cross section is formed.
  • the insulating spacer 29a has an opening 29b for each pixel, and the upper surface of the fourth conductive plug 28 is formed from the opening 29b. Exposed.
  • the fourth resist pattern 37 is etched and removed at the same time as the formation of the insulating spacer 29a.
  • the step of removing the fourth resist pattern 37 again as in the embodiment is not required, so that the manufacturing process of the LCOS substrate can be simplified, and the manufacturing cost of the LCOS substrate can be reduced.
  • the conductive film is polished into the reflective electrode, the upper surfaces of the reflective electrode and the insulating spacer have the same height. Therefore, even if the liquid crystal panel is attached on the reflective electrode, no gap is formed between the liquid crystal panel and the insulating spacer, so that a reflective liquid crystal display module with good color tone and high contrast is provided. Can be realized.
  • the reflection electrodes can be arranged at a high density, and the reflectance of the entire reflection type liquid crystal display module can be increased.
  • the aluminum film is used as a reflective electrode and the aluminum film is formed by a sputtering method at a low substrate temperature of room temperature or higher and 350 ° C or lower, the grain size of the aluminum film is reduced, and the reflection of the reflective electrode is reduced. Rates can be higher.

Abstract

A method for manufacturing a module for reflection liquid crystal displays, characterized by comprising the steps of forming a third interlayer insulating film (first insulating film) (26) over a silicon (semiconductor) substrate (1), forming an insulating film (second insulating film) (29) for a spacer on the third interlayer insulating film (26), forming an insulating spacer (29a) having an opening (29b) for each pixel by patterning the insulating film (29), forming a conductive film (30) on the insulating spacer (29a) and on the third interlayer insulating film (26) in the opening (29b), and polishing the conductive film (30) to an extent that the insulating spacer (29a) becomes exposed, thereby making the conductive film (30) left in the opening (29b) a reflection electrode (30a).

Description

明 細 書 反射型液晶表示装置用モジュールとその製造方法、 及び反射型液晶表示装 置 技術分野  Description Reflective liquid crystal display module, method of manufacturing the same, and reflective liquid crystal display
本発明は、 反射型液晶表示装置用モジュールとその製造方法、 及び反射 型液晶表示装置に関する。 より詳細には、 本発明は、 表示品質が良好な反 射型液晶表示装置用モジュールとその製造方法、 及び反射型液晶表示装置 に関する。 背景技術  The present invention relates to a reflection type liquid crystal display device module, a method for manufacturing the same, and a reflection type liquid crystal display device. More specifically, the present invention relates to a reflective liquid crystal display module having good display quality, a method for manufacturing the same, and a reflective liquid crystal display device. Background art
近年、 ヘッドマウントディスプレイや投射型ディスプレイとして、 シリ コンチップ ·ベースド液晶といわれる反射型液晶表示装置が注目されてい る。 以下に、 従来例に係るこの反射型液晶表示装置の製造方法について図 In recent years, a reflection type liquid crystal display device called a silicon chip-based liquid crystal has been attracting attention as a head mounted display or a projection type display. Hereinafter, a method for manufacturing the reflection type liquid crystal display device according to the conventional example will be described.
1 ( a )、 ( b ) を参照しながら説明する。 1 This will be described with reference to (a) and (b).
最初に、図 1 ( a )に示す断面構造を得るまでの工程について説明する。 まず、 表面に MOS トランジスタが作成されたシリコンウェハ (不図示) の上方に層間絶縁膜 1 0 1を成膜し、 次いで、 フォトリソグラフィ法とェ ツチング工程によりその層間絶縁膜 1 0 1に第 1、 第 2ホール 1 0 1 a、 1 0 1 bを形成する。 続いて、 上記の MOS トランジスタのソース · ドレ イン領域に接続される第 1、 第 2導電性プラグ 1 0 2 a、 1 0 2 bをこの 第 1、 第 2ホール 1 0 1 a、 1 0 l b内に形成する。  First, steps required until a sectional structure shown in FIG. First, an interlayer insulating film 101 is formed above a silicon wafer (not shown) on which MOS transistors are formed on the surface, and then the first interlayer insulating film 101 is formed on the interlayer insulating film 101 by a photolithography method and an etching step. The second holes 101a and 101b are formed. Subsequently, the first and second conductive plugs 102 a and 102 b connected to the source / drain regions of the MOS transistor are connected to the first and second holes 101 a and 100 lb. Form within.
次いで、 層間絶縁膜 1 0 1と各導電性プラグ 1 0 2 a、 1 0 2 bのそれ ぞれの上面上に金属膜を形成した後に、 その金属膜をパタ一エングして各 導電性プラグ 1 0 2 a、 1 0 2 b上に第 1反射電極 1 0 3 a、 第 2反射電 極 1 0 3 bとして残す。  Next, after forming a metal film on the upper surface of each of the interlayer insulating film 101 and each of the conductive plugs 102a and 102b, the metal film is patterned to form each conductive plug. The first reflective electrode 103a and the second reflective electrode 103b are left on 102a and 102b.
その後に、各反射電極 1 0 3 a、 1 0 3 b間のギヤップを埋めるために、 全面に絶縁膜を形成し、 その絶縁膜を CMP法によって研磨したり、 或い はエッチバックすることにより、 各反射電極 1 0 3 a、 1 0 3 b間のギヤ ップに残った絶縁膜を埋め込み絶縁膜 1 0 4とする。 After that, in order to fill the gap between the reflective electrodes 103a and 103b, an insulating film is formed on the entire surface, and the insulating film is polished by CMP method or etched back. , Gear between each reflective electrode 103a, 103b The insulating film remaining in the gap is a buried insulating film 104.
ここまでの工程により、 LCOS(Liquid Crystal on Silicon)基板 1 0 5が完 成する。  Through the steps so far, the LCOS (Liquid Crystal on Silicon) substrate 105 is completed.
次に、 図 1 ( b ) に示すように、 別の工程で作成された液晶パネル 1 0 6を不図示のシール材によってこの LCOS基板 1 0 5上に接合する。 その 液晶パネル 1 0 6は、 下部液晶配向層 1 0 7と上部液晶配向層 1 0 9との 間に液晶層 1 0 8が封入され、 その上部液晶配向層 1 0 9の上には透明な コモン電極 1 1 0が形成されると共に、 液晶パネル 1 0 6の表面を外部の 衝撃から保護するための表面ガラス 1 1 1をコモン電極 1 1 0上に有す る。  Next, as shown in FIG. 1 (b), a liquid crystal panel 106 formed in another step is bonded onto the LCOS substrate 105 by a sealing material (not shown). In the liquid crystal panel 106, a liquid crystal layer 108 is sealed between the lower liquid crystal alignment layer 107 and the upper liquid crystal alignment layer 109, and a transparent liquid crystal is formed on the upper liquid crystal alignment layer 109. The common electrode 110 is formed, and the surface glass 111 for protecting the surface of the liquid crystal panel 106 from external impact is provided on the common electrode 110.
以上により、 従来例に係る反射型液晶表示装置 1 1 5の基本構造が完成 する。  As described above, the basic structure of the reflective liquid crystal display device 115 according to the conventional example is completed.
この反射型液晶表示装置 1 1 5では、 第 1、 第 2反射電極 1 0 3 a、 1 0 3 bによって画素が画定され、 各反射電極 1 0 3 a、 1 0 3 bの電圧値 を不図示の MOS トランジスタによって個別に変化させることにより、 コ モン電極 1 1 0と各反射電極 1 0 3 a、 1 0 3 bとの間の電位差を制御し、 その電位差に応じて液晶層 1 0 6の配向を画素毎に制御する。  In this reflective liquid crystal display device 115, pixels are defined by the first and second reflective electrodes 103a and 103b, and the voltage value of each reflective electrode 103a and 103b is not changed. The potential difference between the common electrode 110 and each of the reflective electrodes 103 a and 103 b is controlled by individually changing the MOS transistors shown in the figure, and the liquid crystal layer 106 is controlled according to the potential difference. Is controlled for each pixel.
そして、 図 2に示すように、 3色の発光ダイオードで構成される光源 1 1 2から出た光を偏光子 1 1 3により 1方向に偏光させ、 得られた偏光を 反射型液晶表示装置 1 1 5に斜めに入れる。 入射した光は、 液晶層 1 0 8 を通過して各反射電極 1 0 3 a、 1 0 3 bにより反射し、 再び液晶層 1 0 8を通過して外に出る。 光が液晶層 1 0 8を通過するとき、 液晶層 1 0 8 の配向に応じてその光の偏光方向が捩れるので、 出てきた光を検光子 1 1 4に通すことにより、 画素毎に光の強度が制御された画像を得ることがで きる。  Then, as shown in FIG. 2, light emitted from a light source 112 composed of light emitting diodes of three colors is polarized in one direction by a polarizer 113, and the obtained polarized light is reflected by a reflective liquid crystal display device 1. 1 Insert diagonally into 5. The incident light passes through the liquid crystal layer 108, is reflected by each of the reflective electrodes 103a and 103b, passes through the liquid crystal layer 108 again, and goes out. When the light passes through the liquid crystal layer 108, the polarization direction of the light is twisted according to the orientation of the liquid crystal layer 108. An image with a controlled light intensity can be obtained.
ところで、 図 1 ( a ) に示した LCOS基板 1 0 5の製造方法では、 CMP 法やエッチバック法により埋め込み絶縁膜 1 0 4を反射電極 1 0 3 a、 1 0 3 b間のギャップに残しているが、 CMPやエツチバックの終点検出を絶 縁膜に対して制度良く行うのは難しいので、 埋め込み絶縁膜 1 0 4が過剰 に研磨され、 埋め込み絶縁膜 1 0 4の上面が各反射電極 1 0 3 a、 1 0 3 bの上面よりも沈み込み易くなり、 LCOS基板 1 0 5の上面の平坦性が悪 くなる。 By the way, in the method of manufacturing the LCOS substrate 105 shown in FIG. 1A, the buried insulating film 104 is left in the gap between the reflective electrodes 103a and 103b by the CMP method or the etch-back method. However, it is difficult to detect the end point of CMP or etch back on the insulating film in a systematic manner, so the buried insulating film 104 is excessively polished, and the upper surface of the buried insulating film 104 0 3 a, 1 0 3 It becomes easier to sink than the upper surface of b, and the flatness of the upper surface of the LCOS substrate 105 becomes worse.
しかしながら、 このように平坦性が悪い LCOS基板 1 0 5上に液晶パネ ル 1 0 6を接合すると、 埋め込み絶縁膜 1 0 4と液晶パネル 1 0 6との間 に空隙 1 1 2が形成され、 その空隙 1 1 2によって入射光が散乱されて色 調が不良となったり、 コントラストが低下するといつた不都合を招いてし まう。 発明の開示  However, when the liquid crystal panel 106 is bonded on the LCOS substrate 105 having such poor flatness, a gap 112 is formed between the buried insulating film 104 and the liquid crystal panel 106. When the incident light is scattered by the gaps 1 and 12, the color tone becomes poor, and when the contrast is lowered, some inconvenience is caused. Disclosure of the invention
本発明の目的は、 コントラストの低下や色調不良を防止することができ る反射型液晶表示装置用モジュールとその製造方法、 及び反射型液晶表示 装置を提供することにある。  An object of the present invention is to provide a reflection type liquid crystal display module capable of preventing a decrease in contrast and poor color tone, a method for manufacturing the same, and a reflection type liquid crystal display device.
本発明の一観点によれば、 半導体基板と、 前記半導体基板の上方に形成 された絶縁膜と、 前記絶縁膜上に形成され、 画素毎に開口を有する絶縁性 スぺーサと、 前記絶縁性スぺ一サの開口内に形成され、 前記絶縁性スぺー サの上面と同じ高さの平坦な上面を有する反射電極と、 を有することを特 徵とする反射型液晶表示装置用モジュールが提供される。  According to one aspect of the present invention, a semiconductor substrate; an insulating film formed above the semiconductor substrate; an insulating spacer formed on the insulating film, having an opening for each pixel; A reflective electrode formed in the opening of the spacer and having a flat upper surface at the same height as the upper surface of the insulating spacer; and a module for a reflective liquid crystal display device, comprising: Is done.
また、 本発明の別の観点によれば、 半導体基板の上方に第 1絶縁膜を形 成する工程と、 前記第 1絶縁膜の上に第 2絶縁膜を形成する工程と、 前記 第 2絶縁膜をパターニングすることにより、 画素毎に開口を有する絶縁性 スぺーサを形成する工程と、 前記絶縁性スぺーサ上と前記開口内の前記第 According to another aspect of the present invention, a step of forming a first insulating film above a semiconductor substrate; a step of forming a second insulating film on the first insulating film; Forming an insulating spacer having an opening for each pixel by patterning the film; and forming the insulating spacer on the insulating spacer and in the opening in the opening.
1絶縁膜上とに導電膜を形成する工程と、 前記絶縁性スぺーザが露出する 程度に前記導電膜を研磨し、 前記開口内に残った前記導電膜を反射電極と する工程と、 を有することを特徴とする反射型液晶表示装置用モジュール の製造方法が提供される。 1) a step of forming a conductive film on the insulating film, and a step of polishing the conductive film to such an extent that the insulating spacer is exposed, and using the conductive film remaining in the opening as a reflective electrode. A method for manufacturing a module for a reflection type liquid crystal display device, comprising:
次に、 本発明の作用について説明する。  Next, the operation of the present invention will be described.
本発明によれば、 絶縁性スぺーザが露出する程度に導電膜を研磨し、 絶 縁性スぺーザの開口内に残された導電膜を反射電極とするので、 反射電極 の上面が平坦となると共に、 該上面が絶縁性スぺーザの上面と同じ高さに なる。 従って、 反射電極の上に液晶パネルを貼り付けても、 液晶パネルと 絶縁性スぺーサとの間に従来のような空隙が形成されないので、 空隙によ る入射光の散乱が防止される。 その結果、 液晶パネルとの組み合わせによ つて、 色調が良好にされ、 且つコントラストが高められる反射型液晶表示 用モジュールが実現される。 According to the present invention, the conductive film is polished to such an extent that the insulating spacer is exposed, and the conductive film remaining in the opening of the insulating spacer is used as the reflective electrode, so that the upper surface of the reflective electrode is flat. And the upper surface is at the same height as the upper surface of the insulating spacer. Therefore, even if the liquid crystal panel is pasted on the reflective electrode, Since a gap is not formed between the insulating spacer and the insulating spacer as in the related art, scattering of incident light due to the gap is prevented. As a result, a combination of the liquid crystal panel and the liquid crystal panel realizes a reflection type liquid crystal display module in which the color tone is improved and the contrast is enhanced.
更に、 絶縁性スぺーサの断面形状をテ一パ一状にすることにより、 絶縁 性スぺーサの幅が細い上面によって、 隣接する反射電極同士の間隔が極め て短くなる。 これにより、 各反射電極が非常に高密度に配列されるので、 絶縁性スぺーサによって散乱される入射光が減り、 入射光の大部分が反射 電極で反射されるようになり、 反射型液晶表示用モジュール全体の反射率 が向上する。  Further, by making the cross-sectional shape of the insulating spacer into a tapered shape, the interval between adjacent reflective electrodes becomes extremely short due to the narrow upper surface of the insulating spacer. As a result, the reflection electrodes are arranged at a very high density, so that the incident light scattered by the insulating spacer is reduced, and most of the incident light is reflected by the reflection electrode. The reflectance of the entire display module is improved.
絶縁性スぺーサの断面形状を上記のようなテーパー状にするには、 例え ば、 上記第 2絶縁膜の上にレジストパターンを形成し、 エッチング性ガス と、 該エッチング性ガスよりも流量が大きい堆積性ガスとの混合ガスをェ ツチングガスとして使用して、 上記レジストパターンをマスクにしながら 第 2絶縁膜をエッチングすればよい。  In order to make the cross-sectional shape of the insulating spacer tapered as described above, for example, a resist pattern is formed on the second insulating film, and the etching gas and the flow rate are higher than the etching gas. Using a mixed gas with a large deposition gas as an etching gas, the second insulating film may be etched using the resist pattern as a mask.
或いは、 これに代えて、 上記第 2絶縁膜の上にレジストパターンを形成 し、 このレジストパターンを加熱して溶融することにより、 該レジストパ ターンの断面形状を崩し、 レジストパターンと第 2絶縁膜とを同時にエツ チングすることによつても、 断面がテーパー状の絶縁性スぺーサを形成す ることができる。  Alternatively, instead of this, a resist pattern is formed on the second insulating film, and the resist pattern is heated and melted to break the cross-sectional shape of the resist pattern, and the resist pattern and the second insulating film Also, by etching simultaneously, an insulating spacer having a tapered cross section can be formed.
また、 反射電極となる導電膜としてアルミニウム膜を形成する場合は、 基板温度を室温 (2 0 °C ) 以上 3 5 0 °C以下の低温にするスパッ夕法によ りそのアルミニウム膜を形成すると、 アルミニウム膜のグレインが大きく 成長しないので、 アルミニウム膜の表面の凹凸が小さくなり、 高い反射率 を有する反射電極が得られる。 図面の簡単な説明  In the case where an aluminum film is formed as a conductive film serving as a reflective electrode, the aluminum film is formed by a sputtering method in which the substrate temperature is kept at a low temperature of room temperature (20 ° C.) to 350 ° C. However, since the grains of the aluminum film do not grow large, the irregularities on the surface of the aluminum film are reduced, and a reflective electrode having a high reflectance can be obtained. Brief Description of Drawings
図 1 ( a )、 ( b ) は、 従来例に係る反射型液晶表示装置の製造方法につ いて説明するための断面図であり ;  FIGS. 1 (a) and 1 (b) are cross-sectional views for explaining a method of manufacturing a reflection type liquid crystal display device according to a conventional example;
図 2は、 シリコンチップ ·ベ一スド液晶を使用した反射型液晶表示装置 を模式的に示す原理図であり ; Figure 2 shows a reflective liquid crystal display using silicon chip-based liquid crystal. It is a principle diagram schematically showing;
図 3 (a)、 (b) は、 本発明の第 1の実施の形態に係る反射型液晶表示 装置用モジュールの製造方法を工程順に示す断面図 (その 1) であり ; 図 4 (a)、 (b) は、 本発明の第 1の実施の形態に係る反射型液晶表示 装置用モジュールの製造方法を工程順に示す断面図 (その 2) であり ; 図 5 (a)、 (b) は、 本発明の第 1の実施の形態に係る反射型液晶表示 装置用モジュールの製造方法を工程順に示す断面図 (その 3) であり ; 図 6 (a)、 (b) は、 本発明の第 1の実施の形態に係る反射型液晶表示 装置用モジュールの製造方法を工程順に示す断面図 (その 4) であり ; 図 7は、 本発明の第 1の実施の形態に係る反射型液晶表示装置用モジュ ールの製造方法を工程順に示す断面図 (その 5) であり ;  3 (a) and 3 (b) are cross-sectional views (part 1) showing a method of manufacturing a reflective liquid crystal display module according to the first embodiment of the present invention in the order of steps; FIG. 5 (a) and 5 (b) are cross-sectional views (part 2) showing a method of manufacturing the reflective liquid crystal display device module according to the first embodiment of the present invention in the order of steps; FIGS. FIGS. 6A and 6B are cross-sectional views showing a method of manufacturing a module for a reflection type liquid crystal display device according to the first embodiment of the present invention in the order of steps; FIGS. FIG. 7 is a cross-sectional view (part 4) showing a method for manufacturing a module for a reflective liquid crystal display device according to the first embodiment in the order of steps; FIG. 7 is a reflective liquid crystal display device according to the first embodiment of the present invention. Sectional drawing (No. 5) showing the manufacturing method of the module for use in the order of steps;
図 8は、 本発明の第 1の実施の形態に係る反射型液晶表示装置用モジュ ールの製造方法を工程順に示す断面図 (その 6) であり ;  FIG. 8 is a cross-sectional view (part 6) illustrating a method for manufacturing a module for a reflective liquid crystal display device according to the first embodiment of the present invention in the order of steps;
図 9は、 本発明の第 1の実施の形態に係る反射型液晶表示装置用モジュ ールの製造方法を工程順に示す断面図 (その 7) であり ;  FIG. 9 is a sectional view (No. 7) showing the method of manufacturing the module for the reflective liquid crystal display device according to the first embodiment of the present invention in the order of steps;
図 1 0は、 本発明の第 1の実施の形態に係る反射型液晶表示装置用モジ ユールの製造方法を工程順に示す断面図 (その 8) であり ;  FIG. 10 is a sectional view (No. 8) showing a method for manufacturing a module for a reflective liquid crystal display device according to the first embodiment of the present invention in the order of steps;
図 1 1は、 本発明の第 1の実施の形態に係る反射型液晶表示装置用モジ ユールの製造方法を工程順に示す断面図 (その 9) であり ;  FIG. 11 is a cross-sectional view (No. 9) showing a method for manufacturing a module for a reflective liquid crystal display device according to the first embodiment of the present invention in the order of steps;
図 1 2は、 本発明の第 1の実施の形態に係る反射型液晶表示装置用モジ ユールの製造方法を工程順に示す断面図 (その 1 0) であり ;  FIG. 12 is a cross-sectional view (No. 10) showing a method of manufacturing a module for a reflective liquid crystal display device according to the first embodiment of the present invention in the order of steps;
図 1 3は、 本発明の第 1の実施の形態に係る反射型液晶表示装置用モジ ユールの製造方法を工程順に示す断面図 (その 1 1 ) であり ;  FIG. 13 is a cross-sectional view (No. 11) showing a method for manufacturing a module for a reflective liquid crystal display device according to the first embodiment of the present invention in the order of steps;
図 1 4は、 本発明の第 1の実施の形態に係る反射型液晶表示装置の製造 方法を示す断面図であり ;  FIG. 14 is a cross-sectional view illustrating the method of manufacturing the reflective liquid crystal display device according to the first embodiment of the present invention;
図 1 5は、 本発明の第 1の実施の形態に係る反射型液晶表示装置用モジ ユールの製造方法を示す斜視図 (その 1 ) であり ;  FIG. 15 is a perspective view (No. 1) showing the method of manufacturing the module for a reflective liquid crystal display device according to the first embodiment of the present invention;
図 1 6は、 本発明の第 1の実施の形態に係る反射型液晶表示装置用モジ ユールの製造方法を示す斜視図 (その 2) であり ;  FIG. 16 is a perspective view (part 2) showing the method of manufacturing the module for a reflective liquid crystal display device according to the first embodiment of the present invention;
図 1 7は、 本発明の第 2の実施の形態に係る反射型液晶表示装置用モジ ユールの製造方法を工程順に示す断面図 (その 1 ) であり ; 図 1 8は、 本発明の第 2の実施の形態に係る反射型液晶表示装置用モジ ユールの製造方法を工程順に示す断面図 (その 2 ) であり ; FIG. 17 shows a module for a reflective liquid crystal display device according to the second embodiment of the present invention. FIG. 18 is a cross-sectional view (No. 1) showing a method of manufacturing a module in the order of steps; FIG. 18 is a cross-sectional view showing a method of manufacturing a module for a reflective liquid crystal display device according to the second embodiment of the present invention in the order of steps. (Part 2);
図 1 9は、 本発明の第 2の実施の形態に係る反射型液晶表示装置用モジ ユールの製造方法を工程順に示す断面図 (その 3 ) である。 発明の実施をするための最良の形態  FIG. 19 is a cross-sectional view (No. 3) illustrating a method for manufacturing a module for a reflective liquid crystal display device according to the second embodiment of the present invention in the order of steps. BEST MODE FOR CARRYING OUT THE INVENTION
以下に本発明の実施形態を図面に基づいて説明する。  Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(第 1実施形態)  (First Embodiment)
図 3〜図 1 3は、 本実施形態に係る反射型液晶表示装置用モジュールの 製造方法を工程順に示す断面図である。  3 to 13 are cross-sectional views illustrating a method of manufacturing a module for a reflective liquid crystal display device according to the present embodiment in the order of steps.
最初に、図 3 ( a )に示す断面構造を得るまでの工程について説明する。 まず、 LOCOS(Local Oxidation of Silicon)法により、 p型シリコン (半導 体)基板 1の表面の一部に素子分離絶縁膜 2として Si02膜を形成する。素 子分離絶縁膜 2としては LOCOS以外の素子分離構造、例えば STI(Shallow Trench Isolation)を採用してもよい。 First, steps required until a sectional structure shown in FIG. First, an SiO 2 film is formed as an element isolation insulating film 2 on a part of the surface of a p-type silicon (semiconductor) substrate 1 by a LOCOS (Local Oxidation of Silicon) method. As the element isolation insulating film 2, an element isolation structure other than LOCOS, for example, STI (Shallow Trench Isolation) may be adopted.
次いで、 素子分離絶縁膜 2の間に露出するシリコン基板 1に p型不純物 を導入して pゥエル 3を形成した後、 露出しているシリコン基板 1を熱酸 化してシリコン酸化膜 4を形成する。  Next, a p-type impurity is introduced into the silicon substrate 1 exposed between the element isolation insulating films 2 to form a p-well 3, and then the exposed silicon substrate 1 is thermally oxidized to form a silicon oxide film 4. .
次に、 図 3 ( b ) に示す断面構造を得るまでの工程について説明する。 まず、 基板温度が 6 2 0 °Cの条件で、 シラン (SiH4) ガスを使用する減 圧 C V Dにより、 第 1導電膜 5としてポリシリコン膜を厚さ約 1 8 O nm 程度に全面に形成する。 Next, steps required until a sectional structure shown in FIG. First, a polysilicon film is formed as the first conductive film 5 on the entire surface to a thickness of about 18 O nm by low-pressure CVD using silane (SiH 4 ) gas at a substrate temperature of 62 ° C. I do.
続いて、 N20等の酸化剤とシランガスとを反応ガスとして使用する減圧 C V D法を用い、 基板温度 8 0 0 °Cの条件下で、 第 1導電膜 5の上に Si02 膜を厚さ約 2 8 nmに形成し、 それを誘電体膜 6とする。 Then, using a low pressure CVD method using an oxidizing agent and a silane gas such as N 2 0 as a reaction gas, under conditions of a substrate temperature of 8 0 0 ° C, the thickness of the Si0 2 film on the first conductive film 5 The dielectric film 6 is formed to a thickness of about 28 nm.
更に、 基板温度が約 5 3 0での条件下で、 シランガスを使用する減圧 C V D法により、 誘電体膜 6の上に第 2導電膜 7としてポリシリコン膜を厚 さ約 1 0 O nmに形成する。  Furthermore, a polysilicon film is formed to a thickness of about 10 O nm as the second conductive film 7 on the dielectric film 6 by a low-pressure CVD method using silane gas at a substrate temperature of about 530. I do.
続いて、 図 4 ( a ) に示すように、 キャパシ夕上部電極形状の第 1 レジ ストパターン 8を第 2導電膜 7上に形成した後、 その第 1レジストパター ン 8をマスクに使用しながら第 2導電膜 7をエッチングし、 これにより残 つた第 2導電膜 7を上部電極 7 aとする。 このエッチングは、 例えば Cl2 と 02 との混合ガスをエッチングガスとして使用する RIE(Reactive Ion Etching)により行われる。 Next, as shown in Fig. 4 (a), the first register in the shape of the upper electrode After the strike pattern 8 is formed on the second conductive film 7, the second conductive film 7 is etched using the first resist pattern 8 as a mask, and the remaining second conductive film 7 is a. This etching is performed by, for example, RIE (Reactive Ion Etching) using a mixed gas of Cl 2 and O 2 as an etching gas.
その後に、 第 1レジストパターン 8は除去される。  After that, the first resist pattern 8 is removed.
次に、 図 4 ( b ) に示すように、 キャパシタ誘電体膜形状を有し、 且つ 上部電極 7 aの上面と側面とを覆う第 2レジストパターン 9を形成し、 そ の第 2レジストパターン 9をマスクに使用しながら Si02よりなる誘電体 膜 6を HF (弗酸)溶液でゥエツ トエッチングし、上部電極 7 aの下に残った 誘電体膜 6をキャパシタ誘電体膜 6 aとする。 この後に、 第 2レジストパ ターン 9は除去される。 Next, as shown in FIG. 4 (b), a second resist pattern 9 having a capacitor dielectric film shape and covering the upper surface and side surfaces of the upper electrode 7a is formed, and the second resist pattern 9 is formed. the dielectric film 6 made of Si0 2 while using as a mask Uetsu preparative etched with HF (hydrofluoric acid) solution, the dielectric film 6 remaining below the upper electrode 7 a and the capacitor dielectric film 6 a. After this, the second resist pattern 9 is removed.
続いて、 図 5 ( a ) に示すように、 キャパシタ誘電体膜 6 aと上部電極 7 aとを覆うパターンと、 ゲート電極形状のパターンとを有する第 3レジ ストパターン 1 0を第 1導電膜 5上に形成する。 そして、 この第 3レジス トパターン 1 0をエッチングマスクに使用し、 例えば Cl2と 02との混合 ガスをエッチングガスとする RIE により第 1導電膜 5をエッチングす る。 Subsequently, as shown in FIG. 5 (a), a third resist pattern 10 having a pattern covering the capacitor dielectric film 6a and the upper electrode 7a and a gate electrode-shaped pattern is formed as a first conductive film. Form on 5 Then, using the third resist pattern 10 as an etching mask, the first conductive film 5 is etched by, for example, RIE using a mixed gas of Cl 2 and O 2 as an etching gas.
これにより、キャパシタ誘電体膜 6 a下の第 1導電膜 5が下部電極 5 aとして残され、 該下部電極 5 a、 キャパシ夕誘電体膜 6 a、 及び上部 電極 7 aで構成されるキャパシ夕 Qが素子分離絶縁膜 2の上に形成さ れる。 更に、 pゥエル 3の上方では、 第 3レジストパターン 1 0の下に 第 1導電膜 5がゲート電極 5 bとして残される。  As a result, the first conductive film 5 under the capacitor dielectric film 6a is left as the lower electrode 5a, and the capacitor formed by the lower electrode 5a, the capacitor dielectric film 6a, and the upper electrode 7a. Q is formed on the element isolation insulating film 2. Further, above the p-well 3, the first conductive film 5 remains as the gate electrode 5 b under the third resist pattern 10.
次いで、 このゲート電極 5 bをエッチングマスクにしてシリコン酸化 膜 4を HF水溶液によりエッチングし、 シリコン酸化膜 4をゲート電極 5 bの下にゲート絶縁膜 4 aとして残す。  Next, using the gate electrode 5b as an etching mask, the silicon oxide film 4 is etched with an HF aqueous solution to leave the silicon oxide film 4 as a gate insulating film 4a under the gate electrode 5b.
この後に、 第 3 レジストパターン 1 0は除去される。  Thereafter, the third resist pattern 10 is removed.
続いて、 図 5 ( b ) に示すように、 不図示のレジストパターンの窓を通 じてシリコン基板 1にリンをィォン注入し、 ゲート電極 5 bの側方の pゥ エル 3に第 1、 第 2 n型不純物拡散領域 1 1 a、 l i bを形成する。 その W Subsequently, as shown in FIG. 5 (b), phosphorus is ion-implanted into the silicon substrate 1 through the window of the resist pattern (not shown), and the first and second p-wells 3 are formed on the sides of the gate electrode 5b. A second n-type impurity diffusion region 11a, lib is formed. That W
8 後、 イオン注入に使用したレジストパターンを除去する。  After that, the resist pattern used for ion implantation is removed.
次に、 図 6 ( a ) に示す断面構造を得るまでの工程について説明する。 まず、 N20等の酸化剤とシランガスとを反応ガスとして使用する C V D 法により、基板温度 8 0 0 °Cの条件下で、 Si02膜を全面に厚さ約 1 0 O nm 程度に形成する。 そして、 この Si02膜を異方的にエッチングし、 ゲート電 極 5 bと上部電極 7 aのそれぞれの側面にのみ Si02膜を残し、 残存する Si02膜を第 1、 第 2側壁絶縁膜 1 2、 1 3とする。 Next, steps required until a sectional structure shown in FIG. First, formed by a CVD method using an oxidizing agent and a silane gas such as N 2 0 as a reaction gas, under conditions of a substrate temperature of 8 0 0 ° C, to about Si0 2 film having a thickness of about 1 0 O nm on the entire surface I do. Then, the Si0 2 film is anisotropically etched, leaving the Si0 2 film only on each side of the gate electrodes 5 b and the upper electrode 7 a, remaining the Si0 2 film first, second sidewall insulating films 1 and 13, respectively.
更に、 この第 1側壁絶縁膜 1 2をマスクに使用して pゥエル 3にリンを 再びイオン注入することにより、 第 1、 第 2 n型不純物拡散領域 1 1 a、 1 1 bを LDD(Lightly Doped Drain)構造にする。  Further, the first and second n-type impurity diffusion regions 11 a and 11 b are LDD (lightly-lighted) by implanting phosphorus again into the p-well 3 using the first side wall insulating film 12 as a mask. Doped Drain) structure.
その後、 高融点金属膜としてコバルト膜をスパッタ法により約 9 nm の 厚さに全面に形成する。 そして、 N2雰囲気中、 基板温度 5 2 0度でそのコ バルト膜を約 3 0秒間ァニールすることにより、 pゥエル 3の上でコバル ト膜をシリコンと反応させ、 第 1、 第 2 n型不純物拡散領域 1 1 a、 1 1 bの表層部分に第 1、 第 2コバルトシリサイ ド層 1 4 a、 1 4 bを形成す る。 その後に、 未反応のコバルト膜をエッチングして除去する。 After that, a cobalt film is formed as a refractory metal film to a thickness of about 9 nm on the entire surface by sputtering. Then, in a N 2 atmosphere, the cobalt film is annealed at a substrate temperature of 520 ° C. for about 30 seconds, so that the cobalt film reacts with silicon on the p-well 3, and the first and second n-types are formed. First and second cobalt silicide layers 14a and 14b are formed in the surface layer of the impurity diffusion regions 11a and 11b. Thereafter, the unreacted cobalt film is removed by etching.
以上により、 ゲート電極 5 bと、 ソース · ドレイン領域として機能する 第 1、 第 2不純物拡散領域 1 1 a、 l i bとを有する MOS トランジス夕 TRが pゥエル 3の上に形成されたことになる。  As described above, the MOS transistor TR having the gate electrode 5b and the first and second impurity diffusion regions 11a and lib functioning as the source / drain regions is formed on the p-well 3.
次に、 図 6 ( b ) に示す断面構造を得るまでの工程について説明する。 まず、 シランガスと Ar ガスと 02ガスとを反応ガスとして使用する HDPCVD(Hig Density Plasma CVD)法により、 MOS トランジスタ TRとキ ャパシ夕 Qの上に Si02膜を厚さ約 8 0 O nmに形成し、 それを第 1埋め込 み絶縁膜 1 5とする。 Next, steps required until a sectional structure shown in FIG. First, the HDPCVD (Hig Density Plasma CVD) method using silane gas and Ar gas and 0 2 gas as the reaction gas, the MOS transistor TR and key Yapashi about 8 0 O nm evening thickness of Si0 2 film on the Q It is formed and used as a first buried insulating film 15.
この HDPCVD では、 高周波(HF: High Frequency)と低周波(LF: Low Frequency)の二種類の交流電力が用いられ、 HFの周波数は 13.56MHz、 ノ\° ヮ一は 2 1 0 0 Wであり、 LFの周波数は 400KHz、 パワーは 3 0 0 0 Wで ある。 また、 各ガスの流量は、 例えばシランガスが 8 0 sccm、 Ar ガスが 4 4 O sccm、 02力 S I 1 5 sccmに設定され、 成膜中の圧力は 1 0 mTorr、 基 板温度は 3 5 0 °Cに設定される。 このような HDPCVD法で成膜される第 1埋め込み絶縁膜 1 5は、 埋め 込み性が極めて良いため、 ポイ ドが発生すること無しに、 MOS トランジ スタ TRやキャパシ夕 Q等で挟まれる狭い部分を埋め込むことが可能であ り、 その表面形状は、 下地の形状を反映したものとなる。 In this HDPCVD, two types of AC power, high frequency (HF) and low frequency (LF), are used. The HF frequency is 13.56 MHz, and the noise power is 210 W. The frequency of the LF is 400 KHz and the power is 300 W. The flow rate of each gas, for example silane gas is 8 0 sccm, Ar gas is set to 4 4 O sccm, 0 2 force SI 1 5 sccm, the pressure during film formation is 1 0 mTorr, board temperature 3 5 Set to 0 ° C. The first buried insulating film 15 formed by such an HDPCVD method has an extremely good burying property, so that a narrow portion sandwiched between the MOS transistor TR, the capacitor Q, etc. can be formed without generating a void. Can be embedded, and its surface shape reflects the shape of the base.
次いで、 この第 1埋め込み絶縁膜 1 5の上に、 TEOS を反応ガスとして 使用するプラズマ C V D法により Si02膜を第 1犠牲絶縁膜 1 6として厚 さ約 8 0 O nm程度に形成する。 Then, on the first buried insulating film 1 5 is formed on the Si0 approximately 2 film thickness of about 8 0 O nm as the first sacrificial insulating film 1-6 by a plasma CVD method using TEOS as reactive gas.
その後に、 第 1犠牲絶縁膜 1 6を CMP(Chemical Mechanical Polishing)法 により研磨してその表面を平坦化すると共に、 第 1埋め込み絶縁膜 1 5と 第 1犠牲絶縁膜 1 6とで構成される第 1層間絶縁膜 1 7の厚さを約 1 0 0 O nm程度にする。  Thereafter, the first sacrificial insulating film 16 is polished by a CMP (Chemical Mechanical Polishing) method to flatten its surface, and is composed of the first buried insulating film 15 and the first sacrificial insulating film 16. The thickness of the first interlayer insulating film 17 is set to about 100 O nm.
次に、 図 7に示す断面構造を得るまでの工程について説明する。  Next, steps required until a sectional structure shown in FIG.
まず、 フォトリソグラフィとそれに続くエッチングにより、 第 1、 第 2 n型不純物拡散領域 1 l a、 l i bに至る深さの第 1、 第 2コンタクトホ —ル 1 7 a、 1 7 bを第 1層間絶縁膜 1 7に形成すると共に、 上部電極 7 aに至る深さの第 3コンタクトホール 1 7 cをキャパシ夕 Qの上に形成 する。  First, by photolithography and subsequent etching, the first and second contact holes 17a and 17b, which reach the first and second n-type impurity diffusion regions 1 la and lib, are first interlayer insulating. A third contact hole 17c having a depth reaching the upper electrode 7a is formed on the capacitor Q while being formed on the film 17.
次いで、 スパッタ法により、 各コンタクトホール 1 7 a〜 l 7 cの内面 と第 1層間絶縁膜 1 7の上面にグルー膜として ΉΝ膜を厚さ約 5 O nmに 形成する。 続いて、 六弗化タングステンガスを使用する C V D法によりグ ルー膜の上にタングステン膜を形成し、 各コンタクトホール 1 7 a〜 1 7 c内をそのタングステン膜で完全に埋め込む。 その後に、 第 1層間絶縁膜 1 7の上面上に形成された余分なグルー膜とタングステン膜とを CMP法 により除去し、 各コンタクトホール 1 7 a〜 l 7 c内に残されたダル一膜 とタングステン膜を第 1〜第 3導電性プラグ 1 8 a〜 1 8 cとする。  Next, a ΉΝ film is formed to a thickness of about 5 O nm as a glue film on the inner surfaces of the contact holes 17 a to 17 c and the upper surface of the first interlayer insulating film 17 by sputtering. Subsequently, a tungsten film is formed on the glue film by a CVD method using tungsten hexafluoride gas, and the contact holes 17a to 17c are completely filled with the tungsten film. After that, the excess glue film and the tungsten film formed on the upper surface of the first interlayer insulating film 17 are removed by the CMP method, and the dull film remaining in each of the contact holes 17a to 17c is removed. And the tungsten film are referred to as first to third conductive plugs 18a to 18c.
各導電性プラグ 1 8 a〜 1 8 cのうち、第 1、第 2導電性プラグ 1 8 a、 1 8 bは、 第 1、 第 2 n型不純物拡散領域 1 1 a、 l i bに電気的に接続 され、 第 3導電性プラグ 1 8 cは、 キャパシ夕 Qの上部電極 7 aと電気的 に接続される。  Of the conductive plugs 18a to 18c, the first and second conductive plugs 18a and 18b are electrically connected to the first and second n-type impurity diffusion regions 11a and lib. The third conductive plug 18 c is electrically connected to the upper electrode 7 a of the capacitor Q.
次に、 図 8に示す断面構造を得るまでの工程について説明する。 まず、 第 1層間絶縁膜 1 7上と第 1〜第 3導電性プラグ 1 8 a〜 l 8 c の上に、 スパッ夕法により金属積層膜を形成する。 その金属積層膜は、 例 えば、 厚さ 4 0 nmの Ti膜、 厚さ 3 0 nmの TiN膜、 厚さ 5 0 0 nmの Cu 含有 Al膜、 厚さ 5 nmの Ti膜、 及び厚さ 1 0 0 nmの TiN膜をこの順に積 層して形成される。 Next, steps required until a sectional structure shown in FIG. First, a metal laminated film is formed on the first interlayer insulating film 17 and the first to third conductive plugs 18a to 18c by a sputtering method. The metal laminated film includes, for example, a Ti film having a thickness of 40 nm, a TiN film having a thickness of 30 nm, an Al film containing Cu having a thickness of 500 nm, a Ti film having a thickness of 5 nm, and a thickness of 5 nm. It is formed by laminating 100 nm TiN films in this order.
その後、 この金属積層膜をパターニングして、 第 1、 第 2金属配線 1 9 a、 1 9 bを形成する。 このうち、 第 2金属配線 1 9 bは、 第 2、 第 3導 電性プラグ 1 8 b、 1 8 cの上に形成され、 キャパシタ Qの上部電極 7 a と第 2 n型不純物拡散領域 1 1 bとを電気的に接続するように機能する。 続いて、 各金属配線 1 9 a、 1 9 b間の狭いスペースを絶縁膜で埋め込 むために、 埋め込み性の良い HDPCVD法を用いて、 各金属配線 1 9 a、 1 9 b上と、 第 1層間絶縁膜 1 7上とに Si02膜を約 8 0 O nmの厚さに形 成し、 それを第 2埋め込み絶縁膜 2 0とする。 この第 2埋め込み絶縁膜 2 0の成膜条件は、 第 1埋め込み絶縁膜 1 5の成膜条件と同じである。 Thereafter, the metal laminated film is patterned to form first and second metal wirings 19a and 19b. Among them, the second metal wiring 19 b is formed on the second and third conductive plugs 18 b and 18 c, and the upper electrode 7 a of the capacitor Q and the second n-type impurity diffusion region 1 Functions to electrically connect 1b. Then, in order to fill the narrow space between the metal wirings 19a and 19b with an insulating film, using the HDPCVD method with good embedding property, the metal wirings 19a and 19b are formed on the metal wirings 19a and 19b. A SiO 2 film is formed on the interlayer insulating film 17 to a thickness of about 80 O nm, and is used as a second buried insulating film 20. The conditions for forming the second buried insulating film 20 are the same as those for forming the first buried insulating film 15.
次いで、 第 1犠牲絶縁膜 1 6を成膜したのと同様のプラズマ CVD法に より、第 2埋め込み絶縁膜 2 0の上に第 2犠牲絶縁膜 2 1として Si02膜を 厚さ約 1 3 0 O nmに形成する。 その後、 この第 2犠牲絶縁膜 2 1を CMP 法により研磨し、 各絶縁膜 2 0、 2 1で構成される第 2層間絶縁膜 2 2の 各金属配線 1 9 a、 1 9 b上での厚さを約 1 0 0 O nmとする。 Next, a SiO 2 film having a thickness of about 13 was formed as a second sacrificial insulating film 21 on the second buried insulating film 20 by the same plasma CVD method as used for forming the first sacrificial insulating film 16. Form at 0 O nm. Then, the second sacrificial insulating film 21 is polished by the CMP method, and the second interlayer insulating film 22 composed of the insulating films 20 and 21 is formed on the metal wirings 19 a and 19 b. The thickness is about 100 O nm.
次に、 図 9に示す断面構造を得るまでの工程について説明する。  Next, steps required until a sectional structure shown in FIG.
まず、 第 2層間絶縁膜 2 2の上にスパッ夕法により金属積層膜を形成し、 その金属積層膜をパターエングして遮光膜 2 3とする。 遮光膜 2 3を構成 する ·金属積層膜としては、 例えば、 アルミニウム膜が採用される。  First, a metal laminated film is formed on the second interlayer insulating film 22 by a sputtering method, and the metal laminated film is patterned to form a light shielding film 23. Constructing the light shielding film 23 · As the metal laminated film, for example, an aluminum film is adopted.
その後、 HDPCVD法を用いて、 この遮光膜 2 3上と第 2層間絶縁膜 2 2 上とに第 3埋め込み絶縁膜 2 4として Si02膜を厚さ約 8 0 O nm程度に形 成し、 その第 3埋め込み絶縁膜 2 4により、 隣接する遮光膜 2 3の間のス ペースを埋め込む。 この第 3埋め込み絶縁膜 2 4の成膜条件としては、 第 1埋め込み絶縁膜 1 7におけるのと同じ成膜条件が採用される。 Then, using a HDPCVD process, form the shading film 2 3 and on the third buried insulating film 2 4 as Si0 2 forms film to a thickness of about 8 0 O nm on the second interlayer insulating film 2 2 above, The space between the adjacent light shielding films 23 is buried by the third buried insulating film 24. As the film forming conditions for the third buried insulating film 24, the same film forming conditions as for the first buried insulating film 17 are employed.
次に、 第 1犠牲絶縁膜 1 6と同じ成膜条件のプラズマ CVD法により、 第 3埋め込み絶縁膜 2 4上に Si02膜を厚さ約 1 3 0 O nm程度に形成し、 それを第 3犠牲絶縁膜 2 5とする。 Next, by a plasma CVD method under the same film forming conditions as the first sacrificial insulating film 16, a SiO 2 film is formed on the third buried insulating film 24 to a thickness of about 130 nm, This is referred to as a third sacrificial insulating film 25.
そして、 各絶縁膜 2 4、 2 5で構成される第 3層間絶縁膜(第 1絶縁膜) 2 6を CMP法により研磨し、 遮光膜 2 3上での第 3層間絶縁膜 2 6の厚 さを約 9 5 O nm程度にする。  Then, the third interlayer insulating film (first insulating film) 26 composed of the insulating films 24 and 25 is polished by the CMP method, and the thickness of the third interlayer insulating film 26 on the light shielding film 23 is increased. To about 95 O nm.
次に、 図 1 0に示す断面構造を得るまでの工程について説明する。  Next, steps required until a sectional structure shown in FIG.
まず、 第 2金属配線 1 9 bに至る深さのホール 2 7を第 2、 第 3層間絶 縁膜 2 2 , 2 6に形成し、 そのホール 2 7の内面と第 3層間絶縁膜 2 6の 上面にグルー膜として TiN膜を約 5 O nmの厚さに形成する。 次いで、 ホ ール 2 7を完全に埋め込む厚さのタングステン膜をグルー膜の上に CVD 法により形成した後、 第 3層間絶縁膜 2 6の上面に形成された余分なダル 一膜とタングステン膜とを CMP法により研磨して除去し、 ホール 2 7内 に残ったグルー膜とタングステン膜とを第 4導電性プラグ 2 8とする。 こ の第 4導電性プラグ 2 8は、 第 2金属配線 1 9 bと電気的に接続されるこ とになる。  First, a hole 27 having a depth reaching the second metal wiring 19 b is formed in the second and third interlayer insulating films 22 and 26, and the inner surface of the hole 27 and the third interlayer insulating film 26 are formed. A TiN film with a thickness of about 5 O nm is formed on the upper surface as a glue film. Next, a tungsten film having a thickness completely burying the hole 27 is formed on the glue film by a CVD method, and then an excess dull film and a tungsten film formed on the upper surface of the third interlayer insulating film 26 are formed. Are removed by polishing by a CMP method, and the glue film and the tungsten film remaining in the hole 27 are used as a fourth conductive plug 28. The fourth conductive plug 28 is electrically connected to the second metal wiring 19b.
続いて、 プラズマ CVD法を用いて、 この第 4導電性プラグ 2 8上と第 3層間絶縁膜 2 6上とに Si02膜を厚さ約 3 0 O nm程度に形成し、 それを スぺーサ用絶縁膜 (第 2絶縁膜) 2 9とする。 Then, using the plasma CVD method, it is formed on the fourth conductive plug 2 8 and on the third interlayer insulating film 2 6 above and the Si0 2 film thickness of about 3 0 O nm, scan it page Insulating film for substrate (second insulating film) 29.
その後、 このスぺ一サ用絶縁膜 2 9上にフォトレジストを塗布し、 それ を露光、 現像することにより第 4レジストパターン 3 7とする。 この第 4 レジストパターン 3 7は、 隣接する画素の境界線上に沿って形成され、 そ の幅 Wは約 0 . 5 m程度である。  Thereafter, a photoresist is applied on the insulating film for spacer 29, and is exposed and developed to form a fourth resist pattern 37. The fourth resist pattern 37 is formed along the boundary between adjacent pixels, and has a width W of about 0.5 m.
次に、 図 1 1に示す断面構造を得るまでの工程について説明する。  Next, steps required until a sectional structure shown in FIG.
まず、 プラズマエッチングを行う不図示のチャンバ内シリコン基板 1を 入れ、 このチャンバ内に、 堆積性の CHF3ガスとエツチング性の CF4ガス とをエッチングガスとして供給する。 なお、 そのエッチングガスには、 02 も添加される。 エッチングガスの流量は、 堆積性のガスがエッチング性の ガスよりも多くなるように調整され、 例えば、 CHF3ガスの流量を CF4ガ スの流量の 1倍よりも多く且つ 2倍以下とする。 本実施形態では、 CHF3 ガスの流量を約 1 0 O sccmにし、 CF4ガスの流量を約 5 0 sccmにすると共 に、 基板温度を一 1 0〜 3 0 °Cにし、 チャンバ内圧力を約 1 0 0〜 9 0 0 Torrにする。 また、 02の流量は 5 0〜: ί 0 0 sccmにする。 First, a silicon substrate 1 in a chamber (not shown) for performing plasma etching is placed, and a deposition CHF 3 gas and an etching CF 4 gas are supplied as etching gases into the chamber. Note that the etching gas, 0 2 is also added. The flow rate of the etching gas is adjusted so that the deposition gas is higher than the etching gas.For example, the flow rate of the CHF 3 gas is more than 1 and less than twice the flow rate of the CF 4 gas. . In this embodiment, the flow rate of CHF 3 gas to about 1 0 O sccm, the co-when the flow rate of CF 4 gas is about 5 0 sccm, the substrate temperature was at a 1 0~ 3 0 ° C, the pressure in the chamber Approx. 100-900 Set to Torr. Further, 0 2 flow rate 5 0~: ί to 0 0 sccm.
そして、 このような状態を所定時間だけ保持することにより、 図 1 1に 示すように、 スぺーサ用絶縁膜 2 9が等方的にエッチングされる。 その結 果、 スぺーサ用絶縁膜 2 9は、 断面形状がテーパー状の絶縁性スぺーサ 2 9 aとして第 4レジストパターン 3 7の下に残される。 この後に、 第 4レ ジス卜パターン 3 7は除去される。  By maintaining such a state for a predetermined time, the spacer insulating film 29 is isotropically etched as shown in FIG. As a result, the spacer insulating film 29 is left under the fourth resist pattern 37 as an insulating spacer 29 a having a tapered cross section. Thereafter, the fourth register pattern 37 is removed.
なお、 この工程を終了後の拡大斜視図は図 1 5のようになり、 先の図 1 1は、図 1 5の I-I線に沿う断面図に相当する。図 1 5に示されるように、 絶縁性スぺーサ 2 9 aは、 画素毎に開口 2 9 bを有し、 その開口 2 9 b内 に第 4導電性プラグ 2 8の上面が露出する。  An enlarged perspective view after the completion of this step is as shown in FIG. 15, and FIG. 11 corresponds to a cross-sectional view taken along the line II of FIG. As shown in FIG. 15, the insulating spacer 29a has an opening 29b for each pixel, and the upper surface of the fourth conductive plug 28 is exposed in the opening 29b.
次いで、図 1 2に示すように、開口 2 9 b内の第 3層間絶縁膜 2 6上と、 絶縁性スぺーサ 2 9 a上とに第 3導電膜 3 0としてアルミニウム膜をス パッタ法により形成し、 スぺーサ 2 9の開口 2 9 bをその第 3導電膜 3 0 で埋め込む。  Next, as shown in FIG. 12, an aluminum film is formed as a third conductive film 30 on the third interlayer insulating film 26 in the opening 29 b and on the insulating spacer 29 a by a sputtering method. The opening 29 b of the spacer 29 is filled with the third conductive film 30.
上記のように、 第 3導電膜 3 0は、 アルミニウムのスパッ夕により形成 されるが、 スパッタ時の基板温度が高いと、 アルミニウムのグレインサイ ズが大きくな、り、 後で反射電極になる第 3導電膜 3 0の反射率が低下して しまう。  As described above, the third conductive film 30 is formed by aluminum sputter. However, if the substrate temperature during sputtering is high, the aluminum grain size increases, and the third conductive film 30 becomes a reflective electrode later. (3) The reflectance of the conductive film 30 is reduced.
そのため、 第 3導電膜 3 0の成膜時の基板温度は、 なるべく低く設定さ れるのが好ましく、 本実施形態では、 その基板温度を室温 (2 0 °C ) 〜 3 5 0 °C、 好ましくは 2 6 0 °Cとする。  Therefore, the substrate temperature during the formation of the third conductive film 30 is preferably set as low as possible. In the present embodiment, the substrate temperature is set at room temperature (20 ° C.) to 350 ° C., preferably. Is 260 ° C.
次に、 CABOT社製の商品名 SSW2000をスラリーとして使用し、 絶縁性 スぺーサ 2 9 aが露出する程度にこの第 3導電膜 3 0を CMP法により研 磨することにより、 図 1 3に示すように、 第 3導電膜 3 0を開口 2 9 b内 に反射電極 3 0 aとして残す。 この CMPでは、 第 3導電膜 3 0と絶縁性 スぺーサ 2 9 aの研磨速度が共に約 300nm/minと同じ値になるので、第 3 導電膜 3 0と絶縁性スぺーサ 2 9 aのどちらか一方が他方よりも過剰に 研磨に研磨されることはない。 また、 この CMP の研磨量は、 時間によつ て制御される。 Next, the third conductive film 30 was polished by the CMP method to the extent that the insulating spacer 29a was exposed, using SSW2000 (trade name, manufactured by CABOT) as a slurry. As shown, the third conductive film 30 is left as the reflective electrode 30a in the opening 29b. In this CMP, your polishing rate of the third conductive film 3 0 and the insulating spacer 2 9 a have the same value of about 300 n m / min Both the third conductive film 3 0 and the insulating spacer 2 Either one of 9a will not be polished excessively more than the other. The polishing amount of the CMP is controlled by time.
ここまでの工程により、 本実施形態に係る LCOS基板 (反射型液晶表示 装置用モジュール) 4 0の基本構造が完成する。 その LCOS基板 4 0の拡 大斜視図は、 図 1 6のようになり、 先の図 1 3は、 図 1 6の Π-ΙΙ線に沿う 断面図に相当する。 The LCOS substrate according to the present embodiment (reflective liquid crystal display) Module for device) 40 basic structure is completed. An enlarged perspective view of the LCOS substrate 40 is as shown in FIG. 16, and FIG. 13 corresponds to a cross-sectional view taken along a line II-III of FIG.
これ以降は、 上記とは別の工程で作製された液晶パネルをこの LCOS基 板 4 0に貼り付ける工程に移る。  Thereafter, the process proceeds to a step of attaching the liquid crystal panel manufactured in a different process from the above to the LCOS substrate 40.
図 1 4に示すように、 その液晶パネル 3 1は、 不図示のシール材によつ て LCOS基板 4 0に貼り付けられ、 下部液晶配向膜 3 2と上部液晶配向膜 3 4との間に配された液晶層 3 3を有する。 そして、 ITO(Indium Titan Oxide)等の透明導電性材料よりなるコモン電極 3 5が上部液晶配向膜 3 4 上に形成され、 このコモン電極 3 5上には、 外部の衝撃から液晶層 3 3等 を保護するための表面ガラスが設けられる。  As shown in FIG. 14, the liquid crystal panel 31 is adhered to the LCOS substrate 40 by a sealing material (not shown), and is provided between the lower liquid crystal alignment film 32 and the upper liquid crystal alignment film 34. It has a liquid crystal layer 33 arranged. Then, a common electrode 35 made of a transparent conductive material such as ITO (Indium Titan Oxide) is formed on the upper liquid crystal alignment film 34, and the liquid crystal layer 33 is formed on the common electrode 35 from external impact. Is provided with a surface glass for protecting the glass.
以上により、 本実施形態に係る反射型液晶表示装置の基本構造が完成す る。  As described above, the basic structure of the reflective liquid crystal display device according to the present embodiment is completed.
この反射型液晶表示装置は、 トランジスタ TRをオン状態にし、 第 1金 属配線 1 9 aの電圧を反射電極 3 0 aに印加することにより、 反射電極 3 0 a上の液晶層 3 3に画素毎に電圧が印加される。 そして、 表面ガラス 3 6から斜めに入射した入射光は、 反射電極 3 0 aの電圧値に応じて所定の 方向に偏光すると共に、 反射電極 3 0 aにより反射して再び外部に射出し、 図 2に示したような検光子 1 1 4を通すことにより、 ユーザに対して所定 の表示を行う。  In this reflective liquid crystal display device, the transistor TR is turned on, and the voltage of the first metal wiring 19a is applied to the reflective electrode 30a, so that a pixel is formed on the liquid crystal layer 33 on the reflective electrode 30a. A voltage is applied every time. Then, the incident light obliquely incident from the surface glass 36 is polarized in a predetermined direction according to the voltage value of the reflective electrode 30a, and is reflected by the reflective electrode 30a and emitted to the outside again. A predetermined display is provided to the user by passing through an analyzer 114 as shown in FIG.
また、 反射電極 3 0 aに印加された電圧は、 キャパシ夕 Qにも保持され るので、 トランジスタ TRをオフ状態にしても表示画面が変わらず、 その 表示状態を保持することができる。  Further, since the voltage applied to the reflective electrode 30a is also held in the capacitor Q, the display screen does not change even if the transistor TR is turned off, and the display state can be held.
上記したように、 本実施形態によれば、 図 1 2及び図 1 3に示したよう に、 絶縁性スぺーサ 2 9 a上と開口 2 9 b内とに第 3導電膜 3 0を形成し、 その第 3導電膜 3 0を CMP法により研磨して開口 2 8 b内に反射電極 3 0 aとして残すので、 反射電極 3 0 aの上面が平坦となり、 該上面が絶縁 性スぺーサ 2 9 aの上面と同じ高さになる。 その結果、 図 1 4に示したよ うに、 反射電極 3 0 aの上に液晶パネル 3 1を貼り付けても、 液晶パネル 3 1と絶縁性スぺ一サ 2 9 aとの間に空隙が形成されないので、 空隙によ る入射光の散乱が防止され、 色調が良好で、 且つコントラストが高められ た反射型液晶表示装置を提供することができる。 As described above, according to this embodiment, as shown in FIGS. 12 and 13, the third conductive film 30 is formed on the insulating spacer 29 a and in the opening 29 b. Then, the third conductive film 30 is polished by the CMP method and left as the reflective electrode 30a in the opening 28b, so that the upper surface of the reflective electrode 30a becomes flat, and the upper surface becomes an insulating spacer. It is the same height as the upper surface of 29a. As a result, as shown in FIG. 14, even when the liquid crystal panel 31 is attached on the reflective electrode 30a, a gap is formed between the liquid crystal panel 31 and the insulating spacer 29a. Because it is not Thus, it is possible to provide a reflection type liquid crystal display device in which scattering of incident light is prevented, color tone is good, and contrast is enhanced.
しかも、 図 1 3に示したように、 絶縁性スぺーサ 2 9 aの断面形状をテ —パー状にしたので、 絶縁性スぺ一サ 2 9 aの幅が細い上面によって、 隣 接する反射電極 3 0 a同士の間隔 dが極めて短くなる。 そのため、 各反射 電極 3 0 aが非常に高密度に配列されることになるので、 絶縁性スぺ一サ 2 9 aによって散乱される入射光が減り、 入射光の大部分が反射電極 3 0 aで反射されて、 LCOS基板 4 0全体の反射率が向上し、 コントラストが 向上する。  Moreover, as shown in FIG. 13, the cross-sectional shape of the insulating spacer 29a is tapered, so that the upper surface where the width of the insulating spacer 29a is narrow allows adjacent reflections. The distance d between the electrodes 30a is extremely short. Therefore, the reflection electrodes 30a are arranged at a very high density, so that the incident light scattered by the insulating spacer 29a is reduced, and most of the incident light is reflected by the reflection electrodes 30a. Reflected by a, the reflectance of the entire LCOS substrate 40 is improved, and the contrast is improved.
更に、 反射電極 3 0 aを構成するアルミニウム膜をスパッタ法で形成す る際、 基板温度を室温〜 3 5 0 °C程度の低温に保持するので、 アルミニゥ ム膜のグレインが大きく成長せず、 アルミニウム膜の表面の凹凸が小さく なり、 反射電極 3 0 a自身の反射率を向上させることができる。  Further, when the aluminum film forming the reflective electrode 30a is formed by sputtering, the substrate temperature is kept at a low temperature of about room temperature to about 350 ° C., so that the grains of the aluminum film do not grow significantly. Irregularities on the surface of the aluminum film are reduced, and the reflectance of the reflective electrode 30a itself can be improved.
(第 2実施形態)  (Second embodiment)
本実施形態が第 1実施形態と異なる点は、 テーパー状の絶縁性スぺーサ 2 9 aの形成方法であり、 これ以外は第 1実施形態と同じである。 図 1 7 〜図 1 9は、 本実施形態に係る反射型液晶表示装置用モジュールの製造方 法を工程順に示す断面図である。 これらの図において、 第 1実施形態で既 に説明した部材には、 第 1実施形態と同じ符号を付してある。  This embodiment is different from the first embodiment in a method of forming a tapered insulating spacer 29a, and is otherwise the same as the first embodiment. 17 to 19 are cross-sectional views illustrating a method of manufacturing the module for a reflective liquid crystal display device according to the present embodiment in the order of steps. In these drawings, members already described in the first embodiment are denoted by the same reference numerals as in the first embodiment.
まず、 第 1実施形態に従って図 1 0に示した構造を形成した後、 シリコ ン基板 1をホットプレート上に載せ、 N2の雰囲気中で基板温度が 1 2 0 °C 〜 1 3 0 ° (:、 になるようにシリコン基板 1を加熱する。 このようにシリコ ン基板 1を加熱すると、 図 1 7に示すように、 第 4レジストパターン 3 7 が熱によって溶融してその形が崩れる。 First, after forming the structure shown in FIG. 10 according to the first embodiment, the silicon substrate 1 is placed on a hot plate, and the substrate temperature is set to 120 ° C. to 130 ° C. in an atmosphere of N 2 ( : The silicon substrate 1 is heated so as to become: When the silicon substrate 1 is heated in this way, the fourth resist pattern 37 is melted by heat and its shape collapses, as shown in FIG.
次に、 図 1 8に示す断面構造を得るまでの工程について説明する。  Next, steps required until a sectional structure shown in FIG.
まず、 Si02よりなるスぺ一サ用絶縁膜 2 9と、 第 4レジストパターン 3 7とのエッチレートが 1 : 1になるような条件下で、 スぺーサ用絶縁膜 2 9と第 4レジストパターン 3 7とをエツチングする。 このようなエツチン グは、 CHF3ガスと CF4ガスとの混合ガスに、 該混合ガスよりも流量が多 い 02、 例えば約 5 0 0 sccmの流量の 02を添加したものをエッチングガス として使用するプラズマエッチングによって行うことができる。 First, Si0 a scan Bae one sub insulating film 2-9 composed of 2, the etch rate of the fourth resist pattern 3 7 1: under conditions such that 1, for spacer insulating film 2 9 and the fourth The resist pattern 37 is etched. Such Etsuchin grayed is, CHF 3 to a mixed gas of gas and CF 4 gas, the mixed flow rate is not multi than gas 0 2, for example about 5 0 0 sccm flow rate of 0 2 etching gas obtained by adding Can be performed by using plasma etching.
これにより、 テーパー状の第 4レジストパターン 3 7の断面形状がスぺ ーサ用絶縁膜 2 9に転写され、 断面がテーパー状の絶縁性スぺーサ 2 9 a が形成される。 その絶縁性スぺ一サ 2 9 aは、 第 1実施形態と同様に、 画 素毎に開口 2 9 bを有しており、 その開口 2 9 bから第 4導電性プラグ 2 8の上面が露出する。  As a result, the cross-sectional shape of the tapered fourth resist pattern 37 is transferred to the spacer insulating film 29, and an insulating spacer 29a having a tapered cross section is formed. As in the first embodiment, the insulating spacer 29a has an opening 29b for each pixel, and the upper surface of the fourth conductive plug 28 is formed from the opening 29b. Exposed.
その後に、 既述した図 1 2〜図 1 3の工程を行うことにより、 図 1 9に 示すように、 絶縁性スぺーサ 2 9 aの開口 2 9 bの中にアルミニウム膜よ りなる反射電極 3 0 aを形成する。  Thereafter, by performing the above-described steps of FIGS. 12 to 13, as shown in FIG. 19, the reflection made of the aluminum film in the opening 29 b of the insulating spacer 29 a is performed. An electrode 30a is formed.
上記した本実施形態によれば、 図 1 8に示したように、 絶縁性スぺーサ 2 9 aが形成されるのと同時に第 4レジストパターン 3 7がエッチング されて除去されるので、 第 1実施形態のように第 4レジストパターン 3 7 を改めて除去する工程が不要となり、 LCOS基板の製造工程の簡略化を図 ることができ、ひいては LCOS基板の製造コストを安くすることができる。 以上説明したように、 本発明によれば、 導電膜を研磨して反射電極にす るので、 反射電極と絶縁性スぺ一サのそれぞれの上面が同じ高さになる。 そのため、 反射電極の上に液晶パネルを貼り付けても、 液晶パネルと絶縁 性スぺーサとの間に空隙が形成されないので、 色調が良好で、 且つコント ラストの高い反射型液晶表示用モジュールを実現することができる。  According to the above-described embodiment, as shown in FIG. 18, the fourth resist pattern 37 is etched and removed at the same time as the formation of the insulating spacer 29a. The step of removing the fourth resist pattern 37 again as in the embodiment is not required, so that the manufacturing process of the LCOS substrate can be simplified, and the manufacturing cost of the LCOS substrate can be reduced. As described above, according to the present invention, since the conductive film is polished into the reflective electrode, the upper surfaces of the reflective electrode and the insulating spacer have the same height. Therefore, even if the liquid crystal panel is attached on the reflective electrode, no gap is formed between the liquid crystal panel and the insulating spacer, so that a reflective liquid crystal display module with good color tone and high contrast is provided. Can be realized.
しかも、 絶縁性スぺーザの断面形状をテーパー状にしたので、 反射電極 を高密度に配列することができ、 反射型液晶表示用モジュール全体の反射 率を高めることができる。  In addition, since the cross-sectional shape of the insulating spacer is tapered, the reflection electrodes can be arranged at a high density, and the reflectance of the entire reflection type liquid crystal display module can be increased.
また、 反射電極としてアルミニウム膜を使用し、 室温以上 3 5 0 °C以下 の低温の基板温度でそのアルミニウム膜をスパッタ法により形成するの で、 アルミニウム膜のグレインサイズが小さくなり、 反射電極の反射率を 高くすることができる。  In addition, since the aluminum film is used as a reflective electrode and the aluminum film is formed by a sputtering method at a low substrate temperature of room temperature or higher and 350 ° C or lower, the grain size of the aluminum film is reduced, and the reflection of the reflective electrode is reduced. Rates can be higher.

Claims

請 求 の 範 囲 The scope of the claims
1 . 半導体基板と、 1. a semiconductor substrate;
前記半導体基板の上方に形成された絶縁膜と、  An insulating film formed above the semiconductor substrate;
前記絶縁膜上に形成され、 画素毎に開口を有する絶縁性スぺーサと、 前記絶縁性スぺーサの開口内に形成され、 前記絶縁性スぺ一サの上面と 同じ高さの平坦な上面を有する反射電極と、  An insulating spacer formed on the insulating film and having an opening for each pixel; and a flat surface formed in the opening of the insulating spacer and having the same height as the upper surface of the insulating spacer. A reflective electrode having an upper surface,
を有することを特徴とする反射型液晶表示装置用モジュール。  A module for a reflection type liquid crystal display device, comprising:
2 . 前記絶縁性スぺーサの断面形状がテーパー状であることを特徴と する請求項 1に記載の反射型液晶表示装置用モジュール。 2. The reflective liquid crystal display module according to claim 1, wherein a cross-sectional shape of the insulating spacer is tapered.
3 . 前記絶縁性スぺーサはニ酸化シリコンよりなることを特徴とする 請.求項 1に記載の反射型液晶表示装置用モジュール。 3. The reflective liquid crystal display module according to claim 1, wherein the insulating spacer is made of silicon dioxide.
4 . 前記反射電極はアルミニウムよりなることを特徴とする請求項 1 に記載の反射型液晶表示装置用モジュール。 4. The reflective liquid crystal display module according to claim 1, wherein the reflective electrode is made of aluminum.
5 . 半導体基板の上方に第 1絶縁膜を形成する工程と、 5. forming a first insulating film above the semiconductor substrate;
前記第 1絶縁膜の上に第 2絶縁膜を形成する工程と、  Forming a second insulating film on the first insulating film;
前記第 2絶縁膜をバタ一ニングすることにより、 画素毎に開口を有する 絶縁性スぺ一サを形成する工程と、  A step of forming an insulating spacer having an opening for each pixel by patterning the second insulating film;
前記絶縁性スぺーサ上と前記開口内の前記第 1絶縁膜上とに導電膜を 形成する工程と、  Forming a conductive film on the insulating spacer and on the first insulating film in the opening;
前記絶縁性スぺーザが露出する程度に前記導電膜を研磨し、 前記開口内 に残った前記導電膜を反射電極とする工程と、  Polishing the conductive film to the extent that the insulating spacer is exposed, and using the conductive film remaining in the opening as a reflective electrode;
を有することを特徴とする反射型液晶表示装置用モジュールの製造方 法。 ' A method for manufacturing a module for a reflection type liquid crystal display device, comprising: '
6 . 前記絶縁性スぺーサの断面形状をテーパー状にすることを特徴とす る請求項 5に記載の反射型液晶表示装置用モジュールの製造方法。 6. The cross-sectional shape of the insulating spacer is tapered. A method for manufacturing a module for a reflective liquid crystal display device according to claim 5.
7 . 前記絶縁性スぺーサを形成する工程は、 7. The step of forming the insulating spacer includes:
前記第 2絶縁膜の上にレジストパターンを形成する工程と、  Forming a resist pattern on the second insulating film;
エッチング性ガスと、 該エッチング性ガスよりも流量が大きい堆積性ガ スとの混合ガスをエッチングガスとして使用して、 前記レジストパ夕一ン をマスクにしながら前記第 2絶縁膜をエッチングする工程と、  Using a mixed gas of an etching gas and a deposition gas having a larger flow rate than the etching gas as an etching gas, etching the second insulating film while using the resist pattern as a mask;
により行われることを特徴とする請求項 6に記載の反射型液晶表示装 置用モジュールの製造方法。  7. The method for producing a reflective liquid crystal display device module according to claim 6, wherein the method is performed by the following.
8 . 前記エッチングガスとして CF4ガスを使用し、 前記堆積性ガスとし て CHF3ガスを使用することを特徴とする請求項 7に記載の反射型液晶表 示装置用モジュールの製造方法。 8. The use of CF 4 gas as an etching gas, the manufacturing method of the reflection-type liquid crystal Display device module according to claim 7, wherein the use of CHF 3 gas to said deposition gas.
9 . 前記 CHF3ガスの流量を、 前記 CF4ガスの流量の 1倍よりも多く且 つ 2倍以下にすることを特徴とする請求項 8に記載の反射型液晶表示装 置用モジュールの製造方法。 9. The reflective liquid crystal display module according to claim 8, wherein the flow rate of the CHF 3 gas is set to be more than 1 and not more than twice the flow rate of the CF 4 gas. Method.
1 0 . 前記絶縁性スぺ一サを形成する工程は、 10. The step of forming the insulating spacer comprises:
前記第 2絶縁膜の上にレジストパターンを形成する工程と、  Forming a resist pattern on the second insulating film;
前記レジストパターンを加熱して溶融することにより、 該レジストパタ —ンの断面形状を崩す工程と、  Heating and melting the resist pattern to break the cross-sectional shape of the resist pattern;
前記レジストパターンを加熱した後、 該レジストパターンと前記第 2絶 縁膜とを同時にエッチングする工程と、  After heating the resist pattern, simultaneously etching the resist pattern and the second insulating film;
により行われることを特徴とする請求項 6に記載の反射型液晶表示装 ' 置用モジュールの製造方法。  7. The method for producing a reflective liquid crystal display device module according to claim 6, wherein the method is performed by:
1 1 . 前記レジストパターンの加熱は、 1 2 0 °C以上 1 3 0 °C以下の基 板温度で行われることを特徴とする請求項 1 0に記載の反射型液晶表示 装置用モジュールの製造方法。 11. The manufacturing method of the reflective liquid crystal display module according to claim 10, wherein the resist pattern is heated at a substrate temperature of 120 ° C. or more and 130 ° C. or less. Method.
1 2 . 前記レジストパターンと前記第 2絶縁膜とを同時にエッチングす る工程は、 CHF3ガスと CF4ガスとの混合ガスに、 該混合ガスよりも流量 が多い 02を添加してなるガスをエッチングガスとして使用するプラズマ エッチングにより行われることを特徴とする請求項 1 0に記載の反射型 液晶表示装置用モジュールの製造方法.。 1 2. The resist pattern and the second insulating film are simultaneously etched to that process, CHF 3 to a mixed gas of gas and CF 4 gas, a gas obtained by adding 0 2 flow rate is greater than the mixed gas 11. The method for manufacturing a reflective liquid crystal display module according to claim 10, wherein the etching is performed by plasma etching using a gas as an etching gas.
1 3 . 前記第 2絶縁膜として二酸化シリコン膜を形成することを特徴と する請求項 5に記載の反射型液晶表示装置用モジュールの製造方法。 13. The method for manufacturing a reflective liquid crystal display module according to claim 5, wherein a silicon dioxide film is formed as the second insulating film.
1 4 . 前記導電膜としてアルミニウム膜を形成することを特徴とする請 求項 5に記載の反射型液晶表示装置用モジュールの製造方法。 14. The method for manufacturing a reflective liquid crystal display module according to claim 5, wherein an aluminum film is formed as the conductive film.
1 5 . 前記アルミニウム膜は、 基板温度が室温以上 3 5 0 °C以下のスパ ッ夕法により形成されることを特徴とする請求項 1 4に記載の反射型液 晶表示装置用モジュールの製造方法。 15. The manufacturing method for a reflective liquid crystal display module according to claim 14, wherein the aluminum film is formed by a sputtering method at a substrate temperature of room temperature or higher and 350 ° C. or lower. Method.
1 6 . 半導体基板と、 1 6. The semiconductor substrate,
前記半導体基板の上方に形成された絶縁膜と、  An insulating film formed above the semiconductor substrate;
前記絶縁膜上に形成され、 画素毎に開口を有する絶縁性スぺ一サと、 前記絶縁性スぺ一サの開口内に形成され、 前記絶縁性スぺーサの上面と 同じ高さの平坦な上面を有する複数の反射電極と、  An insulating spacer formed on the insulating film and having an opening for each pixel; and a flat formed in the opening of the insulating spacer and having the same height as the upper surface of the insulating spacer. A plurality of reflective electrodes having a top surface,
前記複数の反射電極に対向して設けられたコモン電極と、  A common electrode provided to face the plurality of reflective electrodes,
前記反射電極と前記コモン電極との間に封入された液晶と、  Liquid crystal sealed between the reflective electrode and the common electrode,
を有することを特徴とする反射型液晶表示装置。  A reflective liquid crystal display device comprising:
1 7 . 前記絶縁性スぺ一ザの断面形状はテーパー状であることを特徴と する請求項 1 6に記載の反射型液晶表示装置。 17. The reflective liquid crystal display device according to claim 16, wherein a cross-sectional shape of the insulating spacer is tapered.
PCT/JP2003/012943 2003-10-09 2003-10-09 Module for reflection liquid crystal display and its manufacturing method, and reflection liquid crystal display WO2005036244A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2003/012943 WO2005036244A1 (en) 2003-10-09 2003-10-09 Module for reflection liquid crystal display and its manufacturing method, and reflection liquid crystal display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2003/012943 WO2005036244A1 (en) 2003-10-09 2003-10-09 Module for reflection liquid crystal display and its manufacturing method, and reflection liquid crystal display

Publications (1)

Publication Number Publication Date
WO2005036244A1 true WO2005036244A1 (en) 2005-04-21

Family

ID=34430847

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2003/012943 WO2005036244A1 (en) 2003-10-09 2003-10-09 Module for reflection liquid crystal display and its manufacturing method, and reflection liquid crystal display

Country Status (1)

Country Link
WO (1) WO2005036244A1 (en)

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05102106A (en) * 1991-10-03 1993-04-23 Oki Electric Ind Co Ltd Manufacture of semiconductor device
JPH05283358A (en) * 1992-02-07 1993-10-29 Sumitomo Metal Ind Ltd Method of forming contact hole in semiconductor device
JPH05326357A (en) * 1992-05-22 1993-12-10 Nippon Telegr & Teleph Corp <Ntt> Method for forming contact hole
JPH06163482A (en) * 1992-11-20 1994-06-10 Sumitomo Metal Ind Ltd Contact hole forming method of semiconductor device
JPH06275577A (en) * 1993-03-23 1994-09-30 Sumitomo Metal Ind Ltd Formation of contact hole of semiconductor device
JPH0766280A (en) * 1993-08-30 1995-03-10 Toshiba Corp Manufacture of semiconductor device
JPH0766185A (en) * 1993-08-27 1995-03-10 Nippondenso Co Ltd Fabrication of semiconductor device
JPH07335625A (en) * 1994-06-10 1995-12-22 Sony Corp Plasma etching method
JPH08199377A (en) * 1995-01-24 1996-08-06 Sony Corp Plasma etching apparatus and plasma etching
EP0911682A2 (en) * 1997-10-24 1999-04-28 Canon Kabushiki Kaisha Matrix substrate and liquid crystal display device using the same

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05102106A (en) * 1991-10-03 1993-04-23 Oki Electric Ind Co Ltd Manufacture of semiconductor device
JPH05283358A (en) * 1992-02-07 1993-10-29 Sumitomo Metal Ind Ltd Method of forming contact hole in semiconductor device
JPH05326357A (en) * 1992-05-22 1993-12-10 Nippon Telegr & Teleph Corp <Ntt> Method for forming contact hole
JPH06163482A (en) * 1992-11-20 1994-06-10 Sumitomo Metal Ind Ltd Contact hole forming method of semiconductor device
JPH06275577A (en) * 1993-03-23 1994-09-30 Sumitomo Metal Ind Ltd Formation of contact hole of semiconductor device
JPH0766185A (en) * 1993-08-27 1995-03-10 Nippondenso Co Ltd Fabrication of semiconductor device
JPH0766280A (en) * 1993-08-30 1995-03-10 Toshiba Corp Manufacture of semiconductor device
JPH07335625A (en) * 1994-06-10 1995-12-22 Sony Corp Plasma etching method
JPH08199377A (en) * 1995-01-24 1996-08-06 Sony Corp Plasma etching apparatus and plasma etching
EP0911682A2 (en) * 1997-10-24 1999-04-28 Canon Kabushiki Kaisha Matrix substrate and liquid crystal display device using the same

Similar Documents

Publication Publication Date Title
US5677231A (en) Method for providing trench isolation
TWI442565B (en) Semiconductor device and method for manufacturing the same
JPH0973103A (en) Display device and its production
JP4643786B2 (en) REFLECTIVE LIQUID CRYSTAL DISPLAY DEVICE MODULE, ITS MANUFACTURING METHOD, AND REFLECTIVE LIQUID CRYSTAL DISPLAY DEVICE
KR101045089B1 (en) Semiconductor device and method of fabricating the same
JP2002359297A (en) Method for forming contact plug of semiconductor element
KR100366619B1 (en) Trench isolation method, Method of manufacturing semiconductor device having trench and Semiconductor device formed thereby
US20070111469A1 (en) Method for fabricating semiconductor device with bulb-shaped recess gate
JP2003289072A (en) Substrate with flattened film and substrate for display device, and method for manufacturing the same
JP2000307001A (en) Manufacture of semiconductor device
JPH11312679A (en) Manufacture of wide and flattened semiconductor device
JP2003224263A (en) Method of forming transistor
TWI320215B (en) Method of forming shallow trench isolation(sti) with chamfered corner
JP2002217128A (en) Method for manufacturing semiconductor device
KR100616499B1 (en) Method for fabrication of semiconductor device
WO2005036244A1 (en) Module for reflection liquid crystal display and its manufacturing method, and reflection liquid crystal display
JPH0945687A (en) Flattening method for surface of substrate
US6903022B2 (en) Method of forming contact hole
US20050224794A1 (en) Semiconductor device manufacturing method
JP3097338B2 (en) Method of forming contact hole
JP2001118919A (en) Semiconductor device and manufacturing method therefor
KR19990074800A (en) Semiconductor element and manufacturing method thereof
JP2001284204A (en) Semiconductor device and its manufacturing method
KR100516228B1 (en) Method For Manufacturing Semiconductor Device
JP3070564B2 (en) Method for manufacturing semiconductor device

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP US

NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP