JP2001284204A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device provided with an alignment mark, which can prevent erroneous detection at the time of aligning a mask with the mark. SOLUTION: The alignment mark 15 is formed by filling a groove 12 formed on an interlayer insulating film 11 composed of a BPSG film, etc., and formed on a silicon substrate 10 with a metallic layer 13 composed of a material, such as W, etc., which becomes the material of a via plug and a silicon oxide film 14 formed by using a different material from that of the via plug, for example, TEOS.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a structure of an alignment mark used in a lithography process and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, miniaturization and high density of semiconductor devices have been remarkable. As the miniaturization and the density increase, there is a demand for increasing the resolution of the lithography process. Therefore, the planarization technology of the semiconductor device has become important.

As a technique for flattening, a chemical mechanical polishing (CMP) method is generally known. In the CMP method, a BPSG (Boron Phosphorous Silicate) having a high step coverage can be added to a conventional material for an interlayer insulating film even when the interlayer insulating film is flattened.
The flatness is remarkably superior to a flattening technique by a reflow method using Glass). Further, it has many advantages such as being able to be used not only at the chip level but also for flattening a large area at the wafer level.

On the other hand, in a lithography process, an alignment mark for aligning with a mask is required. This alignment mark is usually formed by providing a wide groove in the semiconductor device.

As described above, when a semiconductor device having a wide groove is polished and flattened by the CMP method, an abrasive (slurry) used for polishing by the CMP method is provided in the groove.
Will remain. For this reason, in the lithography process, a problem occurs when the alignment is performed by recognizing the linear portion with the contrast of the edge of the step of the groove or the like.

As described above, the case where the abrasive remains in the groove serving as the alignment mark is shown in FIG.
This will be described with reference to FIG. FIG. 21A is a plan view of an alignment mark of a semiconductor device after polishing by a CMP method,
FIG. 21B is a cross-sectional view taken along line AA ′ in FIG. Here, taking the example of forming a via plug (Via Plug) as an example, a state of an alignment mark when a metal layer is formed on an interlayer insulating film, a via hole is buried, and the metal layer is flattened. Is shown.

As shown in the figure, an interlayer insulating film 110 is provided on a semiconductor substrate 100, for example.
A groove 120 serving as an alignment mark is provided by removing a part of 0. In a region (not shown), a via hole for making contact with a semiconductor element or a metal wiring layer is formed, and a via plug is formed by embedding a metal layer in the via hole. Usually, simultaneously with the formation of this via hole, the groove 1 of the alignment mark is formed.
20 is formed. Then, a metal layer for filling the via hole is formed on the entire surface, and is polished and flattened by a CMP method so that the metal layer remains in the via hole. Therefore, a part of the metal layer 130 filling the via hole (not shown) remains in the groove 120 of the alignment mark. However, since the size of the groove 120 is relatively large,
The entire groove 120 is not covered with the metal layer 130. After the completion of the polishing by the CMP method, the abrasive 190 remains at the corners in the groove 120. Therefore, FIG.
As shown in the plan view of (a), the edge of the step of the groove does not become a straight line, but becomes uneven.

After the formation of the via plug, a metal wiring layer connected to the via plug is formed. In this case, a metal layer is first formed on the entire surface, and the metal layer is patterned by lithography and etching to form a metal wiring layer having a desired pattern.

However, as described above, the polishing material of CMP remains in the groove of the alignment mark, and the edge of the step of the groove is not straight, and has irregularities. When the alignment with the mask to be used is performed, the alignment mark may not be normally recognized. For this reason, there is a problem that alignment cannot be performed, or even if alignment is performed, misalignment increases.

[0010]

The alignment marks for lithography provided on the above-mentioned conventional semiconductor device are as follows.
It is formed by a groove provided on the base of the material to be etched. However, when the CMP step is performed after forming the groove, there is a problem that the abrasive used in the CMP step remains in the groove. The residual abrasive in the groove causes an erroneous detection of the alignment, for example, the edge of the step of the originally linear groove becomes uneven. For this reason, there has been a problem that alignment cannot be performed, or the amount of misalignment increases even if alignment is performed, and the alignment mark does not function.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor device having an alignment mark capable of preventing erroneous detection when aligning with a mask, and a method of manufacturing the same. is there.

[0012]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: an interlayer insulating film provided on a semiconductor substrate on which a semiconductor element is formed; A via plug electrically connected to the element, and a wiring formed on the interlayer insulating film and electrically connected to the via plug, wherein the wiring comprises a metal layer formed on the interlayer insulating film. In a semiconductor device formed by patterning, a groove formed in the interlayer insulating film and formed on a bottom surface and a side surface in the groove as an alignment mark of a mask for forming a wiring by patterning the metal layer. A conductive film for forming the via plug; and a key formed on the conductive film in the groove so as to fill the groove, and made of a material different from the conductive film. Tsu is characterized in that a and-flops layer.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a via hole and a groove for an alignment mark in an interlayer insulating film on a semiconductor substrate; and forming a conductive film on the interlayer insulating film. A step of filling the via hole and a part of the groove, a step of forming a cap layer on the conductive film using a material different from the conductive film and filling the groove, and using the interlayer insulating film as a stopper,
A step of polishing and flattening the cap layer and the conductive film while protecting the trench with the cap layer; and a step of forming a metal wiring layer on the interlayer insulating film and the conductive film. It is characterized by.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the second aspect, after the step of forming a metal wiring layer on the interlayer insulating film and the conductive film,
The groove, the conductive film filling a part of the groove,
The method further includes a step of patterning the metal wiring layer into a desired pattern by a lithography technique and etching using an alignment mark formed from a cap layer provided on the conductive film and filling the groove.

Further, as described in claim 4, in the method of manufacturing a semiconductor device according to claim 2, the cap layer and the conductive film are polished and flattened while protecting the groove with the cap layer. After the step of removing, the method further comprises a step of removing the cap layer in the groove.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourth aspect, after the step of forming a metal wiring layer on the interlayer insulating film and the conductive film, the trench and the trench are formed. The method further includes a step of patterning the metal wiring layer into a desired pattern by a lithography technique and etching using an alignment mark formed from the conductive film that partially fills the inside.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the second to fifth aspects,
The step of polishing and flattening the cap layer and the conductive film while protecting the groove with the cap layer is a step of polishing the cap layer using the conductive film as a stopper, and a step of polishing the interlayer insulating film. Polishing the conductive film using a stopper.

According to the structure and the method as described in the first to third aspects, the inside of the groove serving as the alignment mark is filled with the cap layer. Therefore, when the conductive film is polished by a CMP method or the like to form a via plug, it is possible to prevent the abrasive used for the polishing from remaining in the groove. Further, by using different types of film for the conductive film and the cap layer, the alignment mark can be easily recognized.
Therefore, when aligning the alignment mark with the mask in the lithography process, erroneous detection of alignment can be prevented.

By providing a step of removing the cap layer after the planarization step by polishing, the reliability of alignment at the time of lithography can be further improved.

In the step of polishing the cap layer and the conductive film, the two layers may be polished in separate steps. Even in this case, since the inside of the groove of the alignment mark is buried with the cap layer, the abrasive does not remain.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. For this explanation,
Common parts are denoted by common reference symbols.

A semiconductor device according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view of a semiconductor device, showing a state of a peripheral region where an alignment mark used for alignment with a mask is formed in a lithography process.

As shown in the figure, an interlayer insulating film 11 such as a BPSG (Boron Phosphorous Silicon Grass) film is formed on a silicon substrate 10.
1 is provided with a groove 12. Then, for example, W (Tungste) serving as a material of a via plug is formed in the groove 12.
n) A metal layer 13 is formed by a film or the like, and further different from the material of the via plug, for example, TEOS (tetraethylorthosilil).
An alignment mark 15 is formed by embedding the groove 12 as a cap layer with a silicon oxide film 14 formed using icate; Si (OC ₂ H ₅ ) ₄ ).

2 (a), 2 (b) to 7 (a),
3B is a sectional view sequentially showing a manufacturing process of the semiconductor device having the above structure. FIG. 4A is a circuit region where a semiconductor element is formed, and FIG. 5B is a peripheral region where an alignment mark is formed. Is shown.

First, as shown in FIGS. 2A and 2B, a metal wiring layer 16 is formed in a circuit region on a silicon substrate 10, and a BPSG film serving as an interlayer insulating film 11 is formed on the entire surface.
It is formed by a VD (Chemical Vapor Deposition) method or the like. In the element region, a via hole 17 for making contact with the metal wiring layer 16 is formed by lithography technology and R
It is formed by anisotropic etching such as IE (Reactive Ion Etching). At the same time, a groove 12 for forming an alignment mark is also formed. In addition, since the size of the opening of the alignment mark groove 12 is usually much larger than that of the via hole 17, the etching speed of the alignment mark groove 12 is higher. for that reason,
Although not shown in FIG. 2B, a depth of the groove 12 may be controlled by forming a layer serving as an etching stopper in advance on the silicon substrate 10 in the peripheral region. The method of forming the groove for the alignment mark is the same as the conventional method.

Next, as shown in FIGS. 3A and 3B,
As a via material for filling the via hole 17, a metal layer 13 such as a W film is formed on the entire surface by a CVD method or the like. The metal layer 13 completely fills the via hole 17, but does not completely fill the groove 12 of the alignment mark portion because it is wide.

Subsequently, as shown in FIGS. 4A and 4B, a silicon oxide film 14 is formed on the entire surface by a CVD method using TEOS as a cap layer for the groove portion 12 of the alignment mark portion. Groove 12
Embed completely. The material for filling the groove 12 may be a material different from that of the metal layer 13 and is not limited to the silicon oxide film.

Next, C using the metal layer 13 as a stopper
The structure shown in FIGS. 5A and 5B is obtained by polishing the silicon oxide film 14 by the MP method.

Further, as shown in FIGS. 6A and 6B,
By polishing the metal layer 13 and the silicon oxide film 14 by the CMP method using the interlayer insulating film 11 as a stopper,
The via plug and the alignment mark 15 are completed.

Then, as shown in FIGS. 7A and 7B, a metal layer 18 having a three-layer structure of a Ti film, a TiN film, and an Al film is formed by sputtering.

Thereafter, the metal layer 13 is patterned into a desired pattern by lithography and etching to complete a metal wiring layer. At the time of this lithography step, alignment between the lithography mask and the semiconductor device is performed using the alignment mark 15. The alignment is performed by an optical method or by contrast depending on the type of film. In the alignment mark 15 formed according to the present embodiment, the metal layer 13 is formed in the groove 12 and further embedded with a transparent silicon oxide film.
Therefore, alignment can be achieved by either of the above two methods. Further, since the trench 12 is filled with the silicon oxide film, it is possible to prevent the abrasive from remaining in the trench 12 during the CMP process shown in FIGS. Therefore, a desired alignment mark as designed can be formed, and the alignment mark can be formed into a shape that facilitates recognition. Therefore, misdetection of alignment can be prevented, and the amount of misalignment can be reduced.

In the process of FIG. 6, the metal layer 13 is
After polishing, for example, by wet etching,
The silicon oxide film 14 as the cap layer may be removed. This silicon oxide film 14 is for preventing the abrasive from remaining in the groove 12 in the CMP, and is not essential as an alignment mark. That is, it is necessary to remove the silicon oxide film 14 when performing alignment not by an optical method or by a difference in film type but by a step. However, in this case, it is necessary to use a material different from the interlayer insulating film 11, for example, a silicon nitride film, as the material functioning as the cap layer.

Next, a semiconductor device and a method for manufacturing the same according to a second embodiment of the present invention will be described with reference to FIGS.
A description will be given with reference to FIGS. This embodiment is an example in which the alignment mark described in the first embodiment is applied to a specific method for manufacturing a semiconductor device. 8 (a), 8 (b) to 20 (a), and (b) are cross-sectional views sequentially showing a manufacturing process of a semiconductor device. FIGS. 8 (a) to 20 (a) show a semiconductor element. FIGS. 8B to 20B show a circuit region to be formed, and a peripheral region in which an alignment mark is formed.

First, as shown in FIGS. 8A and 8B,
A semiconductor element is formed on the silicon substrate 20. Here, a MOS transistor is taken as an example. As shown, an element isolation region 21 is formed on a silicon substrate 20 in a circuit region by STI (Shallow Trench Isolation) technology or the like. Then, the gate insulating film 22 is formed on the silicon substrate 20.
A gate electrode 23 is formed through the gate electrode 23.
Is used as a mask to introduce impurities into the silicon substrate 20 so that the impurity diffusion layers 24 serving as source and drain regions can be formed.
Is formed to complete a MOS transistor.

Next, as shown in FIGS. 9A and 9B,
The first interlayer insulating film 25 is entirely formed of BPSG film by CVD.
It is formed by a method or the like. Then, the first interlayer insulating film 25 is reflowed by heat treatment, and further polished by a CMP method, so that the first interlayer insulating film 25 is flattened.

As shown in FIGS. 10A and 10B, a via hole 26 for making contact with the impurity diffusion layer 24 of the MOS transistor is formed in the circuit region, and an alignment mark is formed in the peripheral region. Groove 27
Is formed by lithography and anisotropic etching. Although not shown in FIG. 10B, as described in the first embodiment, a layer serving as an etching stopper for forming the groove 27 is formed in advance on the silicon substrate 20 in the peripheral region. The groove 27 may be formed by etching until the silicon substrate 20 is exposed without providing a stopper. The peripheral region where the alignment mark is formed has no influence on the semiconductor element formed in the circuit region.

Further, as shown in FIGS. 11A and 11B, in order to form a via plug, a metal layer 28 such as a W film is
It is formed on the entire surface by a VD method or the like. Although the metal layer 28 completely fills the via hole 26, the groove 27 in the peripheral region is not completely filled because it is wide. Note that a low-resistance semiconductor film such as a polycrystalline silicon film may be formed instead of the metal layer 28.

Subsequently, as shown in FIGS. 12A and 12B, the layer functions as a cap layer for the alignment mark.
A silicon oxide film 29 is formed on the entire surface by a CVD method using TEOS, and the trench 27 is completely buried. The material for filling the groove 27 may be a material different from that of the metal layer 28, and is not limited to the silicon oxide film.

Then, the silicon oxide film 29 and the metal layer 28 are polished by the CMP method to obtain the structures shown in FIGS. In the CMP, first, the silicon oxide film 29 is polished using the metal layer 28 as a stopper, and then the first
The metal layer 28 may be polished using the interlayer insulating film 25 as a stopper. In addition, the silicon oxide film 29 and the metal layer 28 may be continuously polished using the first interlayer insulating film 25 as a stopper.

The above process completes the alignment mark 30.

Thereafter, as in the first embodiment, the silicon oxide film 29 filling the groove 27 of the alignment mark 30 may be removed. Also in this case, it is necessary to use a material different from the first interlayer insulating film 25, for example, a silicon nitride film, as a material functioning as a cap layer of the alignment mark.

Next, as shown in FIGS. 14A and 14B, a metal layer 31 having a three-layer structure of a Ti film, a TiN film and an Al film is formed on the entire surface by sputtering.

Then, the metal layer 31 is patterned into a desired pattern by lithography and etching to complete a metal wiring layer as shown in FIGS. 15 (a) and 15 (b). At the time of this lithography step, the alignment mark 30 is used to align the lithography mask with the semiconductor device.

Subsequently, as shown in FIGS. 16A and 16B, a second interlayer insulating film 32 is formed on the entire surface.

As shown in FIGS. 17A and 17B, a via hole 33 for making contact with the metal wiring layer 31 is formed in the circuit region, and a groove portion 34 for forming an alignment mark is formed in the peripheral region. , By lithography and anisotropic etching. Of course, also in this step, a layer serving as an etching stopper when forming the groove 34 may be formed in advance on the first interlayer insulating film 25 in the peripheral region.

Next, as shown in FIGS. 18A and 18B, a metal layer 35 such as a W film is formed to form a via plug.
Is formed on the entire surface by a CVD method or the like. This metal layer 35
Completely fills the via hole 33, but does not completely fill the groove 34 in the peripheral region because the width is wide.

Subsequently, the silicon oxide film 36 as a cap layer for the alignment mark is
The groove 34 is completely buried by the VD method. The material for filling the groove 34 may be a material different from the metal layer 35, and is not limited to the silicon oxide film. Then, the metal layer 35 and the silicon oxide film 36
Using CMP using the second interlayer insulating film 32 as a stopper.
Via plug and alignment mark 37
Is formed to obtain the structure shown in FIGS. In the CMP, the silicon oxide film 36 is first polished using the metal layer 35 as a stopper, and then the second interlayer insulating film 3 is polished.
The polishing may be performed by two steps of polishing the metal layer 35 by using 2 as a stopper. Further, the silicon oxide film 36 and the metal layer 3 are formed using the second interlayer insulating film 32 as a stopper.
5 may be continuously polished.

The alignment mark 37 is completed by the above steps.

After that, similarly to the alignment mark 30, the silicon oxide film 36 filling the groove 34 of the alignment mark 37 may be removed. Also in this case, it is necessary to use a material different from that of the second interlayer insulating film 32 as a material for the cap layer of the alignment mark.

Next, a Ti film, a TiN film, and an Al
A three-layer metal layer 38 of a film is formed by sputtering. Then, using the alignment mark 37, the metal layer 38 is patterned into a desired pattern by lithography and etching.
A metal wiring layer as shown in (a) and (b) is completed.

Thereafter, a coating material having an opening in a bonding pad region (not shown) is formed by a well-known technique to complete a semiconductor device.

According to the first and second embodiments, the groove serving as the alignment mark is filled with the metal layer and the cap layer for filling the via hole. Therefore, when the metal layer is polished by the CMP method or the like to form a via plug, it is possible to prevent the abrasive used for the polishing from remaining in the groove. In addition, the alignment mark can be easily recognized by using different types of films for the metal layer and the cap layer. Therefore, in the lithography process,
When aligning the alignment mark with the mask, erroneous detection of alignment can be prevented.

The materials of the respective layers are not limited to those described in the above embodiment, but can be changed as appropriate without departing from the gist of the present invention.

[0054]

As described above, according to the present invention, it is possible to provide a semiconductor device having an alignment mark which can prevent erroneous detection when aligning with a mask, and a method of manufacturing the same.

[Brief description of the drawings]

FIG. 1 is a sectional view of an alignment mark of a semiconductor device according to a first embodiment of the present invention.

FIGS. 2A and 2B are cross-sectional views of a first manufacturing process of the semiconductor device according to the first embodiment of the present invention, wherein FIG.
(B) The figure shows the peripheral area.

FIGS. 3A and 3B are cross-sectional views illustrating a second manufacturing process of the semiconductor device according to the first embodiment of the present invention; FIG.
(B) The figure shows the peripheral area.

FIG. 4 is a cross-sectional view of a third manufacturing step of the semiconductor device according to the first embodiment of the present invention, wherein FIG.
(B) The figure shows the peripheral area.

FIG. 5 is a sectional view of a fourth manufacturing step of the semiconductor device according to the first embodiment of the present invention, wherein FIG.
(B) The figure shows the peripheral area.

FIG. 6 is a sectional view of a fifth manufacturing step of the semiconductor device according to the first embodiment of the present invention, wherein FIG.
(B) The figure shows the peripheral area.

FIG. 7 is a sectional view of a sixth manufacturing step of the semiconductor device according to the first embodiment of the present invention, wherein FIG.
(B) The figure shows the peripheral area.

FIG. 8 is a cross-sectional view of a first manufacturing step of a semiconductor device according to a second embodiment of the present invention, wherein FIG.
(B) The figure shows the peripheral area.

FIGS. 9A and 9B are cross-sectional views of a second manufacturing process of the semiconductor device according to the second embodiment of the present invention, wherein FIG.
(B) The figure shows the peripheral area.

FIGS. 10A and 10B are cross-sectional views of a third manufacturing process of the semiconductor device according to the second embodiment of the present invention, wherein FIG.
(B) The figure shows the peripheral area.

FIGS. 11A and 11B are cross-sectional views illustrating a fourth manufacturing process of the semiconductor device according to the second embodiment; FIG.
(B) The figure shows the peripheral area.

FIG. 12 is a sectional view of a fifth manufacturing step of the semiconductor device according to the second embodiment of the present invention.
(B) The figure shows the peripheral area.

FIG. 13 is a sectional view of a sixth manufacturing step of the semiconductor device according to the second embodiment of the present invention.
(B) The figure shows the peripheral area.

FIGS. 14A and 14B are cross-sectional views of a seventh manufacturing step of the semiconductor device according to the second embodiment of the present invention, wherein FIG.
(B) The figure shows the peripheral area.

FIG. 15 is a sectional view of an eighth manufacturing step of the semiconductor device according to the second embodiment of the present invention, wherein FIG.
(B) The figure shows the peripheral area.

FIG. 16 is a cross-sectional view of a ninth manufacturing step of the semiconductor device according to the second embodiment of the present invention.
(B) The figure shows the peripheral area.

FIG. 17 is a cross-sectional view of a tenth manufacturing step of the semiconductor device according to the second embodiment of the present invention.
(B) The figure shows the peripheral area.

FIG. 18 is a cross-sectional view of an eleventh manufacturing process of the semiconductor device according to the second embodiment of the present invention.
(B) The figure shows the peripheral area.

FIG. 19 is a sectional view of a twelfth manufacturing step of the semiconductor device according to the second embodiment of the present invention, wherein FIG.
(B) The figure shows the peripheral area.

FIG. 20 is a sectional view of a thirteenth manufacturing step of the semiconductor device according to the second embodiment of the present invention, wherein FIG.
(B) The figure shows the peripheral area.

21A is a plan view and FIG. 21B is a cross-sectional view of an alignment mark portion of a conventional semiconductor device.

[Explanation of symbols]

 10, 20, 100: silicon substrate 11, 25, 32, 110: interlayer insulating film 12, 27, 34, 120: groove 13, 28, 31, 35, 130, 38: metal layer 14, 29, 36: silicon oxide Film 15, 30, 37 Alignment mark 16, 18 Metal wiring layer 17, 26, 33 Via hole 190 Polishing agent 21 Element isolation region 22 Gate insulating film 23 Gate electrode 24 Impurity diffusion layer

Continued on the front page F-term (reference)

Claims (6)

[Claims] An interlayer insulating film provided on a semiconductor substrate on which a semiconductor element is formed; a via plug embedded in the interlayer insulating film and electrically connected to the semiconductor element; A wiring formed, wherein the wiring is formed by patterning a metal layer formed on the interlayer insulating film, wherein the wiring is formed by patterning a metal layer formed on the interlayer insulating film. A groove formed in the interlayer insulating film, a conductive film formed on the bottom surface and a side surface in the groove, and a conductive film for forming the via plug, as an alignment mark of a mask for forming a wiring; A semiconductor device, comprising: a cap layer formed on the conductive film so as to fill the trench and made of a different material from the conductive film. 2. A step of forming a via hole and a groove for an alignment mark in an interlayer insulating film on a semiconductor substrate; and forming a conductive film on the interlayer insulating film;
A step of filling a part of the groove, a step of forming a cap layer on the conductive film with a material different from the conductive film and filling the groove, a step of using the interlayer insulating film as a stopper, A semiconductor comprising: a step of polishing and flattening a conductive film while protecting the trench with the cap layer; and a step of forming a metal wiring layer on the interlayer insulating film and the conductive film. Device manufacturing method. 3. After the step of forming a metal wiring layer on the interlayer insulating film and the conductive film, the groove, the conductive film filling a part of the groove,
A step of patterning the metal wiring layer into a desired pattern by lithography and etching using an alignment mark formed on a cap layer provided on the conductive film and filling the groove. Item 3. A method for manufacturing a semiconductor device according to Item 2. 4. After the step of polishing and flattening the cap layer and the conductive film while protecting the groove with the cap layer, the method further comprises a step of removing the cap layer in the groove. 3. The method for manufacturing a semiconductor device according to claim 2, wherein: 5. After the step of forming a metal wiring layer on the interlayer insulating film and the conductive film, using an alignment mark formed by the groove and the conductive film filling a part of the groove. 5. The method according to claim 4, further comprising the step of patterning the metal wiring layer into a desired pattern by lithography and etching. 6. The step of polishing and flattening the cap layer and the conductive film while protecting the groove with the cap layer, the step of polishing the cap layer using the conductive film as a stopper; 6. The method of manufacturing a semiconductor device according to claim 2, further comprising: polishing the conductive film using the interlayer insulating film as a stopper. 7.