WO2005027326A1 - Switching element protective circuit - Google Patents

Switching element protective circuit Download PDF

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Publication number
WO2005027326A1
WO2005027326A1 PCT/JP2004/007936 JP2004007936W WO2005027326A1 WO 2005027326 A1 WO2005027326 A1 WO 2005027326A1 JP 2004007936 W JP2004007936 W JP 2004007936W WO 2005027326 A1 WO2005027326 A1 WO 2005027326A1
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WO
WIPO (PCT)
Prior art keywords
switching element
fet
voltage
switching
protection circuit
Prior art date
Application number
PCT/JP2004/007936
Other languages
French (fr)
Japanese (ja)
Inventor
Akio Iwabuchi
Hironori Aoki
Original Assignee
Sanken Electric Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanken Electric Co., Ltd. filed Critical Sanken Electric Co., Ltd.
Publication of WO2005027326A1 publication Critical patent/WO2005027326A1/en

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
    • H03K17/0822—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K2017/0806—Modifications for protecting switching circuit against overcurrent or overvoltage against excessive temperature

Definitions

  • the present invention relates to a switching element protection circuit that can prevent deterioration and destruction of electrical characteristics of a switching element during high-temperature operation.
  • a switching power supply device having a transformer for primary and secondary insulation is provided with a switching element protection circuit for preventing overheating of the switching element due to overvoltage generated in the transformer or the like when the switching element is turned off.
  • FIG. 4 shows an example of a conventional switching element protection circuit.
  • a self-extinguishing type switching element such as a MOS-FET as shown in the figure is used as the switching element.
  • the main circuit of the switching power supply is configured using (4).
  • the first main terminal (D) drawn out is the output terminal, the second main terminal drawn out of the source
  • (5) is a GND (ground) terminal, and a current limiting resistor (3), an inductive load such as a pulse transformer (2) as a load, and a DC power supply (1) are connected in series to both terminals (D, S). Then, DC power is supplied from the DC power supply (1) to the inductive load (2).
  • the control terminal (G) drawn from the gate of the MOS-FET (4) is used as an input terminal, and an input potential regulating resistor (7) is connected between the control terminal (G) and the second main terminal (S).
  • a transient overvoltage occurs between the sources, that is, between the first and second main terminals (D, S). If such an overvoltage exceeds the rated voltage of the M-S-FET (4), the element (MOS_FET (4)) is overheated and destroyed, so an overvoltage protection circuit (10) is provided as overvoltage protection means. .
  • the overvoltage protection circuit (10) is connected in series with opposite polarities between the drain and gate of the MOS-FET (4), that is, between the first main terminal (D) and the control terminal (G). It consists of two avalanche diodes (5,6). Each avalanche diode (5,6) has a sudden increase in reverse current when the reverse voltage at the PN junction exceeds the breakdown voltage.
  • Avalanche yielding (avalanche yielding) characteristics When the M ⁇ S_FET (4) is switched from the on state to the off state, if the overvoltage generated by the inductance of the inductive load (2) exceeds the breakdown voltage of the avalanche diode (5), the M ⁇ S-FET A voltage signal is applied to the control terminal (G) of (4), and the M ⁇ S_FET (4) in the turn-off state is temporarily turned on.
  • the stored energy of the inductive load (2) is discharged to the ground side through the first and second main terminals (D, S) of the M-S-FET (4), so that the MOS-FET ( The overvoltage applied between the drain and source in 4) is limited to a safe level, and the MOS-FET (4) can be protected from overvoltage.
  • the other avalanche diode (6) which is connected in reverse polarity to the avalanche diode (5), turns on the MOS_FET (4) during the high-frequency switching of the MOS-FET (4), and the drain When the voltage between the gates drops to near 0 [V], the control signal (G)
  • an overvoltage protection circuit or a snubber circuit including an avalanche diode (not shown) is provided in parallel with the drain and source of the MOS_FET (4), and the voltage is applied between the drain and source.
  • Switching element protection circuits that limit overvoltages are also known.
  • a switching element protection circuit having a configuration substantially similar to the above configuration is disclosed in, for example, Patent Document 1 below.
  • Patent Document 1 JP-A-7-288456 (Page 6, FIG. 3)
  • the overvoltage protection circuit (10) When the potential of the first main terminal (D) rises and the avalanche diode (5) constituting the overvoltage protection circuit (10) enters a breakdown (breakdown) state, the overvoltage protection starts from the first main terminal (D). A current flows into the control terminal (G) drawn from the gate of the MOS-FET (4) through the circuit (10), the potential of the gate of the M ⁇ S_FET (4) rises, and the M ⁇ S_FET (4) turns on. It becomes. M ⁇ S_FET (4) turns on and drain current I starts to flow
  • the M ⁇ S_FET (4) is continuously turned on and off. When the temperature rises, the device may be damaged beyond the limit of the reduced safe operation area. Also, since the internal resistance between the drain and source increases as the operating temperature of the MOS_FET (4) rises, the voltage V between the drain and source of the MOS-FET (4) increases, and even if the device is used below the maximum rating. Poor characteristic
  • the maximum rating of the M-S-FET (4) is made sufficiently large so that a safe operation area is provided for all operations including an abnormal state to prevent element destruction.
  • the MOS-FET (4) becomes large and the manufacturing cost rises.
  • the drain current I value (period A in Fig. 2 (B)) is limited and accumulated in the inductive load (2).
  • this method can cope with the current limiting circuit, etc., even if the resistance value of the current limiting resistor (3) varies, but also reduces the safety operating area due to temperature rise, for example. There is another problem that has no effect on this. Furthermore, when the temperature rises, the drain current I (period A in Fig. 2 (B)) can be reduced when the MOS-FET (4) is turned on.
  • an object of the present invention is to provide a switching element protection circuit that can prevent deterioration and destruction of characteristics of the switching element during high-temperature operation without increasing the size of the switching element.
  • a switching element protection circuit provides a switching element (4) having first and second main terminals (D, S) connected in series to a DC power supply (1) and a load (2). Control signal (V) to the control terminal (G) of the switching element (4) to turn on and off the switching element (4).
  • a drive circuit (9) that supplies DC power from a DC power supply (1) to a load (2) under control, and controls one of the first and second main terminals (D, S) of a switching element (4) And an overvoltage protection means (10) connected to the terminal (G).
  • the switching element (4) When the switching element (4) is turned off, the voltage (V) generated between the first and second main terminals (D, S) of the switching element (4) exceeds a predetermined level.
  • the switching element protection circuit includes a temperature detecting means (11) for detecting an operating temperature of the switching element (4) and generates a maintenance signal when the operating temperature detected by the temperature detecting means (11) exceeds a predetermined level.
  • the switching means connected between the comparing means (12), the plurality of voltage setting elements (5, 6) for setting the detection voltage of the overvoltage protection means (10), and the control terminal (G) of the switching element (4).
  • Means (13), and the switching means (13) reduces the detection voltage of the overvoltage protection means (10) when the maintenance signal of the comparison means (12) is generated.
  • the operating temperature of the switching element (4) is detected by the temperature detecting means (11), and the comparing means (12) outputs a maintenance signal when the operating temperature detected by the temperature detecting means (11) exceeds a predetermined level. appear.
  • the switching means (13) connected to the switching means (13) can reduce the detection voltage of the overvoltage protection means (10) and switch the operation of the switching element (4) to an operation within the reduced safe operation area. Therefore, at the time of high-temperature operation, the overvoltage protection means (10) is turned on at the reduced voltage level and turns on the switching element (4), so that the characteristic deterioration and destruction of the switching element (4) can be prevented. it can.
  • the switching means when the operating temperature of the switching element rises and the temperature detected by the temperature detecting means exceeds a predetermined level, the switching means reduces the detection voltage of the overvoltage protection means, and the switching element Is switched to the operation within the reduced safe operation area. For this reason, at the time of high-temperature operation, the overvoltage protection means is turned on at the lowered voltage level, and the switching element is turned on, so that deterioration and destruction of the electrical characteristics of the switching element can be prevented. Therefore, unlike the conventional case, a switching element with a sufficiently large maximum rating is not required, so that it is possible to prevent the deterioration of the electrical characteristics of the switching element at high temperature operation and the destruction due to overheating without increasing the size of the switching element. Can be. Brief Description of Drawings
  • FIG. 1 An electric circuit diagram showing an embodiment of a switching element protection circuit according to the present invention.
  • FIG. 2 Timing charts of voltage waveforms and current waveforms of respective parts in FIG. 1 and FIG.
  • FIG. 3 is an electric circuit diagram showing another embodiment of the switching element protection circuit according to the present invention.
  • FIG. 4 is an electric circuit diagram showing a conventional switching element protection circuit.
  • FIGS. 1 to 3 the same reference numerals are given to substantially the same portions as those shown in FIG. 4, and the description thereof will be omitted.
  • the switching element protection circuit of the present invention includes a temperature detecting thermistor (11) as temperature detecting means for detecting the operating temperature of the M ⁇ S_FET (4), and a temperature detecting sensor.
  • a comparison circuit (12) as a comparison means for generating a maintenance signal when the operating temperature detected by the mister (11) exceeds a predetermined level; and a plurality of voltage setting elements for setting a detection voltage of the overvoltage protection circuit (10).
  • the difference from the conventional switching element protection circuit shown in FIG. 4 is that the detection means of the overvoltage protection circuit (10) is reduced by the switching means (13) when the maintenance signal of the comparison circuit (12) is generated.
  • the overvoltage protection circuit (10) is provided between the first main terminal (D) of the MOS-FET (4) and the control terminal (G).
  • An avalanche diode (5, 6) as a constant voltage element having avalanche breakdown characteristics is connected in series with the same polarity.
  • the resistance of the thermistor for temperature detection (11) changes in response to the change in the operating temperature of the chip (element) that constitutes the M ⁇ S-FET (4), and the change in the resistance is determined by the change in the voltage level between both ends. Detect as a change.
  • the switching means (13) is connected in parallel with the avalanche diode (6), and is turned on by a high voltage (H) level maintenance signal output from the comparison circuit (12). ).
  • H high voltage
  • the comparison circuit (12) applies a high voltage (H) level maintenance signal to the base of the transistor (14).
  • Other configurations are substantially the same as those of the conventional switching element protection circuit shown in FIG.
  • a control signal applied from the drive circuit (9) to the control terminal (G) of the MOS_FET (4) via the gate series resistor (8) V is low and voltage (L) level at time t
  • the M ⁇ S-FET (4) turns on, the voltage of the DC power supply (1) is applied to the inductive load (2), and flows to the inductive load (2)
  • the current I gradually increases and energy is stored in the inductive load (2).
  • the voltage applied to the inductive load (2) is Since the voltage of the DC power supply (1) is reduced by the limiting resistor (3), the current I flowing to the inductive load (2) is limited. Accordingly, the drain current I flowing through the MOS_FET (4) is
  • the current gradually increases as shown in 2 (B) and reaches the current value limited by the current limiting resistor (3) at time t.
  • the inductive load (2) is turned off to generate a back electromotive force, and the stored energy is released.
  • a transient overvoltage occurs between the first and second main terminals (D, S) of the MFETS_FET (4) when the M ⁇ S_FET (4) is turned off, as shown in FIG. 2 (C).
  • the voltage V between the first and second main terminals (D, S) of the MOS_FET (4) rises rapidly, forming the overvoltage protection circuit (10).
  • the MOS_FET (4) can be protected against overvoltage.
  • the drain current I flowing through the MOS_FET (4) gradually decreases. In the MOS-FET (4), the drain current I decreases between the first and second main terminals (D, S). mark
  • the operating temperature of the element constituting the MOS-FET (4) is detected as a voltage level by a temperature detecting thermistor (11).
  • the voltage V between the first and second main terminals (D, S) of the MOS-FET (4) drops sharply from the value at time t to approximately o [v].
  • FIG. 2 (B) and 2 (C) show the operation of the conventional circuit shown in FIG.
  • the stored energy from the inductive load (2) is generated by the high overvoltage generated between the first and second main terminals (D, S) when the MOS-FET (4) is turned off. Because of the release, the release of the stored energy is completed at time t earlier than time t . Power, while the overvoltage protection circuit
  • the MOS-FET (4) Since the operating temperature of the M-S-FET (4) rises significantly during the overvoltage clamping period B due to (10), the first and second main terminals (D, S If the voltage V and the drain current I exceed the safe operating area due to the rise in operating temperature, the MOS-FET (4) will be destroyed by overheating. On the other hand, in the circuit according to the first embodiment shown in FIG. 1, since the voltage V at which the accumulated energy of the inductive load (2) is released is lower, the stored energy is lower than that of the conventional circuit shown in FIG. However, the power generated by the M ⁇ S-FET (4) is reduced by the lower voltage V between the first and second main terminals (D, S) of the M ⁇ S-FET (4).
  • the operating temperature of the M ⁇ S-FET (4) during the overvoltage clamp period B is also suppressed to be lower than in the conventional circuit shown in FIG. Therefore, at the time of high-temperature operation, the M ⁇ S-FET (4) can be protected from overvoltage, and the characteristic deterioration and destruction of the M ⁇ S-FET (4) can be prevented.
  • the operating temperature of the MOS-FET (4) is detected by the temperature detecting thermistor (11), and when the operating temperature exceeds a predetermined level, the comparison circuit (12) Then, a high voltage (H) level maintenance signal is applied to the base of the transistor (14) constituting the switching means (13). As a result, the transistor (14) is turned on, and one of the two diodes (5, 6) constituting the overvoltage protection circuit (10) is short-circuited, so that the detection voltage of the overvoltage protection circuit (10) decreases. Then, the voltage V between the first and second main terminals (D, S) of the MOS-FET (4) becomes Since it decreases, MOS_FET (4) can be switched to operation within the reduced safe operation area.
  • the overvoltage protection circuit (10) is turned on at the reduced voltage level, and the M ⁇ S-FET (4) is temporarily turned on.
  • the MOS-FET (4) can be protected from overvoltage generated by the inductive load (2) during operation, and the electrical characteristics of the MOS-FET (4) can be prevented from being deteriorated or destroyed.
  • FIG. 1 The first embodiment shown in FIG. 1 can be modified.
  • a switching element protection circuit according to a second embodiment which is another embodiment of the present invention, is connected to a first main terminal (D) of a MOS-FET (4).
  • Two avalanche diodes (5, 6) are connected in parallel with the terminal (G) to form an overvoltage protection circuit (10), and two transistors (switch means) (14a, 14b) are connected to two terminals.
  • the switching means (13) is constituted by connecting in series with each of the two avalanche diodes (5, 6).
  • the comparison circuit (12) When the detection voltage of the temperature detection thermistor (11) is lower than a predetermined voltage level, the comparison circuit (12) outputs a high voltage (H) level to one of the bases of the two transistors (14a, 14b). The maintenance signal is applied to selectively turn on one of the transistors (14a, 14b). When the detection voltage of the temperature detection thermistor (11) exceeds a predetermined voltage level, the two transistors (14a, 14a) are turned on. , 14b), a high voltage (H) level maintenance signal is applied to each base to simultaneously turn on the two transistors (14a, 14b).
  • Other configurations are substantially the same as those of the switching element protection circuit according to the first embodiment shown in FIG.
  • the comparison circuit (12 ) when the operating temperature of the M-S-FET (4) rises and the detection voltage of the temperature detection thermistor (11) exceeds a predetermined voltage level, the comparison circuit (12 ), The two transistors (14a, 14b) are simultaneously turned on, and the detection voltage of the overvoltage protection circuit (10), that is, the first main terminal (D) and the control terminal (G) of the MOS-FET (4) The voltage between the first and second main terminals (D, S) of the MOS-FET (4) decreases. As a result, the operation of the MOS-FET (4) can be switched to the operation within the lowered safe operation area (S ⁇ A). Therefore, in the second embodiment shown in FIG. 3, as in the first embodiment shown in FIG.
  • the overvoltage protection circuit (10) Is turned on and the MOS-FET (4) is turned on temporarily, so that the MOS-FET (4) can be protected from the overvoltage generated by the inductive load (2) and the M ⁇ S_FET (4) Deterioration and destruction of electrical characteristics can be prevented.
  • the temperature detection thermistor (11) may be mounted on the same semiconductor substrate as the MOS_FET (4).
  • the thermal coupling between the heat-generating portion of the MOS_FET (4) and the temperature detecting means (11) such as a temperature detecting thermistor becomes tight, so that the temperature rise of the MOS-FET (4) is monitored by the temperature detecting means (11 ),
  • the overheat protection circuit can be operated quickly and reliably by detecting quickly and accurately.
  • a temperature detecting means for detecting a temperature based on a forward voltage, a reverse leakage current or the like of a semiconductor element built in the semiconductor substrate may be provided.
  • a plurality of overvoltage protection circuits (10), a plurality of temperature detecting means (11) such as a thermistor for temperature detection, and a plurality of transistors (14) are provided, and a temperature or inductive characteristic of the MOS-FET (4) is provided.
  • the detection voltage of the overvoltage protection circuit (10) may be adjusted by appropriately switching the plurality of transistors (14) according to the magnitude of the overvoltage generated in the load (2). In this case, the detection voltage of the overvoltage protection circuit (10) is adjusted according to the temperature of the MOS-FET (4) or the magnitude of the overvoltage generated in the inductive load (2).
  • the overheat protection circuit can be operated in a finely detailed manner in response to changes in the ambient temperature and fluctuations in the inductive load (2).
  • the switching means (13) is configured by connecting two transistors (14a, 14b) in series with each of the two avalanche diodes (5, 6). The two transistors
  • One of (14a, 14b) is omitted, and when the operating temperature of the MOS_FET (4) rises and the detection voltage of the temperature detection thermistor (11) exceeds a predetermined voltage level, the comparison circuit (12) The transistor (14) is turned on to reduce the voltage between the first main terminal (D) and the control terminal (G) of the MOS-FET (4), and the first and second main terminals of the MOS_FET (4) are reduced. Low voltage V between terminals (D, S)
  • the power MOS-FET (4) in which the second main terminal (S) drawn from the source of the M-S-FET (4) is set to the ground potential is used.
  • the first main terminal (D) drawn out may be set to the ground potential.
  • the overvoltage protection circuit (10) is configured using a plurality of avalanche (avalanche) diodes.
  • the overvoltage protection circuit (10) may be configured using a transistor switch or the like.
  • the present invention can be applied to a self-extinguishing type switching element other than M ⁇ S_FET (MOS type field effect transistor), for example, IGBT (insulated gate type transistor) or SIT (static induction type transistor). Noh.
  • the present invention has a remarkable effect on a switching element protection circuit and a solenoid driving device of a switching power supply device used in a high temperature environment.

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Abstract

A switching element protective circuit comprising a thermistor (11) for detecting the operating temperature of an MOSFET (4), a comparison circuit (12) generating a maintenance signal when an operating temperature detected by the temperature detecting thermistor (11) exceeds a specified level, two avalanche diodes (5, 6) for setting the detection voltage of an overvoltage protective circuit (10), and a transistor (14) connected between the avalanche diodes (5, 6) and the control terminal of the MOSFET (4). When a maintenance signal is generated from the comparison circuit (12), the transistor (14) is turned on to lower the detection voltage of the overvoltage protective circuit (10) and the MOSFET (4) is switched from a high temperature operation down to an operation in a safety operation region. Consequently, the MOSFET (4) can be protected against degradation in characteristics or breakdown during high temperature operation without increasing the size thereof.

Description

明 細 書  Specification
スイッチング素子保護回路  Switching element protection circuit
技術分野  Technical field
[0001] 本発明は、高温動作時にスイッチング素子の電気的特性の劣化や破壊を防止でき るスイッチング素子保護回路に関する。  The present invention relates to a switching element protection circuit that can prevent deterioration and destruction of electrical characteristics of a switching element during high-temperature operation.
背景技術  Background art
[0002] 一般に、一次及び二次絶縁用のトランスを有するスイッチング電源装置では、スイツ チング素子のターンオフ時にトランス等で発生する過電圧によるスイッチング素子の 過熱破壊を防止するスイッチング素子保護回路が設けられる。図 4は、従来のスイツ チング素子保護回路の一例を示す。図 4に示すスイッチング素子保護回路では、スィ ツチング素子として自己消弧型のスイッチング素子、例えば図示のように MOS-FET [0002] Generally, a switching power supply device having a transformer for primary and secondary insulation is provided with a switching element protection circuit for preventing overheating of the switching element due to overvoltage generated in the transformer or the like when the switching element is turned off. FIG. 4 shows an example of a conventional switching element protection circuit. In the switching element protection circuit shown in FIG. 4, a self-extinguishing type switching element such as a MOS-FET as shown in the figure is used as the switching element.
(4)を使用してスイッチング電源装置の主回路を構成する。 MOS_FET(4)のドレイン 力 引き出された第 1の主端子 (D)を出力端子、ソースから引き出された第 2の主端子The main circuit of the switching power supply is configured using (4). MOS_FET (4) drain power The first main terminal (D) drawn out is the output terminal, the second main terminal drawn out of the source
(5)を GND (接地)端子とし、両端子 (D,S)に電流制限抵抗 (3)、負荷としてのパルストラ ンス等の誘導性負荷 (2)及び直流電源 (1)を直列に接続して、直流電源 (1)から誘導性 負荷 (2)に直流電力を供給する。また、 MOS-FET(4)のゲートから引き出された制御 端子 (G)を入力端子とし、制御端子 (G)と第 2の主端子 (S)との間に入力電位規定抵抗 (7)を接続すると共に、制御端子 (G)に接続されたゲート直列抵抗 (8)を介して駆動回 路 (9)を接続し、駆動回路 (9)から出力される制御信号 Vによって MOS-FET(4)をォ (5) is a GND (ground) terminal, and a current limiting resistor (3), an inductive load such as a pulse transformer (2) as a load, and a DC power supply (1) are connected in series to both terminals (D, S). Then, DC power is supplied from the DC power supply (1) to the inductive load (2). The control terminal (G) drawn from the gate of the MOS-FET (4) is used as an input terminal, and an input potential regulating resistor (7) is connected between the control terminal (G) and the second main terminal (S). Drive circuit (9) via the gate series resistor (8) connected to the control terminal (G), and the MOS-FET (4 )
G  G
ン 'オフ制御することにより、制御信号 Vの時比率に対応して誘導性負荷 (2)に供給  Control to supply the inductive load (2) according to the duty ratio of the control signal V.
G  G
される直流電力を制御することができる。  DC power to be controlled.
[0003] 図 4に示す M〇S_FET(4)をオン.オフ制御すると、 MOS-FET(4)のターンオン時 に誘導性負荷 (2)のインダクタンスにエネルギを蓄積し、 MOS_FET(4)のターンオフ 時に誘導性負荷 (2)に流れる電流 Iを遮断することにより、 MOS_FET(4)のドレイン一 し  [0003] When the MFETS_FET (4) shown in Fig. 4 is turned on and off, energy is accumulated in the inductance of the inductive load (2) when the MOS-FET (4) is turned on, and the MOS_FET (4) is turned off. By interrupting the current I flowing through the inductive load (2) at times, the drain of the MOS_FET (4)
ソース間、即ち第 1及び第 2の主端子 (D，S)間に過渡的な過電圧が発生する。このよう な過電圧が M〇S-FET(4)の定格電圧を超えると、素子（MOS_FET(4))が過熱して 破壊されるため、過電圧保護手段としての過電圧保護回路 (10)が設けられる。 [0004] 過電圧保護回路 (10)は、 MOS-FET(4)のドレイン一ゲート間、即ち第 1の主端子 (D) と制御端子 (G)との間に互いに逆極性で直列に接続された 2つのアバランシェ（雪崩） ダイオード (5,6)から構成され、各アバランシヱダイオード (5,6)は、 PN接合での逆方向 電圧が降伏電圧を超えると、逆方向電流が急激に増加するアバランシェ降伏（雪崩 降伏）特性を有する。 M〇S_FET(4)がオンからオフ状態に切り換えられたときに、誘 導性負荷 (2)のインダクタンスにより発生する過電圧がアバランシェダイオード (5)の降 伏電圧を超えると、 M〇S-FET(4)の制御端子 (G)に電圧信号が付与され、ターンォ フ状態の M〇S_FET(4)が一時的にオン状態となる。このとき、誘導性負荷 (2)の蓄積 エネルギが M〇S- FET(4)の第 1及び第 2の主端子 (D,S)を介して接地側に放出され るので、 MOS-FET(4)のドレイン一ソース間に印加される過電圧が安全なレベルに 制限され、 MOS-FET(4)を過電圧から保護することができる。また、アバランシヱダイ オード (5)に対して逆極性に接続された他方のアバランシヱダイオード (6)は、 MOS-F ET(4)の高周波スイッチング中に MOS_FET(4)がオンして、ドレイン一ゲート間の電 圧が 0[V]近くまで低下したとき、ゲートに付与される制御信号 Vにより制御端子 (G) A transient overvoltage occurs between the sources, that is, between the first and second main terminals (D, S). If such an overvoltage exceeds the rated voltage of the M-S-FET (4), the element (MOS_FET (4)) is overheated and destroyed, so an overvoltage protection circuit (10) is provided as overvoltage protection means. . [0004] The overvoltage protection circuit (10) is connected in series with opposite polarities between the drain and gate of the MOS-FET (4), that is, between the first main terminal (D) and the control terminal (G). It consists of two avalanche diodes (5,6). Each avalanche diode (5,6) has a sudden increase in reverse current when the reverse voltage at the PN junction exceeds the breakdown voltage. Avalanche yielding (avalanche yielding) characteristics. When the M〇S_FET (4) is switched from the on state to the off state, if the overvoltage generated by the inductance of the inductive load (2) exceeds the breakdown voltage of the avalanche diode (5), the M〇S-FET A voltage signal is applied to the control terminal (G) of (4), and the M〇S_FET (4) in the turn-off state is temporarily turned on. At this time, the stored energy of the inductive load (2) is discharged to the ground side through the first and second main terminals (D, S) of the M-S-FET (4), so that the MOS-FET ( The overvoltage applied between the drain and source in 4) is limited to a safe level, and the MOS-FET (4) can be protected from overvoltage. Also, the other avalanche diode (6), which is connected in reverse polarity to the avalanche diode (5), turns on the MOS_FET (4) during the high-frequency switching of the MOS-FET (4), and the drain When the voltage between the gates drops to near 0 [V], the control signal (G)
G  G
力 過電圧保護回路 (10)を介して第 1の主端子 (D)に向けて電流が流れることを防止 する。  Prevents current from flowing toward the first main terminal (D) via the overvoltage protection circuit (10).
[0005] 上記のスイッチング素子保護回路以外に、 MOS_FET(4)のドレイン一ソース間と並 列に図示しないアバランシヱダイオードから成る過電圧保護回路又はスナバ回路を 設けて、ドレイン一ソース間に印加される過電圧を制限するスイッチング素子保護回 路も知られている。前記構成に略類似する構成を有するスイッチング素子保護回路 は、例えば下記の特許文献 1に開示されている。  [0005] In addition to the above switching element protection circuit, an overvoltage protection circuit or a snubber circuit including an avalanche diode (not shown) is provided in parallel with the drain and source of the MOS_FET (4), and the voltage is applied between the drain and source. Switching element protection circuits that limit overvoltages are also known. A switching element protection circuit having a configuration substantially similar to the above configuration is disclosed in, for example, Patent Document 1 below.
特許文献 1 :特開平 7— 288456号公報 (第 6頁、図 3)  Patent Document 1: JP-A-7-288456 (Page 6, FIG. 3)
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0006] ところで、図 4に示す構成の回路では、 MOS-FET(4)のオフ時に誘導性負荷 (2)の 蓄積エネルギを放出する必要があり、また一般的な MOS-FETでは順バイアス動作 時の安全動作領域（SOA: Safe Operation Area)の方が逆バイアス動作時の安全動 作領域よりも支配的であるため、 MOS-FET(4)のドレイン一ゲート間に過電圧保護回 路 (10)が接続される。即ち、 M〇S-FET(4)のオフ時に誘導性負荷 (2)の蓄積エネル ギの放出により逆起電圧が発生すると、 M〇S-FET(4)のドレインから引き出された第 1の主端子 (D)の電位が上昇する。第 1の主端子 (D)の電位が上昇して過電圧保護回 路 (10)を構成するアバランシェダイオード (5)が降伏（ブレークダウン)状態になると、第 1の主端子 (D)から過電圧保護回路 (10)を通して MOS-FET(4)のゲートから引き出さ れた制御端子 (G)に電流が流れ込み、 M〇S_FET(4)のゲートの電位が上昇して M〇 S_FET(4)がオン状態となる。 M〇S_FET(4)がオンしてドレイン電流 Iが流れ始める By the way, in the circuit having the configuration shown in FIG. 4, it is necessary to release the energy stored in the inductive load (2) when the MOS-FET (4) is turned off. The safe operation area (SOA) during operation is more dominant than the safe operation area during reverse bias operation, so the overvoltage protection circuit is connected between the drain and gate of the MOS-FET (4). Road (10) is connected. That is, when a back electromotive voltage is generated due to the release of the stored energy of the inductive load (2) when the M〇S-FET (4) is off, the first voltage drawn from the drain of the M〇S-FET (4) The potential of the main terminal (D) rises. When the potential of the first main terminal (D) rises and the avalanche diode (5) constituting the overvoltage protection circuit (10) enters a breakdown (breakdown) state, the overvoltage protection starts from the first main terminal (D). A current flows into the control terminal (G) drawn from the gate of the MOS-FET (4) through the circuit (10), the potential of the gate of the M〇S_FET (4) rises, and the M〇S_FET (4) turns on. It becomes. M〇S_FET (4) turns on and drain current I starts to flow
D  D
と、第 1の主端子 (D)の電位の上昇が停止し、誘導性負荷 (2)の蓄積エネルギが放出 される。このとき、 M〇S_FET(4)は順バイアス動作となるため、安全動作領域が高く なる。  Then, the rise of the potential of the first main terminal (D) stops, and the stored energy of the inductive load (2) is released. At this time, since the M〇S_FET (4) performs a forward bias operation, the safe operation area increases.
[0007] し力 ながら、 MOS-FET(4)の安全動作領域（S〇A)は、温度の上昇に伴レ、低下 するため、 M〇S_FET(4)を連続的にオン'オフ動作させると温度が上昇し、低下した 安全動作領域の限界を超えて素子が破壊される場合がある。また、 MOS_FET(4) の動作温度の上昇に伴いドレイン ソース間の内部抵抗が増加するため、 MOS-FE T(4)のドレイン ソース間の電圧 V が上昇し、最大定格以下で使用しても特性の劣  However, since the safe operating area (S〇A) of the MOS-FET (4) decreases as the temperature rises, the M〇S_FET (4) is continuously turned on and off. When the temperature rises, the device may be damaged beyond the limit of the reduced safe operation area. Also, since the internal resistance between the drain and source increases as the operating temperature of the MOS_FET (4) rises, the voltage V between the drain and source of the MOS-FET (4) increases, and even if the device is used below the maximum rating. Poor characteristic
DS  DS
化や破壊を引き起こすことがある。一方、誘導性負荷 (2)のインダクタンス値が変動す る場合、例えばインダクタンス値が増加する場合には、誘導性負荷 (2)に流れる電流 I 値が同一であっても放出されるエネルギ量が大きいため、結局、安全動作領域の限 界を超えて素子が破壊される可能性がある。  May cause chemical breakdown and destruction. On the other hand, when the inductance value of the inductive load (2) fluctuates, for example, when the inductance value increases, the amount of energy released even if the current I value flowing through the inductive load (2) is the same. Because of its large size, the device may eventually be destroyed beyond the safe operating area.
[0008] ここで、 M〇S-FET(4)の最大定格を十分に大きくして異常時を含めた全動作に対 して安全動作領域に余裕を持たせて素子の破壊を防止する対策が考えられるが、 M OS-FET(4)が大型となり、製造コストも高騰する問題がある。また、 M〇S- FET(4)の オン時にドレイン電流 I値（図 2(B)の期間 A)を制限して誘導性負荷 (2)に蓄積される [0008] Here, the maximum rating of the M-S-FET (4) is made sufficiently large so that a safe operation area is provided for all operations including an abnormal state to prevent element destruction. However, there is a problem that the MOS-FET (4) becomes large and the manufacturing cost rises. When the M〇S-FET (4) is turned on, the drain current I value (period A in Fig. 2 (B)) is limited and accumulated in the inductive load (2).
D  D
エネルギを制限する方法も考えられるが、この方法は、電流制限抵抗 (3)の抵抗値に ばらつきがあっても電流制限回路等により対応できる反面、例えば温度上昇による安 全動作領域の低下等に対しては効果がない別の問題がある。更に、温度が上昇した ときに MOS-FET(4)のオン時にドレイン電流 I (図 2(B)の期間 A)を低下させることも  Although a method of limiting energy is conceivable, this method can cope with the current limiting circuit, etc., even if the resistance value of the current limiting resistor (3) varies, but also reduces the safety operating area due to temperature rise, for example. There is another problem that has no effect on this. Furthermore, when the temperature rises, the drain current I (period A in Fig. 2 (B)) can be reduced when the MOS-FET (4) is turned on.
D  D
考えられる力 M〇S_FET(4)のオン時の発熱や平均温度の上昇に対して効果があ る反面、最も発熱量の多い過電圧のクランプ時（図 2(C)の期間 B)には十分な効果が 得られない難点がある。したがって、 MOS_FET(4)の最大定格を十分に大きくする 以外に現実的方法がなぐこのため M〇S-FET(4)が大型となる欠点があった。 Possible force Effective against heat generation when M 平均 S_FET (4) is turned on and increase in average temperature. On the other hand, there is a disadvantage that sufficient effect cannot be obtained when clamping the overvoltage that generates the largest amount of heat (period B in Fig. 2 (C)). Therefore, there is a drawback that the M〇S-FET (4) becomes large because there is no practical method other than sufficiently increasing the maximum rating of the MOS_FET (4).
[0009] そこで、本発明はスイッチング素子を大型化せずに高温動作時にスイッチング素子 の特性劣化や破壊を防止できるスイッチング素子保護回路を提供することを目的と する。 [0009] Therefore, an object of the present invention is to provide a switching element protection circuit that can prevent deterioration and destruction of characteristics of the switching element during high-temperature operation without increasing the size of the switching element.
課題を解決するための手段  Means for solving the problem
[0010] 本発明によるスイッチング素子保護回路は、直流電源 (1)及び負荷 (2)に対して直列 に接続された第 1及び第 2の主端子 (D,S)を有するスイッチング素子 (4)と、スィッチン グ素子 (4)の制御端子 (G)に制御信号 (V )を付与し、スイッチング素子 (4)をオン'オフ [0010] A switching element protection circuit according to the present invention provides a switching element (4) having first and second main terminals (D, S) connected in series to a DC power supply (1) and a load (2). Control signal (V) to the control terminal (G) of the switching element (4) to turn on and off the switching element (4).
G  G
制御させて直流電源 (1)から負荷 (2)に直流電力を供給する駆動回路 (9)と、スィッチン グ素子 (4)の第 1及び第 2の主端子 (D，S)の一方と制御端子 (G)との間に接続された過 電圧保護手段 (10)とを備えている。スイッチング素子 (4)のターンオフ時にスイッチング 素子 (4)の第 1及び第 2の主端子 (D，S)間に発生する電圧 (V )が所定のレベルを超え  A drive circuit (9) that supplies DC power from a DC power supply (1) to a load (2) under control, and controls one of the first and second main terminals (D, S) of a switching element (4) And an overvoltage protection means (10) connected to the terminal (G). When the switching element (4) is turned off, the voltage (V) generated between the first and second main terminals (D, S) of the switching element (4) exceeds a predetermined level.
DS  DS
るとき、過電圧保護手段 (10)がオン状態となり、スイッチング素子 (4)の制御端子 (G)に 制御信号 (V )を付与して前記スイッチング素子 (4)をターンオンさせる。このスィッチン  When the overvoltage protection means (10) is turned on, the control signal (V) is applied to the control terminal (G) of the switching element (4) to turn on the switching element (4). This switchin
G  G
グ素子保護回路は、スィッチング素子 (4)の動作温度を検出する温度検出手段 (11)と 、温度検出手段 (11)により検出した動作温度が所定のレベルを越えるときに保全信 号を発生する比較手段 (12)と、過電圧保護手段 (10)の検出電圧を設定する複数の電 圧設定素子 (5，6)とスイッチング素子 (4)の制御端子 (G)との間に接続された切換手段 (13)とを備え、切換手段 (13)は比較手段 (12)の保全信号が発生したときに過電圧保護 手段 (10)の検出電圧を低下させる。  The switching element protection circuit includes a temperature detecting means (11) for detecting an operating temperature of the switching element (4) and generates a maintenance signal when the operating temperature detected by the temperature detecting means (11) exceeds a predetermined level. The switching means connected between the comparing means (12), the plurality of voltage setting elements (5, 6) for setting the detection voltage of the overvoltage protection means (10), and the control terminal (G) of the switching element (4). Means (13), and the switching means (13) reduces the detection voltage of the overvoltage protection means (10) when the maintenance signal of the comparison means (12) is generated.
[0011] スイッチング素子 (4)の動作温度が上昇すると、スイッチング素子 (4)の安全動作領 域が低下すると共に、スイッチング素子 (4)の第 1及び第 2の主端子 (D，S)間の内部抵 杭が増加する。これに伴い第 1及び第 2の主端子 (D,S)間の電圧 (V )が上昇し、最大 [0011] When the operating temperature of the switching element (4) rises, the safe operating area of the switching element (4) decreases, and the first and second main terminals (D, S) of the switching element (4) are connected. The internal pile increases. As a result, the voltage (V) between the first and second main terminals (D, S) rises,
DS  DS
定格以下で使用しても特性の劣化や破壊を起こすことがある。そこで、温度検出手段 (11)によりスイッチング素子 (4)の動作温度を検出し、比較手段 (12)は、温度検出手段 (11)により検出した動作温度が所定のレベルを越えるときに保全信号を発生する。比 較手段 (12)の保全信号が発生したとき、過電圧保護手段 (10)の検出電圧を設定する 複数の電圧設定素子 (5,6)とスイッチング素子 (4)の制御端子 (G)との間に接続された 切換手段 (13)は、過電圧保護手段 (10)の検出電圧を低下させて、スイッチング素子 (4)を低下した安全動作領域内での動作に切り換えることができる。したがって、高温 動作時に、過電圧保護手段 (10)は低下された電圧レベルでオン状態となり、スィッチ ング素子 (4)をターンオンさせるので、スイッチング素子 (4)の特性劣化や破壊を防止 すること力 Sできる。 Degradation or destruction of characteristics may occur even if used below the rating. Therefore, the operating temperature of the switching element (4) is detected by the temperature detecting means (11), and the comparing means (12) outputs a maintenance signal when the operating temperature detected by the temperature detecting means (11) exceeds a predetermined level. appear. ratio Set the detection voltage of the overvoltage protection means (10) when the maintenance signal of the comparison means (12) is generated.Between the voltage setting elements (5, 6) and the control terminal (G) of the switching element (4) The switching means (13) connected to the switching means (13) can reduce the detection voltage of the overvoltage protection means (10) and switch the operation of the switching element (4) to an operation within the reduced safe operation area. Therefore, at the time of high-temperature operation, the overvoltage protection means (10) is turned on at the reduced voltage level and turns on the switching element (4), so that the characteristic deterioration and destruction of the switching element (4) can be prevented. it can.
発明の効果  The invention's effect
[0012] 本発明によれば、スイッチング素子の動作温度が上昇して温度検出手段の検出温 度が所定のレベルを超えたとき、切換手段により過電圧保護手段の検出電圧を低下 させて、スイッチング素子を低下した安全動作領域内での動作に切り換える。このた め、高温動作時に、低下された電圧レベルで過電圧保護手段がオン状態となり、スィ ツチング素子をターンオンさせるので、スイッチング素子の電気的特性の劣化や破壊 を防止することができる。したがって、従来のように、十分に大きな最大定格のスイツ チング素子を必要としないので、スイッチング素子を大型化させずに高温動作時にス イッチング素子の電気的特性の劣化や過熱による破壊を防止することができる。 図面の簡単な説明  [0012] According to the present invention, when the operating temperature of the switching element rises and the temperature detected by the temperature detecting means exceeds a predetermined level, the switching means reduces the detection voltage of the overvoltage protection means, and the switching element Is switched to the operation within the reduced safe operation area. For this reason, at the time of high-temperature operation, the overvoltage protection means is turned on at the lowered voltage level, and the switching element is turned on, so that deterioration and destruction of the electrical characteristics of the switching element can be prevented. Therefore, unlike the conventional case, a switching element with a sufficiently large maximum rating is not required, so that it is possible to prevent the deterioration of the electrical characteristics of the switching element at high temperature operation and the destruction due to overheating without increasing the size of the switching element. Can be. Brief Description of Drawings
[0013] [図 1]本発明によるスイッチング素子保護回路の一実施の形態を示す電気回路図 [図 2]図 1及び図 4の各部の電圧波形及び電流波形のタイミングチャート  [FIG. 1] An electric circuit diagram showing an embodiment of a switching element protection circuit according to the present invention. [FIG. 2] Timing charts of voltage waveforms and current waveforms of respective parts in FIG. 1 and FIG.
[図 3]本発明によるスイッチング素子保護回路の他の実施の形態を示す電気回路図 [図 4]従来のスィッチング素子保護回路を示す電気回路図  FIG. 3 is an electric circuit diagram showing another embodiment of the switching element protection circuit according to the present invention. FIG. 4 is an electric circuit diagram showing a conventional switching element protection circuit.
符号の説明  Explanation of symbols
[0014] (1)··直流電源、 （2)··誘導性負荷 (負荷）、 （3)··電流制限抵抗、 （4)''MOS-F ET (スイッチング素子）、 （5,6)· ·アバランシヱダイオード（電圧設定素子 Z定電圧素 子）、 （7)··入力電位規定抵抗、 （8)··ゲート直列抵抗、 （9)··駆動回路、 （10)·· 過電圧保護回路 (過電圧保護手段）、 （11)··温度検出用サーミスタ (温度検出手段 )、 （12)··比較回路（比較手段）、 （13)··切換手段、 （14，14a，14b)''トランジスタ（ス イッチ手段）、 （0)''第1の主端子、 （¾··第 2の主端子、 （G)''制御端子、 発明を実施するための最良の形態 [0014] (1) DC power supply, (2) inductive load (load), (3) current limiting resistor, (4) '' MOS-FET (switching element), (5,6 Avalanche diode (voltage setting element Z constant voltage element), (7) input voltage regulation resistance, (8) gate series resistance, (9) drive circuit, (10) Overvoltage protection circuit (overvoltage protection means), (11) · Thermistor for temperature detection (temperature detection means), (12) · Comparison circuit (comparison means), (13) · Switching means, (14, 14a, 14b) ) '' Transistor (switch means), (0) '' first main terminal, (¾ ... second main terminal, (G) '' control terminal, BEST MODE FOR CARRYING OUT THE INVENTION
[0015] 以下、本発明によるスイッチング素子保護回路の 2つの実施の形態を図 1から図 3 について説明する。図 1から図 3では図 4に示す箇所と実質的に同一の部分には同 一の符号を付し、その説明を省略する。  Hereinafter, two embodiments of a switching element protection circuit according to the present invention will be described with reference to FIGS. 1 to 3. In FIGS. 1 to 3, the same reference numerals are given to substantially the same portions as those shown in FIG. 4, and the description thereof will be omitted.
[0016] 本発明のスイッチング素子保護回路は、図 1に示すように、 M〇S_FET(4)の動作 温度を検出する温度検出手段としての温度検出用サーミスタ (11)と、温度検出用サ 一ミスタ (11)により検出した動作温度が所定のレベルを越えるときに保全信号を発生 する比較手段としての比較回路 (12)と、過電圧保護回路 (10)の検出電圧を設定する 複数の電圧設定素子としての定電圧素子 (5,6)と、定電圧素子 (5,6)と M〇S-FET(4) の制御端子 (G)との間に接続された切換手段 (13)とを備え、比較回路 (12)の保全信号 が発生したときに切換手段 (13)により過電圧保護回路 (10)の検出電圧を低下させる 点で、図 4に示す従来のスイッチング素子保護回路と異なる。  As shown in FIG. 1, the switching element protection circuit of the present invention includes a temperature detecting thermistor (11) as temperature detecting means for detecting the operating temperature of the M〇S_FET (4), and a temperature detecting sensor. A comparison circuit (12) as a comparison means for generating a maintenance signal when the operating temperature detected by the mister (11) exceeds a predetermined level; and a plurality of voltage setting elements for setting a detection voltage of the overvoltage protection circuit (10). A constant-voltage element (5, 6), and switching means (13) connected between the constant-voltage element (5, 6) and the control terminal (G) of the M-S-FET (4). The difference from the conventional switching element protection circuit shown in FIG. 4 is that the detection means of the overvoltage protection circuit (10) is reduced by the switching means (13) when the maintenance signal of the comparison circuit (12) is generated.
[0017] 図 1に示す本発明の第 1の実施の形態では、過電圧保護回路 (10)は、 MOS-FET (4)の第 1の主端子 (D)と制御端子 (G)との間に雪崩降伏特性を有する 2つの定電圧素 子としてのアバランシヱダイオード (5,6)を互いに同極性で直列に接続して構成される 。温度検出用サーミスタ (11)は、 M〇S- FET(4)を構成するチップ（素子）の動作温度 の変化に対応して抵抗値が変化し、その抵抗値の変化をその両端電圧レベルの変 化として検出する。切換手段 (13)は、アバランシ工ダイオード (6)に並列に接続され、 比較回路 (12)から出力される高い電圧 (H)レベルの保全信号によりオン状態となるス イッチ手段としてのトランジスタ (14)を有する。温度検出用サーミスタ (11)の検出電圧 が所定の電圧レベルを越えるときに、比較回路 (12)は、高い電圧 (H)レベルの保全信 号をトランジスタ (14)のベースに付与する。その他の構成は、図 4に示す従来のスイツ チング素子保護回路と略同様である。  In the first embodiment of the present invention shown in FIG. 1, the overvoltage protection circuit (10) is provided between the first main terminal (D) of the MOS-FET (4) and the control terminal (G). An avalanche diode (5, 6) as a constant voltage element having avalanche breakdown characteristics is connected in series with the same polarity. The resistance of the thermistor for temperature detection (11) changes in response to the change in the operating temperature of the chip (element) that constitutes the M〇S-FET (4), and the change in the resistance is determined by the change in the voltage level between both ends. Detect as a change. The switching means (13) is connected in parallel with the avalanche diode (6), and is turned on by a high voltage (H) level maintenance signal output from the comparison circuit (12). ). When the detection voltage of the temperature detection thermistor (11) exceeds a predetermined voltage level, the comparison circuit (12) applies a high voltage (H) level maintenance signal to the base of the transistor (14). Other configurations are substantially the same as those of the conventional switching element protection circuit shown in FIG.
[0018] 動作の際に、図 2(A)に示すように、駆動回路 (9)からゲート直列抵抗 (8)を介して M OS_FET(4)の制御端子 (G)に付与される制御信号 Vが時刻 tにて低レ、電圧 (L)レべ  In operation, as shown in FIG. 2 (A), a control signal applied from the drive circuit (9) to the control terminal (G) of the MOS_FET (4) via the gate series resistor (8) V is low and voltage (L) level at time t
G 0  G 0
ノレから高い電圧 (H)レベルになると、 M〇S-FET(4)がオン状態となり、誘導性負荷 (2) に直流電源 (1)の電圧が印加され、誘導性負荷 (2)に流れる電流 Iが徐々に増加して 誘導性負荷 (2)にエネルギが蓄積される。誘導性負荷 (2)に印加される電圧は、電流 制限抵抗 (3)で直流電源 (1)の電圧を分圧した分だけ低下するので、誘導性負荷 (2)に 流れる電流 Iが制限される。これに伴い、 MOS_FET(4)に流れるドレイン電流 Iが図 し DWhen the voltage rises to the high voltage (H) level, the M〇S-FET (4) turns on, the voltage of the DC power supply (1) is applied to the inductive load (2), and flows to the inductive load (2) The current I gradually increases and energy is stored in the inductive load (2). The voltage applied to the inductive load (2) is Since the voltage of the DC power supply (1) is reduced by the limiting resistor (3), the current I flowing to the inductive load (2) is limited. Accordingly, the drain current I flowing through the MOS_FET (4) is
2(B)に示すように徐々に増加し、時刻 tにて電流制限抵抗 (3)で制限された電流値に The current gradually increases as shown in 2 (B) and reaches the current value limited by the current limiting resistor (3) at time t.
1  1
なると、次に M〇S_FET(4)がターンオフするまでの期間 Aだけその電流値を保持す る。  Then, the current value is held for the period A until the next time M〇S_FET (4) turns off.
[0019] 図 2(A)に示すように、 MOS-FET(4)の制御端子 (G)に付与される制御信号 Vが時  As shown in FIG. 2A, when the control signal V applied to the control terminal (G) of the MOS-FET (4)
G  G
亥 にて高い電圧 (H)レベルから低い電圧 (L)レベルになると、 MOS- FET(4)がター When the voltage changes from a high voltage (H) level to a low voltage (L) level, the MOS-FET (4)
2 2
ンオフし、誘導性負荷 (2)に逆起電圧が発生して蓄積されたエネルギが放出される。 これにより、 M〇S_FET(4)のターンオフ時に M〇S_FET(4)の第 1及び第 2の主端子 (D,S)間に過渡的な過電圧が発生して、図 2(C)に示すように MOS_FET(4)の第 1及 び第 2の主端子 (D，S)間の電圧 V が急激に上昇し、過電圧保護回路 (10)を構成する  The inductive load (2) is turned off to generate a back electromotive force, and the stored energy is released. As a result, a transient overvoltage occurs between the first and second main terminals (D, S) of the MFETS_FET (4) when the M〇S_FET (4) is turned off, as shown in FIG. 2 (C). The voltage V between the first and second main terminals (D, S) of the MOS_FET (4) rises rapidly, forming the overvoltage protection circuit (10).
DS  DS
アバランシェダイオード (5，6)の降伏電圧によりクランプされる。 MOS-FET(4)の第 1 及び第 2の主端子 (D，S)間に発生した過電圧がアバランシェダイオード (5,6)の降伏電 圧を超えると、アバランシェダイオード (5,6)がオン状態となり、過電圧保護回路 (10)に より MOS-FET(4)の制御端子 (G)に制御信号 (V )が付与され、制御端子 (G)の電圧  Clamped by the breakdown voltage of the avalanche diode (5, 6). When the overvoltage generated between the first and second main terminals (D, S) of the MOS-FET (4) exceeds the breakdown voltage of the avalanche diode (5, 6), the avalanche diode (5, 6) turns on. The control signal (V) is applied to the control terminal (G) of the MOS-FET (4) by the overvoltage protection circuit (10), and the voltage of the control terminal (G) is changed.
G  G
が一時的に上昇するため、ターンオフ状態の M〇S-FET(4)が一時的にオン状態と なる。これにより、誘導性負荷 (2)に蓄積されたエネルギが MOS-FET(4)の第 1又は 第 2の主端子 (D，S)を介して接地側に放出され、第 1及び第 2の主端子 (D，S)間に印加 される過電圧が安全なレベルに制限されるので、 MOS_FET(4)を過電圧力 保護 すること力 Sできる。これと共に、図 2(B)に示すように、 MOS_FET(4)に流れるドレイン 電流 Iは徐々に減少する力 MOS-FET(4)では第 1及び第 2の主端子 (D，S)間に印 Rises temporarily, and the M〇S-FET (4) in the turn-off state is temporarily turned on. As a result, the energy stored in the inductive load (2) is discharged to the ground side via the first or second main terminal (D, S) of the MOS-FET (4), and the first and second Since the overvoltage applied between the main terminals (D, S) is limited to a safe level, the MOS_FET (4) can be protected against overvoltage. At the same time, as shown in Fig. 2 (B), the drain current I flowing through the MOS_FET (4) gradually decreases. In the MOS-FET (4), the drain current I decreases between the first and second main terminals (D, S). mark
D D
加される過電圧 V とドレイン電流 Iとの積に等しい電力損失が発生するため、 M〇S  Since a power loss equal to the product of the applied overvoltage V and the drain current I occurs, M〇S
DS D  DS D
-FET(4)を構成する素子の温度が急激に上昇する。  -The temperature of the element constituting the FET (4) rises rapidly.
[0020] MOS-FET(4)を構成する素子の動作温度は、温度検出用サーミスタ (11)により電 圧レベルとして検出され、温度検出用サーミスタ (11)の検出電圧が時亥 にて所定の  [0020] The operating temperature of the element constituting the MOS-FET (4) is detected as a voltage level by a temperature detecting thermistor (11).
3 電圧レベルを超えると、比較回路 (12)から切換手段 (13)を構成するトランジスタ (14)の ベースに高レ、電圧 (H)レベルの保全信号が付与され、トランジスタ (14)がオン状態と なる。これにより、過電圧保護回路 (10)のアバランシェダイオード (6)が短絡され、過電 圧保護回路 (10)の検出電圧、即ち MOS-FET(4)の第 1の主端子 (D)と制御端子 (G)と の間の電圧が低下するため、図 2(C)に示すように M〇S-FET(4)の第 1及び第 2の主 端子 (D,S)間の電圧 V が短時間で低下するため、 MOS-FET(4)を安全動作領域（3 When the voltage level is exceeded, a high level, voltage (H) level maintenance signal is applied from the comparison circuit (12) to the base of the transistor (14) constituting the switching means (13), and the transistor (14) is turned on. And This short-circuits the avalanche diode (6) of the overvoltage protection circuit (10), As the detection voltage of the voltage protection circuit (10), that is, the voltage between the first main terminal (D) and the control terminal (G) of the MOS-FET (4) decreases, as shown in FIG. In addition, since the voltage V between the first and second main terminals (D, S) of the MFETS-FET (4) decreases in a short time, the MOS-FET (4)
S〇A)内での動作に切り換えることができる。一方、 M〇S_FET(4)に流れるドレイン 電流 Iは、図 2(B)に示すように引き続き徐々に減少し、誘導性負荷 (2)の蓄積エネル ギの放出が時刻 tにて完了すると、ドレイン電流 Iは略ゼロとなる。これと共に、図 2(The operation can be switched to within S〇A). On the other hand, the drain current I flowing through the M〇S_FET (4) gradually decreases as shown in Fig. 2 (B), and when the discharge of the stored energy of the inductive load (2) is completed at time t, The drain current I becomes almost zero. Fig. 2 (
C)に示すように MOS-FET(4)の第 1及び第 2の主端子 (D,S)間の電圧 V が時刻 tで の値から略 o[v]まで急激に降下する。 As shown in C), the voltage V between the first and second main terminals (D, S) of the MOS-FET (4) drops sharply from the value at time t to approximately o [v].
[0021] 図 2(B)及び (C)の破線部は、図 4に示す従来の回路の動作を示す。図 4に示す従 来の回路では、 MOS-FET(4)のターンオフ時に第 1及び第 2の主端子 (D，S)間に発 生する高い過電圧により誘導性負荷 (2)から蓄積エネルギが放出されるため、時刻 t よりも早い時刻 tで蓄積エネルギの放出が完了する。し力、しながら、過電圧保護回路2 (B) and 2 (C) show the operation of the conventional circuit shown in FIG. In the conventional circuit shown in Fig. 4, the stored energy from the inductive load (2) is generated by the high overvoltage generated between the first and second main terminals (D, S) when the MOS-FET (4) is turned off. Because of the release, the release of the stored energy is completed at time t earlier than time t . Power, while the overvoltage protection circuit
(10)により過電圧をクランプする期間 Bでの M〇S-FET(4)の動作温度が大きく上昇 するため、 M〇S-FET(4)の第 1及び第 2の主端子 (D，S)間の電圧 V とドレイン電流 I が動作温度の上昇により安全動作領域を超えると、 MOS-FET(4)が過熱により破壊 される。これに対して、図 1に示す第 1の実施の形態の回路では、誘導性負荷 (2)の蓄 積エネルギを放出する電圧 V が低いため、図 4に示す従来の回路よりも蓄積エネル ギの放出期間が長くなるが、 M〇S-FET(4)の第 1及び第 2の主端子 (D,S)間の電圧 V が低い分だけ M〇S-FET(4)で発生する電力損失が低減されるため、過電圧のク ランプ期間 B中に M〇S-FET(4)の動作温度の上昇も図 4に示す従来の回路に比較 して低く抑えられる。したがって、高温動作時に、 M〇S-FET(4)を過電圧から保護す ると共に、 M〇S-FET(4)の特性劣化や破壊を防止することができる。 Since the operating temperature of the M-S-FET (4) rises significantly during the overvoltage clamping period B due to (10), the first and second main terminals (D, S If the voltage V and the drain current I exceed the safe operating area due to the rise in operating temperature, the MOS-FET (4) will be destroyed by overheating. On the other hand, in the circuit according to the first embodiment shown in FIG. 1, since the voltage V at which the accumulated energy of the inductive load (2) is released is lower, the stored energy is lower than that of the conventional circuit shown in FIG. However, the power generated by the M〇S-FET (4) is reduced by the lower voltage V between the first and second main terminals (D, S) of the M〇S-FET (4). Since the loss is reduced, the operating temperature of the M〇S-FET (4) during the overvoltage clamp period B is also suppressed to be lower than in the conventional circuit shown in FIG. Therefore, at the time of high-temperature operation, the M〇S-FET (4) can be protected from overvoltage, and the characteristic deterioration and destruction of the M〇S-FET (4) can be prevented.
[0022] 第 1の実施の形態では、温度検出用サーミスタ (11)により MOS-FET(4)の動作温 度を検出し、その動作温度が所定のレベルを越えるときに、比較回路 (12)から切換手 段 (13)を構成するトランジスタ (14)のベースに高い電圧 (H)レベルの保全信号を付与 する。これにより、トランジスタ (14)がオン状態となり、過電圧保護回路 (10)を構成する 二ダイオード (5,6)の一方 (6)が短絡されるので、過電圧保護回路 (10) の検出電圧が低下し、 MOS-FET(4)の第 1及び第 2の主端子 (D，S)間の電圧 V が 低下するので、低下した安全動作領域内での動作に MOS_FET(4)を切り換えること ができる。したがって、 M〇S-FET(4)の高温動作時に、低下した電圧レベルで過電 圧保護回路 (10)がオン状態となり、 M〇S-FET(4)を一時的にターンオンさせるので、 高温動作時に誘導性負荷 (2)で発生する過電圧から MOS-FET(4)を保護することが できると共に、 MOS-FET(4)の電気的特性の劣化や破壊を防止することができる。 In the first embodiment, the operating temperature of the MOS-FET (4) is detected by the temperature detecting thermistor (11), and when the operating temperature exceeds a predetermined level, the comparison circuit (12) Then, a high voltage (H) level maintenance signal is applied to the base of the transistor (14) constituting the switching means (13). As a result, the transistor (14) is turned on, and one of the two diodes (5, 6) constituting the overvoltage protection circuit (10) is short-circuited, so that the detection voltage of the overvoltage protection circuit (10) decreases. Then, the voltage V between the first and second main terminals (D, S) of the MOS-FET (4) becomes Since it decreases, MOS_FET (4) can be switched to operation within the reduced safe operation area. Therefore, during high-temperature operation of the M と な り S-FET (4), the overvoltage protection circuit (10) is turned on at the reduced voltage level, and the M〇S-FET (4) is temporarily turned on. The MOS-FET (4) can be protected from overvoltage generated by the inductive load (2) during operation, and the electrical characteristics of the MOS-FET (4) can be prevented from being deteriorated or destroyed.
[0023] 図 1に示す第 1の実施の形態は変更が可能である。例えば、本発明の他の実施の 形態を示す第 2の実施の形態のスイッチング素子保護回路は、図 3に示すように、 M OS-FET(4)の第 1の主端子 (D)と制御端子 (G)との間に 2つのアバランシヱダイオード (5，6)を並列に接続して過電圧保護回路 (10)を構成し、 2つのトランジスタ (スィッチ手 段）（14a, 14b)を 2つのアバランシヱダイオード (5,6)の各々と直列に接続して切換手段 (13)を構成する。比較回路 (12)は、温度検出用サーミスタ (11)の検出電圧が所定の電 圧レベルよりも低いとき、 2つのトランジスタ (14a, 14b)の何れか一方のベースに高い電 圧 (H)レベルの保全信号を付与して何れか一方のトランジスタ (14a， 14b)を選択的に オン状態にし、温度検出用サーミスタ (11)の検出電圧が所定の電圧レベルを超えた ときに 2つのトランジスタ (14a, 14b)の各ベースに高い電圧 (H)レベルの保全信号を付 与して 2つのトランジスタ (14a,14b)を同時にオン状態にする。その他の構成は、図 1に 示す第 1の実施の形態におけるスイッチング素子保護回路と略同様である。  The first embodiment shown in FIG. 1 can be modified. For example, as shown in FIG. 3, a switching element protection circuit according to a second embodiment, which is another embodiment of the present invention, is connected to a first main terminal (D) of a MOS-FET (4). Two avalanche diodes (5, 6) are connected in parallel with the terminal (G) to form an overvoltage protection circuit (10), and two transistors (switch means) (14a, 14b) are connected to two terminals. The switching means (13) is constituted by connecting in series with each of the two avalanche diodes (5, 6). When the detection voltage of the temperature detection thermistor (11) is lower than a predetermined voltage level, the comparison circuit (12) outputs a high voltage (H) level to one of the bases of the two transistors (14a, 14b). The maintenance signal is applied to selectively turn on one of the transistors (14a, 14b). When the detection voltage of the temperature detection thermistor (11) exceeds a predetermined voltage level, the two transistors (14a, 14a) are turned on. , 14b), a high voltage (H) level maintenance signal is applied to each base to simultaneously turn on the two transistors (14a, 14b). Other configurations are substantially the same as those of the switching element protection circuit according to the first embodiment shown in FIG.
[0024] 第 2の実施の形態では、 M〇S-FET(4)の動作温度が上昇して温度検出用サーミ スタ (11)の検出電圧が所定の電圧レベルを超えると、比較回路 (12)により 2つのトラン ジスタ (14a，14b)が同時にオン状態となり、過電圧保護回路 (10)の検出電圧、即ち MO S-FET(4)の第 1の主端子 (D)及び制御端子 (G)間の電圧が低下し、 MOS-FET(4) の第 1及び第 2の主端子 (D,S)間の電圧 V が低下する。これにより、 MOS-FET(4)を 低下した安全動作領域（S〇A)内での動作に切り換えることができる。このため、図 3 に示す第 2の実施の形態でも図 1に示す第 1の実施の形態と同様に、 MOS-FET(4) の高温動作時に、低下した電圧レベルで過電圧保護回路 (10)がオン状態となり、 M OS-FET(4)を一時的にターンオンさせるので、誘導性負荷 (2)で発生する過電圧か ら MOS-FET(4)を保護できると共に、 M〇S_FET(4)の電気的特性の劣化や破壊を 防止できる。 本発明の実施態様は前記の 2つの第 1の実施の形態及び第 2の実施の形態に限 定されず、更に種々の変更が可能である。例えば、温度検出用サーミスタ (11)を MO S_FET(4)と同一の半導体基板上に取り付けてもよい。この場合、 MOS_FET(4)の 発熱部分と温度検出用サーミスタ等の温度検出手段 (11)との熱的な結合が密となる ため、 MOS-FET(4)の温度上昇を温度検出手段 (11)により迅速且つ正確に検出し て過熱保護回路を迅速且つ確実に動作させることができる。また、半導体基板に作り 付けの半導体素子の順方向電圧や逆漏れ電流等で温度を検出する温度検出手段 を設けてもよい。更に、複数の過電圧保護回路 (10)と、複数の温度検出用サーミスタ 等の温度検出手段 (11)と、複数のトランジスタ (14)とを設け、 MOS-FET(4)の温度又 は誘導性負荷 (2)に発生する過電圧の大きさに応じて複数のトランジスタ (14)を適宜 切り換えることにより過電圧保護回路 (10)の検出電圧を調整してもよい。この場合、 M OS-FET(4)の温度又は誘導性負荷 (2)に発生する過電圧の大きさに応じて過電圧 保護回路 (10)の検出電圧が調整されるので、 M〇S-FET(4)の周囲温度の変化や誘 導性負荷 (2)の変動に対応して過熱保護回路をきめ細力べ動作させることができる。ま た、第 2の実施の形態では 2つのトランジスタ (14a, 14b)を 2つのアバランシエダィォー ド (5,6)の各々と直列に接続して切換手段 (13)を構成するが、 2つのトランジスタ In the second embodiment, when the operating temperature of the M-S-FET (4) rises and the detection voltage of the temperature detection thermistor (11) exceeds a predetermined voltage level, the comparison circuit (12 ), The two transistors (14a, 14b) are simultaneously turned on, and the detection voltage of the overvoltage protection circuit (10), that is, the first main terminal (D) and the control terminal (G) of the MOS-FET (4) The voltage between the first and second main terminals (D, S) of the MOS-FET (4) decreases. As a result, the operation of the MOS-FET (4) can be switched to the operation within the lowered safe operation area (S〇A). Therefore, in the second embodiment shown in FIG. 3, as in the first embodiment shown in FIG. 1, when the MOS-FET (4) operates at a high temperature, the overvoltage protection circuit (10) Is turned on and the MOS-FET (4) is turned on temporarily, so that the MOS-FET (4) can be protected from the overvoltage generated by the inductive load (2) and the M〇S_FET (4) Deterioration and destruction of electrical characteristics can be prevented. Embodiments of the present invention are not limited to the above-described first and second embodiments, and various modifications are possible. For example, the temperature detection thermistor (11) may be mounted on the same semiconductor substrate as the MOS_FET (4). In this case, the thermal coupling between the heat-generating portion of the MOS_FET (4) and the temperature detecting means (11) such as a temperature detecting thermistor becomes tight, so that the temperature rise of the MOS-FET (4) is monitored by the temperature detecting means (11 ), The overheat protection circuit can be operated quickly and reliably by detecting quickly and accurately. Further, a temperature detecting means for detecting a temperature based on a forward voltage, a reverse leakage current or the like of a semiconductor element built in the semiconductor substrate may be provided. Furthermore, a plurality of overvoltage protection circuits (10), a plurality of temperature detecting means (11) such as a thermistor for temperature detection, and a plurality of transistors (14) are provided, and a temperature or inductive characteristic of the MOS-FET (4) is provided. The detection voltage of the overvoltage protection circuit (10) may be adjusted by appropriately switching the plurality of transistors (14) according to the magnitude of the overvoltage generated in the load (2). In this case, the detection voltage of the overvoltage protection circuit (10) is adjusted according to the temperature of the MOS-FET (4) or the magnitude of the overvoltage generated in the inductive load (2). The overheat protection circuit can be operated in a finely detailed manner in response to changes in the ambient temperature and fluctuations in the inductive load (2). In the second embodiment, the switching means (13) is configured by connecting two transistors (14a, 14b) in series with each of the two avalanche diodes (5, 6). The two transistors
(14a, 14b)の何れか一方を省略し、 MOS_FET(4)の動作温度が上昇して温度検出用 サーミスタ (11)の検出電圧が所定の電圧レベルを超えたとき、比較回路 (12)によりトラ ンジスタ (14)をオン状態にして MOS-FET(4)の第 1の主端子 (D)及び制御端子 (G)間 の電圧を低下させ、 MOS_FET(4)の第 1及び第 2の主端子 (D，S)間の電圧 V を低 One of (14a, 14b) is omitted, and when the operating temperature of the MOS_FET (4) rises and the detection voltage of the temperature detection thermistor (11) exceeds a predetermined voltage level, the comparison circuit (12) The transistor (14) is turned on to reduce the voltage between the first main terminal (D) and the control terminal (G) of the MOS-FET (4), and the first and second main terminals of the MOS_FET (4) are reduced. Low voltage V between terminals (D, S)
DS  DS
下させてもよい。また、第 1の実施の形態及び第 2の実施の形態では M〇S-FET(4) のソースから引き出された第 2の主端子 (S)を接地電位とした力 MOS-FET(4)のドレ インカ 引き出された第 1の主端子 (D)を接地電位としてもよい。また、上記の各第 1 の実施の形態及び第 2の実施の形態では複数のアバランシェ（雪崩）ダイオードを使 用して過電圧保護回路 (10)を構成したが、基準電源、比較器、抵抗及びトランジスタ スィッチ等を使用して過電圧保護回路 (10)を構成してもよい。更に、本発明は M〇S_ FET (MOS型電界効果トランジスタ）以外の自己消弧型スイッチング素子、例えば I GBT (絶縁ゲート型トランジスタ）又は SIT (静電誘導型トランジスタ）等にも適用が可 能である。 You may let it go down. In the first embodiment and the second embodiment, the power MOS-FET (4) in which the second main terminal (S) drawn from the source of the M-S-FET (4) is set to the ground potential is used. The first main terminal (D) drawn out may be set to the ground potential. In each of the first and second embodiments described above, the overvoltage protection circuit (10) is configured using a plurality of avalanche (avalanche) diodes. The overvoltage protection circuit (10) may be configured using a transistor switch or the like. Further, the present invention can be applied to a self-extinguishing type switching element other than M〇S_FET (MOS type field effect transistor), for example, IGBT (insulated gate type transistor) or SIT (static induction type transistor). Noh.
産業上の利用可能性 Industrial applicability
本発明は、高温環境下で使用されるスィッチング電源装置のスィッチング素子保護 回路及びソレノイド駆動装置に効果が顕著である。  The present invention has a remarkable effect on a switching element protection circuit and a solenoid driving device of a switching power supply device used in a high temperature environment.

Claims

請求の範囲 The scope of the claims
[1] 直流電源及び負荷に対して直列に接続された第 1及び第 2の主端子を有するスィ ツチング素子と、該スイッチング素子の制御端子に制御信号を付与し、前記スィッチ ング素子をオン'オフ制御させて前記直流電源から前記負荷に直流電力を供給する 駆動回路と、前記スイッチング素子の第 1及び第 2の主端子の一方と前記制御端子と の間に接続された過電圧保護手段とを備え、前記スイッチング素子のターンオフ時 に前記スイッチング素子の第 1及び第 2の主端子間に発生する電圧が所定のレベル を超えるとき、前記過電圧保護手段がオン状態となり、前記スイッチング素子の制御 端子に制御信号を付与して、前記スイッチング素子をターンオンさせるスイッチング 素子保護回路において、  [1] A switching element having first and second main terminals connected in series to a DC power supply and a load, and a control signal is applied to a control terminal of the switching element to turn on the switching element. A drive circuit for supplying DC power from the DC power supply to the load by performing off-control, and an overvoltage protection means connected between one of the first and second main terminals of the switching element and the control terminal. When the voltage generated between the first and second main terminals of the switching element when the switching element is turned off exceeds a predetermined level, the overvoltage protection means is turned on, and the control terminal of the switching element is In a switching element protection circuit for applying a control signal and turning on the switching element,
前記スイッチング素子の動作温度を検出する温度検出手段と、  Temperature detection means for detecting the operating temperature of the switching element,
該温度検出手段により検出した動作温度が所定のレベルを越えるときに保全信号 を発生する比較手段と、  Comparing means for generating a maintenance signal when the operating temperature detected by the temperature detecting means exceeds a predetermined level;
前記過電圧保護手段の検出電圧を設定する複数の電圧設定素子と前記スィッチ ング素子の制御端子との間に接続された切換手段とを備え、  Switching means connected between a plurality of voltage setting elements for setting a detection voltage of the overvoltage protection means and a control terminal of the switching element;
該切換手段は、前記比較手段の保全信号が発生したとき、前記過電圧保護手段 の検出電圧を低下させることを特徴とするスイッチング素子保護回路。  The switching element protection circuit, wherein the switching means reduces a detection voltage of the overvoltage protection means when a maintenance signal of the comparison means is generated.
[2] 前記負荷は、誘導性負荷であり、 [2] The load is an inductive load,
前記過電圧保護手段は、降伏特性を有する複数の定電圧素子を直列に接続して 構成され、  The overvoltage protection means is configured by connecting a plurality of constant voltage elements having breakdown characteristics in series,
前記切換手段は、前記複数の定電圧素子の一部と並列に接続され、前記比較手 段の保全信号によりオン状態となるスィッチ手段力 成る請求項 1に記載のスィッチ ング素子保護回路。  2. The switching element protection circuit according to claim 1, wherein said switching means is connected in parallel with a part of said plurality of constant voltage elements, and is a switching means which is turned on by a maintenance signal of said comparison means.
[3] 前記負荷は、誘導性負荷であり、 [3] The load is an inductive load,
前記過電圧検出手段は、降伏特性を有する複数の定電圧素子を並列に接続して 構成され、  The overvoltage detection means is configured by connecting a plurality of constant voltage elements having breakdown characteristics in parallel,
前記切換手段は、前記複数の定電圧素子の一部又は各々と直列に接続された少 なくとも一つのスィッチ手段から成り、 前記比較手段は、前記温度検出手段により検出した動作温度に応じて前記スイツ チ手段を選択的にオン状態にする請求項 1に記載のスイッチング素子保護回路。 The switching means comprises at least one switch means connected in series with a part or each of the plurality of constant voltage elements; 2. The switching element protection circuit according to claim 1, wherein said comparing means selectively turns on said switch means in accordance with an operating temperature detected by said temperature detecting means.
[4] 前記温度検出手段を前記スイッチング素子と同一の半導体基板上に取り付けた請 求項 1一 3の何れ力 4項に記載のスイッチング素子保護回路。 4. The switching element protection circuit according to claim 1, wherein said temperature detecting means is mounted on the same semiconductor substrate as said switching element.
[5] 少なくとも一つの前記過電圧保護手段と、少なくとも一つの前記温度検出手段と、 少なくとも一つの前記スィッチ手段とを設け、 [5] At least one of the overvoltage protection means, at least one of the temperature detection means, and at least one of the switch means,
前記スイッチング素子の動作温度又は前記負荷に発生する過電圧の大きさに応じ て前記スィッチ手段を切り換えることにより前記過電圧保護手段の検出電圧を調整 する請求項 1一 4の何れ力、 1項に記載のスイッチング素子保護回路。  The method according to any one of claims 1 to 4, wherein the detection voltage of the overvoltage protection means is adjusted by switching the switch means according to the operating temperature of the switching element or the magnitude of overvoltage generated in the load. Switching element protection circuit.
PCT/JP2004/007936 2003-09-10 2004-06-07 Switching element protective circuit WO2005027326A1 (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009030691A1 (en) * 2007-09-03 2009-03-12 Continental Automotive Gmbh Circuit arrangement for switching an inductive load
CN107516873A (en) * 2017-10-18 2017-12-26 新誉轨道交通科技有限公司 Inverter and inverter protection device
WO2018041971A1 (en) * 2016-09-01 2018-03-08 Valeo Siemens Eautomotive Germany Gmbh Controlling a semiconductor switch in a switched mode
EP3442019A4 (en) * 2016-04-06 2019-12-04 Shindengen Electric Manufacturing Co., Ltd. Power module
US20210304941A1 (en) * 2020-03-30 2021-09-30 Maxim Integrated Products, Inc. Systems and methods to safely discharge inductors without energy limitations
DE102021209514A1 (en) 2021-08-31 2023-03-02 Robert Bosch Gesellschaft mit beschränkter Haftung Method of operating a device and device

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008033138A1 (en) * 2008-07-15 2010-01-21 Continental Automotive Gmbh Circuit arrangement for switching inductive load for use in motor vehicle, has power transistor with load section between one connection and another connection and control port for controlling current by load section
JP2011024382A (en) * 2009-07-17 2011-02-03 Fuji Electric Systems Co Ltd Gate drive circuit
DE102014112760A1 (en) 2013-09-20 2015-03-26 Maxim Integrated Products, Inc. Systems and methods for discharging inductors with temperature protection
CN104615093B (en) * 2013-10-28 2018-04-20 费希尔控制国际公司 Essential safety voltage clamp equipment
JP6749184B2 (en) * 2016-09-01 2020-09-02 日立オートモティブシステムズ株式会社 Semiconductor device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06295591A (en) * 1993-04-06 1994-10-21 Citizen Watch Co Ltd Semiconductor integrated circuit device
US5465190A (en) * 1992-07-16 1995-11-07 Sgs-Thomson Microelectronics S.A. Circuit and method for protecting power components against forward overvoltages
EP0749208A2 (en) * 1995-06-15 1996-12-18 AT&T IPM Corp. Field effect transistor protection circuit
JPH09163583A (en) * 1995-11-30 1997-06-20 Mitsubishi Electric Corp Protective circuit for semiconductor device
JP2002119044A (en) * 2000-10-12 2002-04-19 Fuji Electric Co Ltd Gate driving circuit for power semiconductor device
JP2002151989A (en) * 2000-11-14 2002-05-24 Toyota Industries Corp Clamp circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5465190A (en) * 1992-07-16 1995-11-07 Sgs-Thomson Microelectronics S.A. Circuit and method for protecting power components against forward overvoltages
JPH06295591A (en) * 1993-04-06 1994-10-21 Citizen Watch Co Ltd Semiconductor integrated circuit device
EP0749208A2 (en) * 1995-06-15 1996-12-18 AT&T IPM Corp. Field effect transistor protection circuit
JPH09163583A (en) * 1995-11-30 1997-06-20 Mitsubishi Electric Corp Protective circuit for semiconductor device
JP2002119044A (en) * 2000-10-12 2002-04-19 Fuji Electric Co Ltd Gate driving circuit for power semiconductor device
JP2002151989A (en) * 2000-11-14 2002-05-24 Toyota Industries Corp Clamp circuit

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009030691A1 (en) * 2007-09-03 2009-03-12 Continental Automotive Gmbh Circuit arrangement for switching an inductive load
EP3442019A4 (en) * 2016-04-06 2019-12-04 Shindengen Electric Manufacturing Co., Ltd. Power module
WO2018041971A1 (en) * 2016-09-01 2018-03-08 Valeo Siemens Eautomotive Germany Gmbh Controlling a semiconductor switch in a switched mode
CN109792241A (en) * 2016-09-01 2019-05-21 法雷奥西门子新能源汽车(德国)有限公司 Running semiconductor switch is being connected in control
CN107516873A (en) * 2017-10-18 2017-12-26 新誉轨道交通科技有限公司 Inverter and inverter protection device
US20210304941A1 (en) * 2020-03-30 2021-09-30 Maxim Integrated Products, Inc. Systems and methods to safely discharge inductors without energy limitations
US11676752B2 (en) * 2020-03-30 2023-06-13 Maxim Integrated Products, Inc. Systems and methods to safely discharge inductors without energy limitations
DE102021209514A1 (en) 2021-08-31 2023-03-02 Robert Bosch Gesellschaft mit beschränkter Haftung Method of operating a device and device

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