WO2005022393A1 - 不揮発性記憶装置及びその書込み方法 - Google Patents
不揮発性記憶装置及びその書込み方法 Download PDFInfo
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- WO2005022393A1 WO2005022393A1 PCT/JP2004/012714 JP2004012714W WO2005022393A1 WO 2005022393 A1 WO2005022393 A1 WO 2005022393A1 JP 2004012714 W JP2004012714 W JP 2004012714W WO 2005022393 A1 WO2005022393 A1 WO 2005022393A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
Definitions
- the present invention relates to a nonvolatile storage device having a rewritable nonvolatile memory and a writing method thereof.
- NAND flash memory which is a non-volatile memory mainly used for such memory cards, uses 16 KB as an erase unit. For this reason, external host devices that use memory cards use a size of 16 KB as a unit for writing.
- FIG. 1 is a diagram showing a conventional memory card 100, in which a controller 101 and flash memories FM0 to FM3, which are nonvolatile memories, are provided.
- Each of the flash memories FM0 to FM3 has a capacity of, for example, 128 MB, and constitutes a 500 MB memory card as an effective data area.
- the controller 1101 has a CPU 111, a temporary memory with a capacity of 2 KB.
- the flash memories FM0 to FM3 each have a capacity of 128 MB.
- each of the flash memories FM0 to FM3 is composed of 102 physical blocks (PB0 to PB1023) each having a capacity of 128 KB.
- the total capacity of the nonvolatile memory of the memory card 100 becomes 512 MB.
- the capacity that the host device 102 can use as a data area is 500 MB.
- the physical block is composed of 64 physical pages P P0 to P P 63. As shown in Fig. 3, each physical page consists of a data area with a capacity of 2 KB and a management area with a capacity of 64 B.
- the memory card 100 has a memory capacity of 500 MB when viewed from the external host device 102, and a logical address is allocated by a logical map as shown in FIG. That is, the data area of 500 MB is divided into 40000 logical blocks (LB) from the logical block LB0 to the logical block LB3999, and each logical block has a capacity of 128 KB. This logical block address corresponds to the address specified by the host device.
- LB logical blocks
- the address conversion table 114 shown in FIG. 1 specifies a flash memory and a physical block in the flash memory when a logical address indicating a logical group is given.
- the first two bits are bits that indicate one of the flash memories FM0 to FM3, and the following 10 bits are bits that indicate which physical block in the flash memory.
- the entry table 115 is a table composed of 1-pit configuration flags corresponding to 4096 physical blocks. The This flag is set to 1 if it has been erased, and 0 if it has been written.
- LBA logical block address
- LPA logical page address
- the physical block PB is specified from the address conversion table 114 based on the logical block address, and this is set as the read source physical block. Then, the data of the logical address of the read source physical block is read and transferred to the host device 102 via the data transfer buffer 113. Then, it is checked whether or not the reading has been completed, and if not, it is checked whether or not the logical page address is the last in the block.
- the logical page address is incremented and the same processing is repeated. If the logical page address is the last in the block, the logical page address is set to 0, the logical block address is incremented, and the same processing is repeated. In this way, data can be read from the specified logical address.
- step S301 of the logical address LA from the host device 102, the address in units of 128 KB is set as a logical block address (LAB), and the address Divide the sub-unit addresses into logical page addresses (LPAs).
- step S302 the entry table is searched, and an erased physical block is obtained as a write destination physical block (PB). Then, the corresponding bit of the entry table 1 15 is updated to “0” which has been written.
- step S303 to check whether or not the logical page address LPA is 0. If the logical page address LPA is not 0, the former half wrapping process to be described later is performed (step S304).
- step S305 the write data from the host device 102 is transferred to the flash memory via the page buffer. And writes to the logical page address of the write destination physical block. At this time, management information for writing to the management area is also written at the same time.
- step S306 it is checked whether the writing has been completed. If not, in step S307, it is checked whether the logical page address (LPA) is the last in the block. If not, the logical page address LPA is incremented in step S308, and the process returns to step S305.
- LPA logical page address
- step S309 If the logical base address is the last block, erasure and table update are performed in step S309, the logical page address LPA is incremented to 0 in step S310, and the logical block address LBA is incremented. Return to 0 2.
- step S311 it is checked in step S311 whether the logical base address is the last in the block. If it is not the last, the latter half of the wrapping process is performed in step S312, and if it is the last in the block, the process proceeds to step S313 without performing this process, and the erasure and table update are performed. Finish.
- the present invention has been made in view of such a conventional problem, and enables writing at a high speed by reducing the unit of writing, and consolidates the written data.
- the purpose of this is to secure an erased block and make it easy to perform the next write in the secured erased area. Disclosure of the invention
- the present invention provides a nonvolatile memory, comprising: a nonvolatile memory; a controller; and writing and reading data to and from the nonvolatile memory based on a logical address given from the outside.
- the nonvolatile memory is composed of a plurality of physical blocks, each of the physical blocks is composed of a plurality of partial physical blocks, and a series of logical group addresses and each logical group is externally provided.
- a logical address including a series of logical block addresses belonging to the logical group address is assigned to the logical block address of the logical block to which the logical block to which the logical group belongs is recorded.
- an address conversion table that has a duplicate address registration area that indicates the physical block address that is recorded in duplicate, and indicates whether each physical block has been written or erased
- the data is written in an unwritten area in units of partial physical blocks, and Register the write destination physical block address for the logical group to which the logical block belongs in the address conversion area of the address conversion table, and If another physical block address has already been registered in the dress conversion area, the physical block address is registered in the duplicate address registration area.
- the writing unit at the time of data writing is the same as the data writing unit used in the host device, and the erasing unit of the non-volatile memory in the memory card has a large capacity. Therefore, even when the data is expanded by the integration, data writing from the external host device can be performed in a short time. Further, even when a part of the write area is used, an effect is obtained that a writable area can be formed by performing the process of securing the erased block.
- FIG. 1 is a diagram showing a configuration of a conventional nonvolatile memory.
- FIG. 2 is a diagram showing the configuration of a conventional flash memory and its physical block.
- FIG. 3 is a diagram showing a configuration of a logical page written in a conventional physical block.
- FIG. 4 is a diagram showing a configuration of a conventional logic block.
- FIG. 5 is a schematic diagram showing an operation at the time of reading data from a conventional nonvolatile memory.
- FIG. 6 is a flowchart showing a data writing process of a conventional nonvolatile memory device.
- FIG. 7 is a schematic diagram showing an operation at the time of conventional data writing.
- FIG. 8 is a block diagram showing an entire configuration of the nonvolatile memory device according to Embodiment 1 of the present invention.
- FIG. 9 is a diagram showing a configuration of a flash memory and a physical block thereof according to the first embodiment.
- FIG. 10 is a diagram showing a configuration of a logical group according to the first embodiment.
- FIG. 11 is a diagram showing a configuration of an address conversion table according to the first embodiment.
- FIG. 12 is a diagram showing a configuration of a logical page in a physical page according to the first embodiment.
- FIG. 13 is a flowchart showing a table initialization process according to the first embodiment.
- FIG. 14 is a flowchart showing a process of registering an address conversion table according to the first embodiment.
- FIG. 15 is a flow chart showing a process of correcting the address conversion table according to the first embodiment.
- FIG. 16 is a flowchart showing a data reading process according to the first embodiment.
- FIG. 17 is a schematic diagram showing an operation of a data read process according to the first embodiment.
- FIG. 18 is a flowchart showing a data write process (part 1) according to the first embodiment.
- FIG. 19 is a flowchart showing a data write process (part 2) according to the first embodiment.
- FIG. 20 is a flowchart showing a duplicate address registration process according to the first embodiment.
- FIG. 21 is a flowchart showing an erase block securing process according to the first embodiment.
- FIG. 22 is a diagram showing a first example before performing an erase block securing process according to the first embodiment.
- FIG. 23 is a diagram showing a state after an erase block securing process of the first example according to the first embodiment.
- FIG. 24 shows a second example before performing the erase block securing process according to the first embodiment.
- FIG. 25 is a diagram showing a state after an erase block securing process of a second example according to the first embodiment.
- FIG. 26 is a flowchart showing the first half wrapping process according to the first embodiment.
- FIG. 27 is a flowchart showing the latter half wrapping process according to the first embodiment.
- FIG. 28 is a flowchart showing erasure and table update processing according to the first embodiment.
- FIG. 29 is a schematic diagram showing the operation of the data write processing according to the first embodiment.
- FIG. 30 is a diagram showing a configuration of a logical group according to the second embodiment of the present invention.
- FIG. 8 is a block diagram showing a configuration of a memory card according to Embodiment 1 of the present invention.
- the memory card 1 includes a controller 2 and a nonvolatile memory, for example, flash memories FM0 to FM3 having a capacity of 128 MB.
- the controller 2 has a CPU 11 and a temporary save buffer 12 with a capacity of 2 KB, a data transfer buffer 13 with a capacity of 512 bytes, and a 15-bit 4-KWord configuration, that is, a capacity of 7.5 KB.
- an entry table 15 having a capacity of 5 12 B, ie, a configuration of 4 K words in one pit.
- the flash memories FM0 to FM3 each have a capacity of 128 MB.
- each flash memory FM0-FM3 has 1,024 physical blocks (128 KB each).
- the total data capacity of the non-volatile memory of the memory card 1 is 512 MB, of which 500 MB can be used from outside as a temporary storage area.
- the physical block is composed of 64 physical pages PP0 to PP63.
- P P0 to P P7 be partial physical blocks P P B 0. That is, each physical block P Bi consists of eight partial physical blocks.
- the partial physical block PPB has the same size as a logical block described later, and is an area in which data of the logical block is written.
- the physical page is the unit of data writing.
- the memory card 1 has a memory capacity of 500 MB as viewed from the external host device 3, and a logical address is allocated by a logical map as shown in FIG. That is, the 500 MB data area is divided into 4000 logical groups (LG) from logical group LG 0 to logical group LG 3999, and each logical group has a data capacity of 128 KB. Each logical group is divided into eight logical blocks (LBs) of 16 KB data capacity units. The logical blocks LB are assigned a series of numbers from LG 0 to LG 3 1999 as shown. This logical address corresponds to the address specified by the host device. Data of different logical groups are always arranged in partial physical blocks included in physically different erase units (physical blocks). Each logical block is allocated to one partial physical block.
- LG logical groups
- LBs logical blocks
- FIG. 11 is a block diagram showing the address conversion table 14. As shown in FIG. As shown in this figure, when a logical address indicating a logical group is given, the address conversion table 14 is a 15-bit address conversion area AC that specifies a flash memory, a physical block therein, and a partial physical block therein. R 14a is provided.
- the first two bits indicate which of the flash memories FM0 to FM3, the next 10 bits indicate which physical block PB in the flash memory, and the next three bits indicate which physical block PB in the flash memory.
- Partial physical block This bit indicates whether it is a PPB.
- a duplicate address registration area O ARR 14b is provided in a part of the free area other than the address conversion area 14a of the address conversion table 14. Since the data of a certain logical group may be recorded across multiple physical blocks, it is registered in the duplicate address registration area 14b at that time.
- the overlapping address registration area 14> has 16 areas, and each area is made up of an overlapping partial physical block address OPPBA 15 bits and an overlapping logical group address OLGA 12 bits.
- the invalid value of the duplicate physical block address is set to 0. Since the partial physical block P PB 0 included in the first physical block PB 0 of the flash memory FM0 is scheduled as an area for writing fixed data, valid values that can be taken as overlapping partial physical block addresses are 8 to 32767. is there. The invalid value of the duplicate logical address is 4095. Possible values for the duplicate logical address are logical groups 0 to 3999 that can be specified by the external host device 3. After the processing of the address conversion table correction flow described later is completed, the lower 3 bits of the overlapping physical block address of the overlapping address registration area 14b are all set to 1.
- FIG. 12 shows the configuration of a logical page written to each physical page.
- the logical page consists of 24 bytes of the block management area BMR, followed by the sector data area SDR 5 12 bytes and the sector management area SMR 8 bytes, which are alternately continuous. Area PMR 8 bytes are provided.
- Section data area There are four SDRs, making up a data area of 2 Kbytes in total.
- a logical block address LBA a logical block address LBA
- an address table AT indicates the addresses of the partial physical blocks in which the eight logical blocks included in the logical group to which this logical block belongs are written. This content is the same for each logical page belonging to the same logical block. Since the address table is represented by 15 bits each, for example, the 16th bit can be used to determine whether or not this logical page has been erased.
- the ring counter is a counter for determining whether the address table is new or old, and is incremented each time the address table is updated.
- the entry table 15 shown in FIG. 8 is a table composed of 1-bit flags corresponding to the physical blocks of 4096. This flag is set to 1 if it has been erased, and 0 if it has been written.
- the CPU 11 of the controller 2 refers to the overlapping address registration area 14 b of the address conversion table 14 when there is no available space for registration in the overlapping address conversion area, and is recorded in multiple physical blocks in an overlapping manner. It has a function of an erasure block securing unit that secures an erasure block by aggregating the data of the logical group into the physical block for any of the physical blocks.
- the erase block securing means may secure an erase block when there is no physical block in which all the partial physical blocks have been erased. Good.
- the initialization process is a process for creating the address conversion table 14 and the entry template 15 according to the state of the nonvolatile memory after the power is turned on.
- all data in the entry table 15 is set to 0 in step S11.
- all data in the address conversion table 14 is set as an invalid address.
- the invalid address is 0.
- Valid addresses are 8 to 3 2 7 6 7.
- the pointer of the flash memory FM is set to 0 (step S13), and the pointer of the physical block PB is set to 0 in step S14.
- step S15 the logical block address is read from the management area of page 0 of the physical block specified, and whether or not the block has been erased is checked.
- step S19 it is checked whether or not the block is the last physical block. If the block is not the last physical block, the pointer of the physical block is incremented in step S20, and the process returns to step S15. If it is the last physical block in step S19, the flow advances to step S21 to check whether the block is the last flash memory. If it is not the last flash memory, the pointer of the flash memory is incremented in step S22, and the process returns to step S14. If it is the last flash memory in step S21, the process proceeds to step S23 to correct the address conversion table described later and finish the process.
- step S18 registration in the address translation table 14 in step S18 will be described with reference to the flowchart in FIG.
- the table offset page TOP
- step S32 the logical block address of the management area of the table offset page of the physical block is read. You. Then, in step S33, it is checked whether or not this page has been erased. If the page has been erased, the table offset page TOP is set to 18 (step S34), and the process returns to step S32. If the data has not been erased, the flow advances to step S35 to read the value of the address conversion table corresponding to the logical group address read from the table offset page of the physical block.
- step S36 it is determined whether the data of the address conversion table corresponding to the logical address read in step S36 is registered or unregistered. If this is an invalid address 0, it is determined that no registration has been made. Then, in step S37, the address of the partial physical block to be read is registered at a position corresponding to the logical group address belonging to the logical block address read from the conversion area 14a of the address conversion table 14. I do. If a valid address has been registered in step S36, the process proceeds from step S36 to S38. Then, the address of the partial physical block to be read and the value of the logical address LGA read from the physical block management area are registered in the overlapping address registration area 14 b of the address conversion table 14.
- Correction processing of the address conversion table means that when data of a logical block belonging to the same logical group is discretely arranged in a plurality of physical blocks, the address of the newly written partial physical block is converted to the address conversion area 1.
- the old write partial physical block is modified to be registered in the duplicate address registration area 14b.
- step S41 the value of i is set to 0, and in step S42, the i-th logical group address LGA and the partial physical block address PPBA of the overlapping address registration area 14b of the address conversion table 14 are obtained. . Then, in step S43, it is determined whether or not this is a valid value.
- step S44 If it is a valid value, the flow advances to step S44 to read the management area of an arbitrary page of the i-th partial physical block and obtain a ring counter value. Then, in step S45, i Address conversion area of address conversion table 1 4 based on logical address
- step S46 Get the address of the corresponding partial physical block from a. Further, in step S46, the management area of the partial physical block address corresponding to the i-th logical address is read to obtain a ring counter value. Then, in step S47, it is determined based on the ring counter value whether the table of the duplicate address registration area is newer. If this is new, the i-th partial physical block is replaced with the partial physical block address corresponding to the i-th logical address in step S48. On the other hand, if the table is not new in step S47, the process proceeds to step S49 without checking this, and checks whether or not the pointer i is 15; otherwise, i is incremented (step S47).
- step S51 of the logical addresses from the host device 3, the 128 KB unit address is the logical group address LGA, the 16 KB unit address is the logical block address LBA, and the address less than 16 KB is logical. Page address LPA.
- step S52 the partial physical block obtained from the address translation table 14 based on the logical group address is set as a table partial physical block TPPB.
- step S53 the address table of an arbitrary page of the table partial physical block is read, and the partial physical block in which the data of the logical block address is written is set as the read source partial physical block.
- step S54 the data of the logical page address of the read source partial physical block is read and transferred to the host device 3 via the data transfer buffer 13. Then, it is checked whether or not the reading has been completed in step S55, and if not, it is checked in step S56 whether or not the logical page address is the last in the block. If not the last —The address LPA is incremented (step S57), and the process returns to step S54 to repeat the same processing.
- step S58 If the logical page address is the last in the block, it is checked in step S58 whether the logical block address is the last in the logical group. If not, the logical page address is set to 0, and the logical block address is incremented (step S59). Then, returning to step S54, the same processing is repeated. If the logical block address is the last in the logical group, the process proceeds to step S60, where the logical page address is set to 0, the logical block address and the logical group address are incremented, and the process returns to step S52. In this way, data can be read from the specified logical page address.
- step S61 of the logical addresses from the host device 3, the address in units of 128 KB is converted to the logical double address LGA, and the address in units of 16 KB is converted to the logical block address LBA. Addresses smaller than 16 KB are logical page addresses LPA.
- step S62 a partial physical block obtained from the address conversion table based on the logical group address is set as a table partial physical block TPPB. Then, the process proceeds to step S63 to read and hold the address table of an arbitrary page of the table partial physical block. Then, the process proceeds to step S64 to check whether the address of the table partial physical block is the last partial physical block in the physical block PB. If not the last partial physical block, step
- step S65 the partial physical block next to the address of the table partial physical block is set as the write destination partial physical block PPB.
- a duplicate address registration process described later is performed in step S66.
- step S67 the entry table 15 is searched to obtain an erased physical block, and the first partial physical block is set as a write destination partial physical block PPB.
- the entry table This bit of the physical block is updated to “0”.
- step S68 the address corresponding to the logical block address of the address table is held as the read source partial physical block.
- step S69 it is checked whether or not the address table has a partial physical block belonging to the same physical block as the partial physical block to be read. This detects whether or not the partial physical block is the last partial physical block. If this does not exist, the partial physical block belonging to the same physical block as the partial physical block to be read may be erased in step S70, and this is retained as the physical block to be erased. If there is no corresponding partial physical block in step S69, the process proceeds to step S71 without performing step S70, and the controller corresponds to the logical block address in the address table inside the controller. Replace the address to be used with the write destination partial physical block.
- step S73 it is checked whether or not the logical base address LPA is 0, and if it is not 0, the first half winding process is performed as described later (step S73). If the logical page address is 0, the process proceeds to step S74 without performing this processing, and the write data from the host device 3 is transferred to the flash memory via the data transfer buffer 13. Then, the data is written to the logical page address of the write destination partial physical block. At this time, the management information to be written to the management area is also written at the same time. Then, it is checked in step S75 whether or not the writing has been completed, and if not, it is checked in step S76 whether or not the logical page address is the last page in the logical block.
- step S77 If not, the logical page address is incremented in step S77, and the flow returns to step S74. If it is the last page in the logical block, erasure and table updating are performed in step S78. Next, in step S79, it is checked whether the logical block address is the last in the logical group. If not, the logical page address is set to 0 in step S80, and the logical Increment the address. Next, in step S81, the address of the write destination partial physical block is entered in the table partial physical block. Then, the flow returns to step S64 in FIG. 18 to repeat the same processing.
- step S79 If the logical block address is the last in the logical group in step S79, the logical page address is incremented to 0, the logical block address and the logical duplication address are incremented in step S82, and the process proceeds to step S62. Return. Then, when the write processing is completed in step S75, it is checked in step S83 whether the logical address is the last in the logical block. If not final, the latter half wrapping process is performed in step S84. If the logical page address is the last in the block, erasure and table updating are performed in step S85, and the processing is terminated.
- step S66 the duplicate address registration processing in step S66 will be described with reference to FIG.
- the registration status of the duplicate address registration area is checked in step S91. Then, it is determined whether or not there is a free area. If there is no free area, a process of securing an erase block, which will be described later, is performed (step S93). If there is an empty area, in step S94, the table partial physical block is written to the overlapping partial physical block address of the empty registration area of the overlapping address registration area, and the logical group address is written to the overlapping logical group address.
- step S101 the effective address of the duplicated address registration area 14b is searched to obtain a set of duplicated physical block addresses and duplicated logical duplicate addresses. Then, these are set as a resolved partial physical block address and a resolved logical group address.
- step S102 a corresponding partial physical block address is obtained from the address conversion area of the address conversion table based on the resolution logical drop address, and is set as a resolution table partial physical block (resolution TPPB).
- step S103 the address tape is read from any page of the physical table block in the resolution table. Read the file.
- step S104 it is checked whether all the partial physical blocks that have already been written among the physical blocks belonging to the resolution table partial physical block have been written in the address table. This process determines whether all valid data can be collected in the physical block to which the partial physical block in the resolution table belongs. If this is YES, in step S105, the partial physical block next to the partial physical block of the resolution table is set as the partial physical block of the resolution write destination. If “NO” in the step S 104, the process proceeds to a step S 106 to write all data to a new physical block. That is, the entry table is searched to obtain an erased physical block. Then, the leading partial physical block is set as the resolution write destination partial physical block.
- step S107 data not in the physical block to which the physical block to be resolved belongs in the address table is sequentially copied to the physical block to be resolved and written. You. At that time, the address table and the address conversion area of the address conversion table are also updated sequentially.
- step S108 the process proceeds to step S108, in which the data of the physical block to which the duplicated physical block belonging to the set having the duplicated group address that matches the resolution logical drop address in the duplicated address registration area belongs is deleted, and the duplicated address is deleted. Invalidate the partial physical block address OPPB and the duplicate group address 0 GA. This is to eliminate duplication, since duplication may occur over three or more physical blocks.
- step S109 the data corresponding to the overlapping partial physical block address of the entry table is updated to the erased state in response to the erasure, and the process ends.
- FIG. FIG. 22 shows an example of physical blocks PB100 and PB101 before an erase block is secured.
- the physical block PB 100 has PPB 800 to 807 as a partial physical block
- the physical block PB101 has partial physical blocks PBB808 to 815.
- the data of the logical blocks LB 0 to 7 of the logical group LG 0 is written to the physical block PB 100 once, and then the logical blocks LB 0 to 6 of the logical group LG 0 are updated and the physical blocks PB 101 Written in the partial physical block PPB 808 to 814.
- FIG. 22 also shows the state of the address conversion table 14 and the entry table 15 before securing the erase block.
- the most recently stored partial physical block PPB 814 of the logical group LG 0 is registered.
- the duplicate address registration area 14b a duplicate physical block PPB 807 and a duplicate logical group LG0 are registered. This indicates that the partial logical block PPB 807 in the physical block PB 100 records valid logical group LG0 and logical block LB7 data.
- step S104 by writing the data of the logical group LG0 and the logical block LB7 to the partial physical block PPB 815, all data is collected in the physical block PB101 as shown in step S104. be able to.
- step S104 by making the resolution table partial physical block the next partial physical block of the resolution table partial physical block (step S104), that is, in this example, by making it the partial physical block 815, as shown in FIG. Then, the data of the logical drop LG0 and the data of the logical block LB7 can be written to the partial physical block PB815, and all the data of the logical group LGO can be collected in the physical block PB101. In this case, all the physical blocks PB100 are erased and unwritten, and new data can be written. Entry table 15 indicates that physical block PB100 is set to “1” and can be written. are doing.
- FIG. 24 Another example of securing an erase block will be described with reference to FIGS. 24 and 25.
- the logical blocks LB0 to LB7 of the logical group LG0 are written in the physical block PB100, and thereafter, the physical blocks PPB808 to 811, which are part of the physical block PB101. 3, the logical blocks LB0 to LB5 of the logical group LG0 are written.
- the partial physical blocks PB800 to 805 of the physical block PB100 are invalid.
- the logical block LB0 of the logical group LGO is written to the partial physical block PPB814 of the physical block PB101, indicating that the data of the partial physical block PPB808 is invalidated.
- step S104 valid data cannot be collected in the physical block PB101 belonging to the partial physical block in the resolution table. That is, in step S104 of FIG. 21, there is shown a case where, among the physical blocks to which the partial physical blocks of the resolution table belong, all of the partial physical blocks which have already been written are not written in the address table. Therefore, in step S106, the entry table 15 is searched to obtain an erased physical block. In this case, the physical block PB102 is obtained, and all data is written in this physical block.
- FIG. 25 shows a state in which all data has been written in this way. In this case, the physical blocks PB100, 101 are erased, and the flag of the entry table 15 becomes 1, indicating a state in which new data can be written.
- step S111 the entangled page address is set to 0.
- step S 1 1 2 Reads the data of the involved page address of the read source partial physical block into the temporary save buffer 12.
- step S 1 1 2 Reads the data of the involved page address of the read source partial physical block into the temporary save buffer 12.
- the data is transferred to the flash memory, and written in the winding page address of the writing destination physical block.
- the management information to be written to the management area is also written at the same time.
- step S113 the wrapped page address is incremented.
- step S114 it is checked whether the wrapped page address matches the logical page address. If they do not match, return to step S112 and repeat the same process. If they match, the first half winding process ends.
- step S1221 the logical page address + 1 is set as the wrapping page address.
- step S 122 the data of the wraparound gate address of the read source physical block is read out to the temporary save buffer 12. Then, the data is transferred to the flash memory, and written to the winding page address of the physical block to be written. At this time, the management information to be written into the management area is also written at the same time. Then, the process proceeds to step S123 to check whether the winding page address is the last page address.
- step S124 the wrapped page address is incremented and the process returns to step S122. If the wrap page address is the last page, the latter half wrap process is completed. In this way, unlike the conventional example, the wrapping process is performed in units of pages, and the write management unit of the flash memory is set to 16 KB, thereby shortening the wrapping process time.
- step S131 it is checked whether or not there is a valid value in the block to be deleted. If there is a valid value, the physical block to be erased is erased in step S132.
- step S133 the weight of the address conversion table is determined. Invalidate the overlapping part physical block address and the overlapping logical group address corresponding to the physical block erased by this writing in the multiple address registration area.
- step S134 the data corresponding to the physical block to be deleted in the entry table is updated to "deleted".
- step S135 the data of the logical group address in the address conversion table is rewritten to the write destination partial physical block. If there is no valid value in the physical block to be erased in step S131, the process ends in step S135 without performing the process up to step S134.
- FIG. 29 shows an example in which 16 KB data provided from the host device is written to the write destination physical block via the data transfer buffer 13 by performing such processing.
- the host device 3 gives 16 KB data as a write unit, the data is written to any of the partial physical blocks in the write destination physical block.
- the other partial physical blocks of this write destination physical block are maintained in their original state, that is, they remain erased.
- 16 KB data is newly given as write data from the host device, new data is written to another partial physical block. Other areas of the physical block are kept as is.
- the logical blocks are given a series of logical block numbers from 0 to 319999 as in the first embodiment.
- the logical group that is expected to be biased in access is 128 KB larger in the size of the allocated physical block than the logical group size of 16 KB. The speed can be prevented from dropping.
- the present invention relates to a nonvolatile memory device having a rewritable nonvolatile memory and a writing method thereof, and can increase the writing speed as compared with the conventional example even when the capacity is increased. Therefore, it can be used for various applications of nonvolatile memories that require large-capacity, high-speed writing.
Abstract
Description
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JP2005513535A JP4667243B2 (ja) | 2003-08-29 | 2004-08-26 | 不揮発性記憶装置及びその書込み方法 |
US10/569,880 US7987314B2 (en) | 2003-08-29 | 2004-08-26 | Non-volatile memory device and write method thereof |
EP04772668A EP1659497A4 (en) | 2003-08-29 | 2004-08-26 | NON-VOLATILE MEMORY BLOCK AND WRITING PROCESS THEREFOR |
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JP2003306160 | 2003-08-29 |
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US (1) | US7987314B2 (ja) |
EP (1) | EP1659497A4 (ja) |
JP (1) | JP4667243B2 (ja) |
CN (1) | CN100511181C (ja) |
TW (1) | TW200511012A (ja) |
WO (1) | WO2005022393A1 (ja) |
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JP2007233838A (ja) * | 2006-03-02 | 2007-09-13 | Toshiba Corp | メモリシステムの制御方法 |
EP1895418A4 (en) * | 2005-12-09 | 2008-08-27 | Matsushita Electric Ind Co Ltd | NON-VOLATILE MEMORY DEVICE AND METHOD FOR WRITEING AND READING DATA |
CN101484882A (zh) * | 2005-12-09 | 2009-07-15 | 晟碟以色列有限公司 | 闪存管理方法 |
KR101247574B1 (ko) | 2007-12-24 | 2013-03-26 | 노키아 코포레이션 | 메모리 기기 상의 데이터 저장 방법, 기기 및 데이터 구조 |
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EP1729218A4 (en) * | 2004-04-20 | 2007-07-18 | Matsushita Electric Ind Co Ltd | NON-VOLATILE STORAGE SYSTEM |
JP4991320B2 (ja) * | 2007-01-12 | 2012-08-01 | 株式会社東芝 | ホスト装置およびメモリシステム |
JP5026213B2 (ja) * | 2007-09-28 | 2012-09-12 | 株式会社日立製作所 | ストレージ装置及びデータ重複排除方法 |
CN101727292B (zh) * | 2008-10-16 | 2013-04-17 | 深圳市朗科科技股份有限公司 | 存储设备的访问系统、方法及存储设备 |
CN101650690B (zh) * | 2009-09-21 | 2011-03-02 | 中兴通讯股份有限公司 | 大容量存储卡的应用方法及移动终端 |
TWI494948B (zh) * | 2011-01-31 | 2015-08-01 | Phison Electronics Corp | 用於非揮發性記憶體的資料寫入方法、控制器與儲存裝置 |
US9645739B2 (en) * | 2014-09-26 | 2017-05-09 | Intel Corporation | Host-managed non-volatile memory |
JP7213712B2 (ja) * | 2019-02-14 | 2023-01-27 | キオクシア株式会社 | 不揮発性半導体記憶装置 |
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- 2004-08-26 WO PCT/JP2004/012714 patent/WO2005022393A1/ja active Application Filing
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EP1895418A4 (en) * | 2005-12-09 | 2008-08-27 | Matsushita Electric Ind Co Ltd | NON-VOLATILE MEMORY DEVICE AND METHOD FOR WRITEING AND READING DATA |
CN101484882A (zh) * | 2005-12-09 | 2009-07-15 | 晟碟以色列有限公司 | 闪存管理方法 |
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Also Published As
Publication number | Publication date |
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CN100511181C (zh) | 2009-07-08 |
TWI354893B (ja) | 2011-12-21 |
CN1846199A (zh) | 2006-10-11 |
JPWO2005022393A1 (ja) | 2006-10-26 |
EP1659497A4 (en) | 2008-01-23 |
US20070276986A1 (en) | 2007-11-29 |
TW200511012A (en) | 2005-03-16 |
US7987314B2 (en) | 2011-07-26 |
JP4667243B2 (ja) | 2011-04-06 |
EP1659497A1 (en) | 2006-05-24 |
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