Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
  • H03K17/12—Modifications for increasing the maximum permissible switched current
  • H03K17/127—Modifications for increasing the maximum permissible switched current in composite switches

Definitions

• the present invention relates to the field of power electronics. It relates to an electronic circuit and a power semiconductor module according to the preamble of claim 1 pp.6.
• FIG. 1 shows a circuit diagram of a power semiconductor module with three parallel-connected power semiconductor switches according to the prior art, which results, for example, in an asymmetrical layout of three bipolar transistors T ⁇ T 2 and T 3 with insulated gate (IGBT).
• Parasitic emitter-side inductors L E> 1 , L E ⁇ 2 , and L E ⁇ 3 have different values due to different geometries of corresponding electrically conductive connections between the respective emitter terminal E 1s E 2 or E 3 and a node C, respectively. In a switching operation different voltages are induced via this due to the different values of the inductances L E ⁇ 1 , L E ⁇ 2 , and /.
• Another variant also uses the hard, direct connection of the output sides, but decouples the drive sides by using separate control units. However, this places high demands on the synchronicity and affinity of the control units, which in turn leads to increased production costs.
• inventive electronic circuit in particular for use as a power switch, is a drive unit which generates at least one drive signal, and two or more synchronously switchable by the drive signal power semiconductor switch, each having a first and a second main terminal, wherein the first and the second main terminals of the power semiconductor switches are each electrically connected in parallel, provided.
• a first and a second electrically conductive connection is provided for connection to the drive unit, wherein in each of the first electrically conductive connections a first inductance and in each of the second electrically conductive connections a second inductance is provided and for each of Power semiconductor switch, the first inductance is coupled to the second inductance.
• each have a common-mode rejection inductor is in each pair of first and second electrically conductive connections are provided, that for each of the power semiconductor switch is each provided for hen "a Gleichtaktunterd Wegungsdrossei.
• a first winding of the common-mode rejection inductor forms the first inductance and a second winding of the common-mode rejection inductor, the second inductance.
• the coupled inductors reduce coupling and crosstalk problems during switching operations. Dynamic circulating currents are minimized and vibrations between the power semiconductor switches are effectively suppressed.
• the inventive electronic circuit has both the advantages of directly parallel output sides and the advantages of a separate control of the power semiconductor switch, without a synchronization of several separate control units or a costly wiring in the output circuit would be necessary, allowing a cost-effective production.
• a symmetrization of the output sides can be optimized for a DC behavior, in particular by a uniform division of a gate resistance on the gate and emitter of the power semiconductor switches.
• the common mode rejection chokes decouple the pairs of first and second electrically conductive connections from the power circuit which is connected through the power semiconductor switches between cathode terminals and a common node of the power semiconductor. switch runs.
• the decoupling ensures a uniform dynamic distribution of current to corresponding paths in the power circuit.
• Fig. 1 shows an electronic circuit with three parallel-connected buttergur- * '3-conductor switches of the prior art.
• Fig. 2 shows an inventive electronic circuit.
• 3a shows a circuit diagram of a measuring arrangement for measuring a series inductance of a common mode rejection choke D ,.
• FIG. 3b shows a circuit diagram of a measuring arrangement for measuring a common mode inductance of a common mode rejection choke D, -.
• Fig. 4 shows a preferred embodiment of an inventive electronic circuit.
• FIG. 2 shows an electronic circuit according to the invention with three IGBTs Tj connected in parallel, with i ⁇ 1, 2, 3 ⁇ , as a power semiconductor switch. These are synchronously switchable by means of a common drive unit 20.
• each of the IGBTs Tj can be fed via a respective drive supply pair to a drive signal generated by the common drive unit 20.
• the synchronously switchable power semiconductor switches T unipolar insulated gate field effect transistors (MOS-FET), p
• MOS-FET unipolar insulated gate field effect transistors
• a common mode rejection choke Dj is provided in each pair of first and second electrically conductive connections (drive line pairs), ie for each i "of the power semiconductor switch Tj is each provided with a common mode rejection choke Dj.
• a first winding of the common-mode rejection 1 is formed ;
• Dj chooses the first inductor D1rt and a second winding of the common mode rejection choke D
• the drive supply pairs ie the pairs of first and second electrically conductive connections, are decoupled from a power circuit which runs through the IGBTs Tj between the cathode connections Kj and a common node C.
• the decoupling ensures a uniform dynamic current distribution on paths Ki-C, K 2 -C and K 3 -C in the power circuit.
• a gate resistance is divided so that for ie ⁇ 1,2,3 ⁇ R G ,, - ⁇ /?
• Series inductances L 1 of the common-mode rejection chokes D j are preferably chosen to be as small as possible, preferably less than or equal to 200 n H.
• the rows- Inductance of the common mode rejection choke Dj is that inductance which is measured when both windings of the common mode rejection choke Dj are connected in series.
• 3a shows a circuit diagram of a measuring arrangement for measuring the series inductance of the common mode rejection choke Dj.
• Common-mode inductors J of the common-mode rejection chokes Dj are preferably selected at least approximately as follows: starting from a maximum ⁇ L E of the differences L E j-L EJ between two emitter inductances with i ⁇ each ⁇ 1,2,3 ⁇ and a predetermined maximum permissible value Difference ⁇ U GE between two gate emitter voltages U GE, - - and U GE , which between auxiliary emitter terminals Hj and H j and gate terminals Gj. or G j of two IGBTs Tj or T j with i ⁇ each ⁇ 1, 2, 3 ⁇ , a minimum DC inactivity can be calculated.
• the IGBTs Tj are voltage-controlled components / * in which a collector current via the gate emitter voltage U GE ;, can be set, 'the maximum allowable voltage difference .DELTA.U GE must have a maximum allowable col. Lektorstromunter Kunststoff in a region of interest from a transfer characteristic of the IGBTs Tj are read out.
• a maximum allowable difference ⁇ I G between gate currents lj and l j with i ⁇ je ⁇ 1,2,3 ⁇ can then be calculated by the maximum allowable difference of the gate charge ⁇ Q GE by a relevant time t R , during which the voltage across the different emitter inductances builds, is shared, that is .DELTA.Q
• the voltage time area above the maximum ⁇ L E of the differences of the emitter inductance L E - L E can be determined by. Multiplication of ⁇ L E with. a greatest possible current, the short circuit current P l as the IGBTs, are calculated:
• the common mode inductance of the common mode rejection chokes Dj is that inductance which is measured when both windings of the common mode rejection choke Dj are connected in parallel.
• FIG. 3b shows a circuit diagram of a measuring arrangement for measuring the common mode inductance of the common mode rejection choke Dj.
• Fig. 4 shows a preferred embodiment of the inventive electronic circuit.
• a resistor R D is provided between the node A 2 and the auxiliary emitter terminals H 2 parallel to the common mode rejection choke D 2 in order to minimize peak values U D between the drive unit 20 and the power circuit.
• a value of a few ohms to a few tens of ohms is selected for R D.
• a power semiconductor module according to the invention comprises a module housing of a type known per se and an electronic circuit according to the invention, as described in this section.
• both the power semiconductor switches and the drive unit 20 and / or the first and second inductances are accommodated in the module housing.
• the drive unit 20 and / or the first and second inductances may also be provided outside the module housing, in particular screwed or plugged.
• this comprises two or more submodules, and the at least two power semiconductor switches controlled by the control unit are not all located in the same submodule.
• the invention can be particularly advantageous since them-' * other identical or mirror-inverted version of control and hozutechnische'n in power semiconductor switches, which are located in different sub-modules, the * is generally not feasible and therefore known, Auxiliary solutions described in the prior art are not available.

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• Power Conversion In General (AREA)
• Electronic Switches (AREA)

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• 2003
  • 2003-05-19 EP EP03405343A patent/EP1480339A1/de not_active Withdrawn
• 2004
  • 2004-05-18 WO PCT/CH2004/000301 patent/WO2004102806A1/de not_active Ceased
  • 2004-05-18 CN CNB2004800136580A patent/CN100394691C/zh not_active Expired - Lifetime
  • 2004-05-18 US US10/557,408 patent/US7671639B2/en active Active
  • 2004-05-18 DE DE502004002311T patent/DE502004002311D1/de not_active Expired - Lifetime
  • 2004-05-18 JP JP2006529536A patent/JP4611985B2/ja not_active Expired - Lifetime
  • 2004-05-18 EP EP04733520A patent/EP1625660B1/de not_active Expired - Lifetime

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