WO2004081974A2 - A method of producing substrates or components on substrates involving transfer of a useful layer, for microelectronics, optoelectronics, or optics - Google Patents

A method of producing substrates or components on substrates involving transfer of a useful layer, for microelectronics, optoelectronics, or optics Download PDF

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Publication number
WO2004081974A2
WO2004081974A2 PCT/IB2004/001344 IB2004001344W WO2004081974A2 WO 2004081974 A2 WO2004081974 A2 WO 2004081974A2 IB 2004001344 W IB2004001344 W IB 2004001344W WO 2004081974 A2 WO2004081974 A2 WO 2004081974A2
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WO
WIPO (PCT)
Prior art keywords
support
layer
useful layer
interface
peripheral zone
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PCT/IB2004/001344
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French (fr)
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WO2004081974A3 (en
Inventor
Fabrice Letertre
Olivier Rayssac
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S.O.I.Tec Silicon On Insulator Technologies
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Application filed by S.O.I.Tec Silicon On Insulator Technologies filed Critical S.O.I.Tec Silicon On Insulator Technologies
Priority to EP04720118A priority Critical patent/EP1606839A2/en
Priority to JP2006506557A priority patent/JP4672648B2/en
Publication of WO2004081974A2 publication Critical patent/WO2004081974A2/en
Publication of WO2004081974A3 publication Critical patent/WO2004081974A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H01L21/30621—Vapour phase etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Definitions

  • the present invention generally relates to methods of fabricating substrates for microelectronics, optoelectronics, or optics involving transfer of a useful layer from a first support to a second support.
  • molecular bonding techniques in which the bonding energy is controlled so that a mechanical force can result in separation of a layer which has been temporarily bonded to a support can also be mentioned.
  • transfer of the layer involves bringing a second support into contact with the free face of the useful layer using suitable bonding forces, which free face of the assembly comprising the layer and the first support is known as the "front" face.
  • the problem is different when the useful layer has already undergone steps in the component fabrication process, in which case it is often necessary to carry out different types of deposition (semiconductor oxides or nitrides, polycrystalline semiconductor, amorphous semiconductor, monocrystalline semiconductor formed by homo- or hetero-epitaxy) .
  • said deposits have a tendency to partially or completely cover the free face of the useful layer and to overflow onto the side faces of the substrate composed of said useful layer temporarily fixed to its first support.
  • Overflowed covering produces a useful layer that is encapsulated after a fashion, the main result being strengthening of the periphery of the bond between the useful layer and the first support, which can then render problematic the subsequent detachment required to transfer said useful layer to its second support.
  • the invention aims to overcome this drawback.
  • the invention provides a method for transferring a useful layer of a monocrystalline material from a first support to a second support, for use in fabricating substrates or components on substrates for microelectronics, optoelectronics or optics, comprising the following steps:
  • the material removing step comprises removing a peripheral zone of deposited material which covers the interface laterally.
  • the material removing step is implemented by cutting.
  • the material removing step is implemented by etching.
  • - etching is carried out by masking the useful layer inside the peripheral zone.
  • the material removing step also comprises removing at least a portion of the material of the first support beneath the peripheral zone of deposited material.
  • the material removing step comprises removing a peripheral zone of material from the first support in the region in which the peripheral zone of deposited material is formed, prior to said deposition.
  • the peripheral zone of the material from the' first support is a peripheral recess that opens laterally and frontally at the side of the useful layer.
  • the depth of the recess is greater than or equal to the thickness of the peripheral zone of deposited material .
  • the width of the recess is such that it substantially covers the distance between the outer edge of the first support and the outer edge of the useful layer.
  • the step of removing a peripheral zone from the first support is implemented after forming the useful layer on said first support.
  • the detachment step is implemented by applying lateral stresses at the detachable interface using a detachment means .
  • the material removal step comprises forming separating channels between the exposed face of the useful layer and the region of the detachable interface, prior to the step of securing the exposed face of the useful layer to the second support .
  • the channels are formed using a technique selected from the group formed by saw cutting, laser cutting, ion beam cutting and masked chemical etching.
  • the detachment step is performed using a detachment means that can apply, between the first and second supports, one or more stresses selected from the group formed by tension, bending and shear stresses.
  • the deposited material layer is formed by "full wafer" epitaxy.
  • the useful layer comprises a layer forming a seed for epitaxial growth and one or more epitaxially grovm layers .
  • the material of the seed layer is selected from the group formed by silicon carbide, sapphire, gallium nitride, silicon and aluminum nitride.
  • the epitaxially grown layer is formed from one or more metal nitrides.
  • the material of the first support is selected from the group formed by semiconductors, semiconductor carbides and insulators such as sapphire.
  • the detachable interface is formed using a technique selected from the group formed by implanting gas species, forming a porous layer that can be attacked chemically, and bonding by molecular bonding with control of the bonding forces.
  • the invention provides a support for fabricating substrates or components on substrates for microelectronics, optoelectronics or optics, which can receive at least a portion of a useful layer, having a detachable interface between the support and the useful layer, and in which a material layer deposition on the useful layer can form a peripheral zone of deposited material that laterally covers said interface at least partially, the support comprising a peripheral recessed zone adapted for receiving said peripheral zone of deposited material, enabling said interface to be exposed laterally for detachment purposes .
  • Figure 1 is a cross sectional view of a first substrate comprising a first support and a useful layer
  • Figure 2 is a cross sectional view of a second support affixed to a first substrate in order to transfer the useful layer thereto;
  • Figure 3 is a cross sectional view illustrating detachment of a working zone from a detachment tool
  • Figure 4 is a cross sectional view of the first substrate illustrating a particular arrangement of a first support of a detachment tool
  • Figures 5 and 6 are cross sectional and plan views of a particular arrangement of the useful layer for gaining access to the interface between it and the first support .
  • a first support 10 is formed from a semiconductor material, for example silicon carbide SiC, mono- or polycrystalline silicon, etc, or formed from an insulating material, for example sapphire.
  • a layer 12 is formed or deposited on said first support and forms a releasable bonding interface; typically, it can be a layer of semiconducting oxide such as Si0 2 / semiconducting nitride, etc.
  • the layer 12 forms a releasable bonding interface between the first support 10 and a useful layer formed in this case by a base layer 14 on which a layer 16 has been formed or deposited.
  • the base layer 14 is a seed layer on which the layer 16 is formed by epitaxy. This seed layer is formed of silicon carbide, sapphire, gallium nitride, silicon, or aluminum nitride, for example.
  • the base layer 14 is formed of SiC while the epitaxially grown layer is formed of a metal nitride such as gallium nitride GaN, or formed by a stack of different metal nitrides.
  • Such a useful layer structure is of advantage in particular in fabricating light-emitting diodes (LEDs) .
  • the first support is slightly larger than the assembly of layers 12, 14 and 16 formed on said support.
  • Deposition of the layer 16 by epitaxy which is traditionally carried out in a "full wafer” reactor, thus extends not only above the seed layer 14, but also around a ring 161 which covers the recessed periphery of the support 10.
  • Figure 2 illustrates affixing the assembly shown in
  • Figure 1 termed the first substrate, to a second support
  • fixing is carried out using a metal bonding technique; the bonding layer is illustrated at 22.
  • the useful layer 14, 16 is transferred from the first support 10 to the second support 20 after fixing as described above, in particular using a detachment tool that can apply a stress to the interface layer 12 between the useful layer 14, 16 and the first support 10, to propagate separation in the plane of said interface.
  • Figure 2 shows that the deposited GaN ring 161 causes two problems as regards such an operation: firstly, it reinforces the bond between the useful layer 14, 16 and the first support at the periphery of the first substrate, and secondly, it renders impossible direct access to the bonding interface 12 by a detachment tool (thin blade, jet of fluid, etc) in order to apply thereto the required detachment stress (arrow FI in Figure 3a) .
  • a detachment tool thin blade, jet of fluid, etc
  • a first solution is shown diagrammatically in Figure 3a. It consists of removing the ring 161. In a first embodiment, said removal can be carried out by etching. To this end, a mask is produced on the free face of the useful layer 14, 16, which mask will only release the ring 161. An attack medium that is suitable for the material of the ring is then used to attack and remove the ring over its entire thickness, in order to detach the separable interface layer 12.
  • the ring is GaN
  • the following is preferably carried out: plasma etching or RIE (reactive ion etching) based on SiCl , BCl 3 (reference should be made to the article "GaN: Processing, Defects and Devices", S J Pearton et al, Journal of Applied Physics, vol 86, no 1, 1 st July 1999).
  • plasma etching or RIE reactive ion etching
  • the ring is removed using a cutting or trimming technique. It is possible to use a mechanical saw cutting technique, a laser cutting technique, or an ion beam cutting technique. As will be understood, the ring is removed by producing a cylindrical cut of revolution and a cut in a transitional plane between the ring 161 and the first support 10. In all cases, care is taken that etching or cutting provides satisfactory access to the detachable interface layer 12 to allow transfer of the useful layer. It should be noted in this respect that merely partial removal of the ring 161 may be sufficient to attenuate the peripheral bond between the first support 10 and the useful layer 14, 16 and to allow the detachment tool to act correctly. In contrast, it is possible to remove the ring 161 while also penetrating into the support itself.
  • cutting is carried out through the entire thickness of the first substrate to remove not only the interfering ring 161 but also the portion 101 of the first support which is subjacent thereto.
  • This variation may be more suitable when the working depth of the cutting technique is difficult to control.
  • the ring 161 is removed before the second support 20 has been affixed to the useful layer 14, 16.
  • removal can be carried out after fixing.
  • FIG. 4 A further approach for overcoming the problem caused by the peripheral deposit 161 is illustrated in Figure 4. It consists of using a first support 10 specifically prepared to include a peripheral recess 102.
  • said peripheral recess extends in a radial direction (horizontally in Figure 4) between the outer edge of the support 10 and the outer edge of the interface layer 12 and useful layer 14, 16.
  • said recess 102 preferably extends over a depth (d) that ' is at least equal to the thickness of the deposit 16 formed, so that at the end of the deposition operation, the peripheral ring 161 that it forms does not obstruct the releasable interface. Thus, the ring 161 does not have to be removed .
  • the recess is preferably produced before forming the layers 12 and 14, and in any case before forming all or a portion of the useful layer which may cover the periphery of the first substrate.
  • said recess is produced by ablation with a laser beam or by mechanical trimming.
  • a further approach is shown in Figures 5 and 6. It consists of forming cuts or channels 18 in the thickness of the useful layer 14, 16, down to the interface layer 12.
  • These cuts define individual islets or tiles 19, for example square in shape, as shown in Figure 6, with a size that is preferably in the range from l x l square micrometer ( ⁇ m 2 ) to 300 x 300 ⁇ m 2 .
  • These cuts can be formed either mechanically, using a saw cutting technique, or laser cutting or using ion beam cutting, or chemically by etching, first placing an etching mask that allows selective geometric attack on the free surface of the useful layer 14, 16.
  • an etching mask that allows selective geometric attack on the free surface of the useful layer 14, 16.
  • a dry or wet etching technique is used.
  • said stress can be a tension, bending or shear stress, or a variety of combinations of said stresses.
  • the present invention can be applied to a very wide variety of semiconductor materials.
  • the invention can be employed, for example when transferring a useful layer based on silicon in which certain methods for fabricating components using CMOS technology on a second insulating support 10 have been carried out. Many other applications are also possible.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

The invention provides a method of transferring a useful layer of a monocrystalline material from a first support to a second support, comprising the following steps: forming a first substrate comprising the first support (10) and the useful layer (14, 16) with a detachable interface (12) between them, in which a treatment involving the useful layer includes the formation of a peripheral zone of material (161) that may laterally cover said interface; removing material, allowing detachment to reach said interface (12) in order to detach it at said interface; affixing a free face of the useful layer (14, 16) to a second support (20); and detaching at said interface (12). The detachment means can be employed in the absence of a peripheral zone of material. Application to fabricating substrates or components on substrates for microelectronics, optoelectronics, or optics.

Description

A METHOD OF PRODUCING SUBSTRATES OR COMPONENTS ON SUBSTRATES INVOLVING TRANSFER OF A USEFUL LAYER, FOR MICROELECTRONICS, OPTOELECTRONICS, OR OPTICS
The present invention generally relates to methods of fabricating substrates for microelectronics, optoelectronics, or optics involving transfer of a useful layer from a first support to a second support.
Various techniques have recently been developed to allow the mechanical transfer of a layer of semiconductor material - which may or may not already have received component production treatments - from a first support to a second support .
Techniques using buried porous layers that can be attacked chemically, such as those described in European patent EP-A-0 849 788, can be mentioned in particular.
Substrates weakened by implanting gas species, whereby a thin useful layer can be separated from the remainder of the material by fracture at the implanted zone, can also be mentioned.
Finally, molecular bonding techniques in which the bonding energy is controlled so that a mechanical force can result in separation of a layer which has been temporarily bonded to a support can also be mentioned. When a useful layer is connected to a first support using one of the above techniques, transfer of the layer involves bringing a second support into contact with the free face of the useful layer using suitable bonding forces, which free face of the assembly comprising the layer and the first support is known as the "front" face.
Transfer is completed by applying stresses
(typically tension and/or bending and/or shear) between the layer to be transferred and the first support, employing one or more tools such as a drawing rig or a blade introduced laterally at the weakened interface to propagate a crack, or by applying a jet of fluid to said weakened interface (see, for example, French patent FR-A-2 796 491) .
When the useful layer to be transferred has not undergone any component fabrication steps, then said transfer is generally carried out regardless of the bonding technique employed to affix the useful layer to the second support (in particular by molecular bonding, eutectic bonding, bonding using a polymer or resin, etc) .
In contrast, the problem is different when the useful layer has already undergone steps in the component fabrication process, in which case it is often necessary to carry out different types of deposition (semiconductor oxides or nitrides, polycrystalline semiconductor, amorphous semiconductor, monocrystalline semiconductor formed by homo- or hetero-epitaxy) .
When, for example, a "full wafer" method is carried out in a specific reactor, said deposits have a tendency to partially or completely cover the free face of the useful layer and to overflow onto the side faces of the substrate composed of said useful layer temporarily fixed to its first support.
Overflowed covering produces a useful layer that is encapsulated after a fashion, the main result being strengthening of the periphery of the bond between the useful layer and the first support, which can then render problematic the subsequent detachment required to transfer said useful layer to its second support.
The present invention aims to overcome this drawback. To this end, in a first aspect, the invention provides a method for transferring a useful layer of a monocrystalline material from a first support to a second support, for use in fabricating substrates or components on substrates for microelectronics, optoelectronics or optics, comprising the following steps:
• forming a first substrate comprising the first support and at least a portion of the useful layer with a detachable interface between the first support and the useful layer, the outer edge of the useful layer being inwardly spaced from the outer edge of the first support; • forming a deposited layer of material on the useful layer, said deposited layer being liable to laterally cover said detachable interface at least partially;
• locally removing support material and/or deposited material so as to have said detachable interface exposed;
• securing an exposed face of the useful layer to a second support; and
• causing detachment at said detachable interface between the first support and the useful layer, said detachment being promoted by said exposed regions of the detachable interface. The following are preferred but non limiting features of the method: - the material removing step comprises removing a peripheral zone of deposited material which covers the interface laterally. the material removing step is implemented by cutting. - the material removing step is implemented by etching.
- etching is carried out by masking the useful layer inside the peripheral zone.
- the material removing step also comprises removing at least a portion of the material of the first support beneath the peripheral zone of deposited material.
- the material removing step comprises removing a peripheral zone of material from the first support in the region in which the peripheral zone of deposited material is formed, prior to said deposition. - the peripheral zone of the material from the' first support is a peripheral recess that opens laterally and frontally at the side of the useful layer.
- the depth of the recess is greater than or equal to the thickness of the peripheral zone of deposited material . the width of the recess is such that it substantially covers the distance between the outer edge of the first support and the outer edge of the useful layer.
- the step of removing a peripheral zone from the first support is implemented after forming the useful layer on said first support. the detachment step is implemented by applying lateral stresses at the detachable interface using a detachment means . the material removal step comprises forming separating channels between the exposed face of the useful layer and the region of the detachable interface, prior to the step of securing the exposed face of the useful layer to the second support .
- the channels define individual islands.
- the channels are formed using a technique selected from the group formed by saw cutting, laser cutting, ion beam cutting and masked chemical etching. the detachment step is performed using a detachment means that can apply, between the first and second supports, one or more stresses selected from the group formed by tension, bending and shear stresses. - the deposited material layer is formed by "full wafer" epitaxy.
- the useful layer comprises a layer forming a seed for epitaxial growth and one or more epitaxially grovm layers . - the material of the seed layer is selected from the group formed by silicon carbide, sapphire, gallium nitride, silicon and aluminum nitride. - the epitaxially grown layer is formed from one or more metal nitrides.
- the material of the first support is selected from the group formed by semiconductors, semiconductor carbides and insulators such as sapphire. the detachable interface is formed using a technique selected from the group formed by implanting gas species, forming a porous layer that can be attacked chemically, and bonding by molecular bonding with control of the bonding forces.
In a second aspect of the invention, the invention provides a support for fabricating substrates or components on substrates for microelectronics, optoelectronics or optics, which can receive at least a portion of a useful layer, having a detachable interface between the support and the useful layer, and in which a material layer deposition on the useful layer can form a peripheral zone of deposited material that laterally covers said interface at least partially, the support comprising a peripheral recessed zone adapted for receiving said peripheral zone of deposited material, enabling said interface to be exposed laterally for detachment purposes .
Further aspects, aims, and advantages of the present invention will become apparent from the following description of preferred implementations thereof, given by way of non-limiting example and made with reference to the accompanying drawings, in which:
Figure 1 is a cross sectional view of a first substrate comprising a first support and a useful layer;
Figure 2 is a cross sectional view of a second support affixed to a first substrate in order to transfer the useful layer thereto;
Figure 3 is a cross sectional view illustrating detachment of a working zone from a detachment tool; Figure 4 is a cross sectional view of the first substrate illustrating a particular arrangement of a first support of a detachment tool;
Figures 5 and 6 are cross sectional and plan views of a particular arrangement of the useful layer for gaining access to the interface between it and the first support .
Referring firstly to Figures 1 and 2, a first support 10 is formed from a semiconductor material, for example silicon carbide SiC, mono- or polycrystalline silicon, etc, or formed from an insulating material, for example sapphire.
A layer 12 is formed or deposited on said first support and forms a releasable bonding interface; typically, it can be a layer of semiconducting oxide such as Si02/ semiconducting nitride, etc.
The layer 12 forms a releasable bonding interface between the first support 10 and a useful layer formed in this case by a base layer 14 on which a layer 16 has been formed or deposited. Typically, the base layer 14 is a seed layer on which the layer 16 is formed by epitaxy. This seed layer is formed of silicon carbide, sapphire, gallium nitride, silicon, or aluminum nitride, for example. In one embodiment, the base layer 14 is formed of SiC while the epitaxially grown layer is formed of a metal nitride such as gallium nitride GaN, or formed by a stack of different metal nitrides.
Such a useful layer structure is of advantage in particular in fabricating light-emitting diodes (LEDs) .
As seen in Figure 1, in conventional manner, the first support is slightly larger than the assembly of layers 12, 14 and 16 formed on said support. Deposition of the layer 16 by epitaxy, which is traditionally carried out in a "full wafer" reactor, thus extends not only above the seed layer 14, but also around a ring 161 which covers the recessed periphery of the support 10. Figure 2 illustrates affixing the assembly shown in
Figure 1, termed the first substrate, to a second support
20. In this case, fixing is carried out using a metal bonding technique; the bonding layer is illustrated at 22.
The useful layer 14, 16 is transferred from the first support 10 to the second support 20 after fixing as described above, in particular using a detachment tool that can apply a stress to the interface layer 12 between the useful layer 14, 16 and the first support 10, to propagate separation in the plane of said interface.
However, Figure 2 shows that the deposited GaN ring 161 causes two problems as regards such an operation: firstly, it reinforces the bond between the useful layer 14, 16 and the first support at the periphery of the first substrate, and secondly, it renders impossible direct access to the bonding interface 12 by a detachment tool (thin blade, jet of fluid, etc) in order to apply thereto the required detachment stress (arrow FI in Figure 3a) .
Several solutions for solving these problems are described below.
A first solution is shown diagrammatically in Figure 3a. It consists of removing the ring 161. In a first embodiment, said removal can be carried out by etching. To this end, a mask is produced on the free face of the useful layer 14, 16, which mask will only release the ring 161. An attack medium that is suitable for the material of the ring is then used to attack and remove the ring over its entire thickness, in order to detach the separable interface layer 12. In the present example, as the ring is GaN, the following is preferably carried out: plasma etching or RIE (reactive ion etching) based on SiCl , BCl3 (reference should be made to the article "GaN: Processing, Defects and Devices", S J Pearton et al, Journal of Applied Physics, vol 86, no 1, 1st July 1999). In a variation, other etching techniques such as plasma etching can be used.
In a second embodiment, the ring is removed using a cutting or trimming technique. It is possible to use a mechanical saw cutting technique, a laser cutting technique, or an ion beam cutting technique. As will be understood, the ring is removed by producing a cylindrical cut of revolution and a cut in a transitional plane between the ring 161 and the first support 10. In all cases, care is taken that etching or cutting provides satisfactory access to the detachable interface layer 12 to allow transfer of the useful layer. It should be noted in this respect that merely partial removal of the ring 161 may be sufficient to attenuate the peripheral bond between the first support 10 and the useful layer 14, 16 and to allow the detachment tool to act correctly. In contrast, it is possible to remove the ring 161 while also penetrating into the support itself.
In a variation, as illustrated in Figure 3b, cutting is carried out through the entire thickness of the first substrate to remove not only the interfering ring 161 but also the portion 101 of the first support which is subjacent thereto. This variation may be more suitable when the working depth of the cutting technique is difficult to control.
Preferably, the ring 161 is removed before the second support 20 has been affixed to the useful layer 14, 16. However, if the technique used to remove the ring 161 allows it, removal can be carried out after fixing.
A further approach for overcoming the problem caused by the peripheral deposit 161 is illustrated in Figure 4. It consists of using a first support 10 specifically prepared to include a peripheral recess 102. Advantageously, said peripheral recess extends in a radial direction (horizontally in Figure 4) between the outer edge of the support 10 and the outer edge of the interface layer 12 and useful layer 14, 16. In the axial direction (vertically in Figure 4) , said recess 102 preferably extends over a depth (d) that ' is at least equal to the thickness of the deposit 16 formed, so that at the end of the deposition operation, the peripheral ring 161 that it forms does not obstruct the releasable interface. Thus, the ring 161 does not have to be removed .
The recess is preferably produced before forming the layers 12 and 14, and in any case before forming all or a portion of the useful layer which may cover the periphery of the first substrate.
Preferably, said recess is produced by ablation with a laser beam or by mechanical trimming. A further approach is shown in Figures 5 and 6. It consists of forming cuts or channels 18 in the thickness of the useful layer 14, 16, down to the interface layer 12.
These cuts define individual islets or tiles 19, for example square in shape, as shown in Figure 6, with a size that is preferably in the range from l x l square micrometer (μm2) to 300 x 300 μm2 .
These cuts can be formed either mechanically, using a saw cutting technique, or laser cutting or using ion beam cutting, or chemically by etching, first placing an etching mask that allows selective geometric attack on the free surface of the useful layer 14, 16. Preferably, and in particular to prevent said attack from excavating the walls of the channels too much during formation, a dry or wet etching technique is used.
When the useful layer is formed from a seed layer of SiC 14 on which GaN epitaxy is carried out, argon based ion etching is carried out (see the article "GaN: Processing, Defects and Devices", cited above). With such an approach, reinforcement of the interface between the useful layer and the first support caused by the presence of the ring 161 is avoided since, when a releasing stress is exerted between the supports 10 and 20 after producing the assembly of the type illustrated in Figure 2, each individualized tile, which is not itself subjected to the reinforcement due to the ring 161, can be separated from the support under the effect of said stress.
It should be noted that said stress can be a tension, bending or shear stress, or a variety of combinations of said stresses. Clearly, the present invention can be applied to a very wide variety of semiconductor materials. In addition to the example of a layer of nitride developed on silicon carbide on insulator (SiCOI) as described above, the invention can be employed, for example when transferring a useful layer based on silicon in which certain methods for fabricating components using CMOS technology on a second insulating support 10 have been carried out. Many other applications are also possible.
In this respect, the skilled person will readily select solutions that are suitable (choice of one of the three approaches described, choice of type of material removal, etc) as a function of the materials used.
Finally, it can be observed that the three approaches of the invention described above can be combined together.

Claims

1. A method for transferring a useful layer of a monocrystalline material from a first support to a second support, for use in fabricating substrates or components on substrates for microelectronics, optoelectronics or optics, comprising the following steps:
• forming a first substrate comprising the first support and at least a portion of the useful layer with a detachable interface between the first support and the useful layer, the outer edge of the useful layer being inwardly spaced from the outer edge of the first support;
• forming a deposited layer of material on the useful layer, said deposited layer being liable to laterally cover said detachable interface at least partially; © locally removing support material and/or deposited material so as to have said detachable interface exposed;
• securing an exposed face of the useful layer to a second support; and
© causing detachment at said detachable interface between the first support and the useful layer, said detachment being promoted by said exposed regions of the detachable interface.
2. A method according to claim 1, wherein the material removing step comprises removing a peripheral zone of deposited material which covers the interface laterally.
3. A method according to claim 2, wherein the material removing step is implemented by cutting.
4. A method according to claim 2, wherein the material removing step is implemented by etching.
5. A method according to claim 3, wherein etching is carried out by masking the useful layer inside the peripheral zone.
6. A method according to any one of claims 2 to 5, wherein the material removing step also comprises removing at least a portion of the material of the first support beneath the peripheral zone of deposited material .
7. A method according to claim 1, wherein the material removing step comprises removing a peripheral zone of material from the first support in the region in which the peripheral zone of deposited material is formed, prior to said deposition.
8. A method according to claim 7 , wherein the peripheral zone of the material from the first support is a peripheral recess that opens laterally and frontally at the side of the useful layer.
9. A method according to claim 8, wherein the depth (d) of the recess is greater than or equal to the thickness of the peripheral zone of deposited material.
10. A method according to claim 8 or claim 9, wherein the width of the recess is such that it substantially covers the distance between the outer edge of the first support and the outer edge of the useful layer.
11. A method according to any one of claims 7 to 10, wherein the step of removing a peripheral zone from the first support is implemented after forming the useful layer on said first support.
12. A method according to any one of claims 2 to 11, wherein the detachment step is implemented by applying lateral stresses at the detachable interface using a detachment means .
13. A method according to claim 12, wherein the material removal step comprises forming separating channels between the exposed face of the useful layer and the region of the detachable interface, prior to the step of securing the exposed face of the useful layer to the second support .
14. A method according to claim 13, wherein the channels define individual islands.
15. A method according to claim 13 or claim 14, wherein the channels are formed using a technique selected from the group formed by saw cutting, laser cutting, ion beam cutting and masked chemical etching.
16. A method according to any one of claims 13 to 15, wherein the detachment step is performed using a detachment means that can apply, between the first and second supports, one or more stresses selected from the group formed by tension, bending and shear stresses.
17. A method according to any one of claims 1 to 16, wherein the deposited material layer is formed by "full wafer" epitaxy.
18. A method according to claim 17, wherein the useful layer comprises a layer forming a seed for epitaxial growth and one or more epitaxially grown layers.
19. A method according to claim 18, wherein the material of the seed layer is selected from the group formed by silicon carbide, sapphire, gallium nitride, silicon and aluminum nitride.
20. A method according to claim 19, wherein the epitaxially grown layer is formed from one or more metal nitrides .
21. A method according to any one of claims 1 to 20, wherein the material of the first support is selected from the group formed by semiconductors, semiconductor carbides and insulators such as sapphire.
2 . A method according to any one of claims 1 to 21, wherein the detachable interface is formed using a technique selected from the group formed by implanting gas species, forming a porous layer that can be attacked chemically, and bonding by molecular bonding with control of the bonding forces.
23. A support for fabricating substrates or components on substrates for microelectronics, optoelectronics or optics, which can receive at least a portion of a useful layer, having a detachable interface between the support and the useful layer, and in which a material layer deposition on the useful layer can form a peripheral zone of deposited material that laterally covers said interface at least partially, the support comprising a peripheral recessed zone adapted for receiving said peripheral zone of deposited material, enabling said interface to be exposed laterally for detachment purposes .
PCT/IB2004/001344 2003-03-14 2004-03-12 A method of producing substrates or components on substrates involving transfer of a useful layer, for microelectronics, optoelectronics, or optics WO2004081974A2 (en)

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JP2006506557A JP4672648B2 (en) 2003-03-14 2004-03-12 Method for manufacturing a microelectronic, photoelectronic or optical substrate or component on a substrate, including the transfer of a useful layer

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005038903A1 (en) * 2003-10-14 2005-04-28 Tracit Technologies Method for preparing and assembling substrates
DE102007025649A1 (en) * 2007-07-21 2009-01-22 X-Fab Semiconductor Foundries Ag A method of transferring an epitaxial layer from a donor to a system disk of microsystem technology
US7572714B2 (en) 2005-07-08 2009-08-11 S.O.I.Tec Silicon On Insulator Technologies Film taking-off method
US8324075B2 (en) 2007-07-11 2012-12-04 Soitec Methods for recycling substrates and fabricating laminated wafers
US8530331B2 (en) 2006-04-10 2013-09-10 Commissariat A L'energie Atomique Process for assembling substrates with low-temperature heat treatments

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EP2246882B1 (en) * 2009-04-29 2015-03-04 Soitec Method for transferring a layer from a donor substrate onto a handle substrate
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6159323A (en) * 1997-12-02 2000-12-12 Commissariat A L'energie Atomique Process for selective transfer of a microstructure formed on an initial substrate to a final substrate
EP1059663A2 (en) * 1999-06-08 2000-12-13 Canon Kabushiki Kaisha Process for producing a semiconductor thin film with a bonding and separating steps, solar cell fabrication and anodizing apparatus
WO2002084721A2 (en) * 2001-04-13 2002-10-24 Commissariat A L'energie Atomique Detachable substrate or detachable structure and method for the production thereof

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69917819T2 (en) * 1998-02-04 2005-06-23 Canon K.K. SOI substrate
US6177359B1 (en) * 1999-06-07 2001-01-23 Agilent Technologies, Inc. Method for detaching an epitaxial layer from one substrate and transferring it to another substrate
JP3472197B2 (en) * 1999-06-08 2003-12-02 キヤノン株式会社 Semiconductor substrate and method for manufacturing solar cell
FR2796491B1 (en) * 1999-07-12 2001-08-31 Commissariat Energie Atomique METHOD FOR TAKING OFF TWO ELEMENTS AND DEVICE FOR IMPLEMENTING SAME
JP2001284622A (en) * 2000-03-31 2001-10-12 Canon Inc Method for manufacturing semiconductor member and method for manufacturing solar cell
JP4109823B2 (en) * 2000-10-10 2008-07-02 株式会社東芝 Manufacturing method of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6159323A (en) * 1997-12-02 2000-12-12 Commissariat A L'energie Atomique Process for selective transfer of a microstructure formed on an initial substrate to a final substrate
EP1059663A2 (en) * 1999-06-08 2000-12-13 Canon Kabushiki Kaisha Process for producing a semiconductor thin film with a bonding and separating steps, solar cell fabrication and anodizing apparatus
WO2002084721A2 (en) * 2001-04-13 2002-10-24 Commissariat A L'energie Atomique Detachable substrate or detachable structure and method for the production thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005038903A1 (en) * 2003-10-14 2005-04-28 Tracit Technologies Method for preparing and assembling substrates
US7572714B2 (en) 2005-07-08 2009-08-11 S.O.I.Tec Silicon On Insulator Technologies Film taking-off method
US8530331B2 (en) 2006-04-10 2013-09-10 Commissariat A L'energie Atomique Process for assembling substrates with low-temperature heat treatments
US8324075B2 (en) 2007-07-11 2012-12-04 Soitec Methods for recycling substrates and fabricating laminated wafers
DE102007025649A1 (en) * 2007-07-21 2009-01-22 X-Fab Semiconductor Foundries Ag A method of transferring an epitaxial layer from a donor to a system disk of microsystem technology
DE102007025649B4 (en) * 2007-07-21 2011-03-03 X-Fab Semiconductor Foundries Ag A method of transferring an epitaxial layer from a donor to a system disk of microsystem technology

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WO2004081974A3 (en) 2004-11-25
FR2852445A1 (en) 2004-09-17
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JP2006520539A (en) 2006-09-07
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