WO2004077296A1 - Method for forming rate compatible code using high dimensional product codes - Google Patents
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- WO2004077296A1 WO2004077296A1 PCT/KR2003/002919 KR0302919W WO2004077296A1 WO 2004077296 A1 WO2004077296 A1 WO 2004077296A1 KR 0302919 W KR0302919 W KR 0302919W WO 2004077296 A1 WO2004077296 A1 WO 2004077296A1
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
- H03M13/296—Particular turbo code structure
- H03M13/2963—Turbo-block codes, i.e. turbo codes based on block codes, e.g. turbo decoding of product codes
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/033—Theoretical methods to calculate these checking codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
- H03M13/2909—Product codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
- H03M13/2918—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes with error correction codes in three or more dimensions, e.g. 3-dimensional product code where the bits are arranged in a cube
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/47—Error detection, forward error correction or error protection, not provided for in groups H03M13/01 - H03M13/37
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/635—Error control coding in combination with rate matching
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/635—Error control coding in combination with rate matching
- H03M13/6362—Error control coding in combination with rate matching by puncturing
- H03M13/6368—Error control coding in combination with rate matching by puncturing using rate compatible puncturing or complementary puncturing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/635—Error control coding in combination with rate matching
- H03M13/6362—Error control coding in combination with rate matching by puncturing
- H03M13/6368—Error control coding in combination with rate matching by puncturing using rate compatible puncturing or complementary puncturing
- H03M13/6381—Rate compatible punctured turbo [RCPT] codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0067—Rate matching
- H04L1/0068—Rate matching by puncturing
- H04L1/0069—Puncturing patterns
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
- H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
- H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
- H04L1/1812—Hybrid protocols; Hybrid automatic repeat request [HARQ]
- H04L1/1819—Hybrid protocols; Hybrid automatic repeat request [HARQ] with retransmission of additional or different redundancy
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0009—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
Definitions
- the present invention relates to a method for forming a rate compatible code using high dimensional product codes and a computer-readable recording medium for recording a program that implements the method.
- the rate compatible code can provide various coding rates and coding performances by using product codes higher than two dimensions .
- Rate compatible codes can provide various coding rates and coding performances with a single encoder and decoder by applying various punctured patterns to parities added to correct errors in an error correction code. Because of this advantage, the rate compatible codes have been applied to adaptive coding and hybrid automatic repeat request (ARQ) in a time varying channel environment.
- ARQ adaptive coding and hybrid automatic repeat request
- the rate compatible codes are formed by applying an optimal punctured pattern to convolutional codes or turbo codes based on convolutional codes.
- U.S. Patent No. 6,430,722 and Korean Patent Laid-Open No. 2001-052246 disclose rate compatible coding methods applied to turbo codes based on convolutional codes. They suggest methods for generating codes with various coding rates by puncturing bits with an optimal punctured pattern.
- Hasung Kim and Gordon L. Stuber "Rate Compatible Punctured Turbo Coding for W-CDMA," ICPWC2000 , pp.143-147
- Hasung Kim and Gordon L. Stuber "Rate Compatible Punctured SCCC”
- VTC 2001 Fall Vol. 4, pp.2399-2403
- a transmission unit various coding rates are generated based on how many of the four parities are transmitted.
- decoding performance is enhanced through repeated decoding processes, because all the parities are formed using the same information word.
- the product code is serial concatenation of block codes with a block interleaver within them. Therefore, there are parities on parities (checks on checks) , and the check digits on check digits are the same whether the checks on rows or on columns are computed first.
- there have been a few schemes generating various coding rates using block codes although they are not rate compatible codes in the following references 6 and 7. However, they have problems that they only generate limited number of coding rates, that they may produce unacceptable performance with a single code or they cannot be decoded with a single code.
- Korean patent application No. 2001-56774 discloses an Iterative Decoding Method for Block Turbo Codes of Greater than Three Dimensions.
- an object of the present invention to provide a method for forming a rate compatible code that can provide various coding rates by using m-dimensional product codes, m being more than two, and a computer- readable recording medium for recording a program that implements the method.
- the product codes are divided by an information block and several parity blocks, and a punctured pattern is determined according to each parity block.
- a method for forming a rate compatible code using high dimensional product codes including the steps of: a) forming an m dimensional product code by using a systematic block code in a predetermined number of axes, wherein the in is a positive integer number; b) dividing the m dimensional product code into an information block and 2 ⁇ !
- the method includes the steps of: g-1) estimating a second weighting factor of W 2 for the identical combinations; g-2 ) selecting a third combination having largest weighting factor w ⁇ among the identical combinations; and g-3) obtaining second combinations of the combinations excepting identical combinations and corresponding new parity blocks which is adjacent to the combination and obtaining second combinations of the third combination and corresponding new parity blocks adjacent to the third combination.
- a computer-readable recording medium for recording a program that implements a method for forming a rate compatible code using high dimensional product codes, the method comprising the steps of: a) forming an m dimensional product code by using a systematic block code in a predetermined number of axes, wherein the m is a positive integer number; b) dividing the m dimensional product code into an information block and 2 m -l parity blocks; c) allocating indices to the divided blocks of the information block and 2 m -l parity blocks; d) obtaining combinations of the information block and corresponding parity blocks which are adjacent to the information block; e) estimating a first weighting factor j for the combinations; f) finding combinations having the same first weighting factor wi as identical combinations; h) if there is no combinations having the same first weighting factor Wi, forming rate compatible codes by using the combinations; and g) if there is combinations having the same first weighting factor i
- the computer readable record medium includes the steps of: g-1) estimating a second weighting factor of w 2 for the identical combinations; g-2) selecting a third combination having largest weighting factor w among the identical combinations; and g-3 ) obtaining second combinations of the combinations excepting identical combinations and corresponding new parity blocks which is adjacent to the combination and obtaining second combinations of the third combination and corresponding new parity blocks adjacent to the third combination.
- Fig. 1 shows the procedure for constructing classical 2 dimensional (2D) product codes using an ( n ⁇ , k ⁇ ) block code and an ( n 2 , k 2 ) block code in accordance with a preferred embodiment of the present invention
- Fig. 2 shows the configuration of a 3D product code constructed in accordance with a preferred embodiment of the present invention
- Figs. 3A and 3B show procedures of dividing m dimensional product code into several m dimensional blocks in accordance with a preferred embodiment of the present invention
- Fig. 4 is a flowchart describing the method for forming a rate compatible code using high dimensional product codes in accordance with the embodiment of the present invention
- Fig. 5 shows a procedure of forming RC codes in accordance with a preferred embodiment of the present invention.
- Fig. 1 shows the procedure for constructing classical 2 dimensional (2D) product codes using an ( n ⁇ f k ⁇ ) block code and an (n 2 , 2 ) block code in accordance with a preferred embodiment of the present invention
- Fig. 2 shows the configuration of a 3D product code constructed exactly the same way as in Fig. 1.
- the decoding performance can be improved but at the expense of the code rate and the data frame length.
- the degree of freedom can be increased in choosing the component codes in each axis, and this make it possible to generate RC codes with various code rates and coding gains .
- an m dimensional product code it is divided into several consisting m dimensional blocks of which axes lengths are information length of k or parity length of (n- k) .
- m dimensional product code there are four 2D blocks including an information block of I 2 and three parity blocks of P 2 1 to P 2 3 as shown in Fig. 3A.
- the 3D product code of Fig. 2 consists of eight 3D blocks including an information block of I 3 and 7 parity blocks of P 3 1 to P 3 7 as shown in Fig. 3B.
- an m dimensional product code consists of an information block and 2 m -l parity blocks. This is because the number of existing m dimensional blocks is exactly the same as the number of ways of allocating two different lengths of k and ( n-k) at each axis of in dimensional blocks.
- RC codes can be made by making several combinations of these consisting blocks.
- RC codes are formed by puncturing a part of parity blocks.
- each m dimensional block consisting the m dimensional product code is identified with a binary number, ( b ⁇ r b 2 , ..., b m ) using the following rule.
- 0 is assigned at b ⁇ if the length of the i-th axis in the block is kj_, and 1 at b ⁇ if the length is ( n ⁇ -k ⁇ ) .
- i is defined by the number of adjacencies in a given block combinations. For example, in the 2D product code of Fig. 3, there are four adjacencies of I 2 & P 2 1 , I 2 & P 2 2 , P 2 1 & P 2 3, and P 2 2 & P 2 3. If there are block combinations of the same value of i, w is used, wherein w 2 is defined by the amount of adjacencies as:
- a ⁇ is the amount of each adjacency, and it is the length for a 2D code and the area for a 3D code.
- RC block turbo codes is formed by using the following procedure in Fig. 4.
- Fig. 4 is a flowchart describing the method for forming a rate compatible code using high dimensional product codes in accordance with the embodiment of the present invention.
- rate compatible codes using high-dimensional product codes at step S201, an m-dimensional product code is formed by using a systematic block code in each dimension.
- the m dimensional product code is divided into an information block and 2 m -l parity blocks.
- the identifier (index) of each block, divided in the step S202 is expressed in a binary number.
- step S204 all combinations of the information block and parity blocks which are adjacent to the information block are found.
- the indices of the parity blocks in these combination must includes m- 1 zeros.
- step S205 for the combinations found in the step
- step S206 for a combination saved in the step 205, another parity block which is adjacent to this combination is found and a new combination is formed. If two blocks are adjacent in the m dimensional product code, then (m-1) positions of their binary representation should be in agreement.
- Wi is estimated for the combination found in the step S 206, and the result is saved.
- step 211 whether all possible combinations in the in dimensional product were investigated is checked. If all possible combinations were not investigated, then return to the step S206..
- combinations that can be formed by using the two-dimensional product code are six.
- weighting factors of wj . and w 2 are estimated to make rate compatible codes.
- Table 1 all the block combinations with which can be used as iterative decoder are selected.
- Two 3D product code is used. For examples, one with the same component code in each axis and the other with different component codes is used.
- the 3D code A in Table 1 is the product code of the (16,11) extended BCH codes
- the 3D code B is the product code of the (32,26), (16,11), and (8,4) extended BCH codes. Since the same component code in each axis in the 3D code A is used, there are 8 combinations in total. While the 3D code B have 18 variations. Weighting factors wi and w 2 are estimated for each punctured code, and they are shown in Table 1 with code rate, R.
- Code 1 to Code 3 can be seen as parallel-concatenated 2D block turbo codes
- Code 4 to Code 6 can be seen as serially concatenated 2D block turbo codes
- rest of the codes (Code 7 to Code 18) can be seen as punctured codes from serially concatenated 3D block turbo codes. Therefore it is required to estimate w 2 for Code 1 to Code 6 as the sum of the adjacent lengths, and for Code 7 to Code 18 as the sum of the adjacent areas.
- Code 7 shows almost the same BER performance to Code 4-6 even with a higher code rate, although they all use the same number of parity blocks as seen in Table 2. This is because Code 7 has larger value of i, i.e. more adjacencies. It would be shown the same in the case of 3D code B though the BER performance is not demonstrated in this paper. For example, in the case of 3D code B, Code 4-6 shows better BER performance than Code 7. In addition, Code 4 shows the best BER performance among Code 4-6 because it has the largest value of w 2 . This is applicable to all cases in Table 1. Table 1
- Table 2 shows an example of RC block turbo codes using the 3D code A, and it shows the code rate variation of each code and the corresponding bit error rate (BER) performance on an AWGN channel using a BPSK modulation scheme.
- a modified soft output Viterbi algorithm is used in the iterative decoder [S. Kim, W. S. Yang, and H. Lee, "Trellis-Based Decoding of High-Dimensional Block Turbo Codes," ETRI Journal, Vol. 25, No.l, Feb. 2003, pp.1-8].
- An uncoded BPSK scheme requires about 10 dB of bit energy to noise spectral density ratio ( E h /N 0 ) to achieve a BER of 10 " 6 .
- the simulation results of Table 2 shows that the RC block turbo code can produce a coding gain of from 5.0 dB up to 8.5 dB depending on the block combination (or puncturing scheme). It can be made more abundant variations if a different component code in each axis of the product code is used. For example 18 variations in the code rate are possible if the 3D code B in Table 1 is used. Table 2
- the RC product codes can be applied to a hybrid ARQ scheme.
- Table 3 illustrates the hybrid ARQ type II and III schemes with the RC product codes in Table 2.
- the Code 1 consisting of (I 3 , P 3 1, P 3 2 ) is transmitted at the first transmission. If the first transmission fails, the P 3 3 blocks are sent at the second transmission. If this fails again, P 3 4, P 3 5, P 3 6, and P 3 7 are transmitted at the successive transmissions.
- type- Ill scheme Code 4, Code 8, Code 12, Codel7 and Code 18 are sent at every retransmission in order after sending the Code 1 at the first transmission.
- Fig. 5 illustrates this. Table 3
- the rate compatible code forming method of the present invention can be embodied in the form of a program and stored in a computer-readable recording medium, such as CD-ROMs, RAMs, ROMs, floppy disks, hard disks and magneto- optical disks.
- a computer-readable recording medium such as CD-ROMs, RAMs, ROMs, floppy disks, hard disks and magneto- optical disks.
- the technology of the present invention can design a rate compatible code effectively by using a product code of a systematic block code, provides an encoding method that has various coding rates and coding performances by using various combinations of the consisting blocks.
- the technology of the present invention can be applied to various areas.
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US10/547,236 US7546509B2 (en) | 2003-02-27 | 2003-12-30 | Method for forming rate compatible code using high dimensional product codes |
EP03781078A EP1602032A4 (en) | 2003-02-27 | 2003-12-30 | Method for forming rate compatible code using high dimensional product codes |
AU2003288782A AU2003288782A1 (en) | 2003-02-27 | 2003-12-30 | Method for forming rate compatible code using high dimensional product codes |
JP2004568804A JP4087384B2 (en) | 2003-02-27 | 2003-12-30 | Rate-exchangeable code construction method using high-dimensional product code |
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KR10-2003-0012436A KR100461544B1 (en) | 2003-02-27 | 2003-02-27 | Rate Compatible Code using High Dimensional Product Codes |
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WO2014079479A1 (en) * | 2012-11-20 | 2014-05-30 | Huawei Technologies Co.,Ltd. | Method and device for encoding and decoding information bits in communications system |
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WO2006092681A2 (en) * | 2005-02-09 | 2006-09-08 | Nokia Siemens Networks Oy | Low complexity hybrid arq scheme based on rate compatible zigzag codes |
KR100729258B1 (en) * | 2005-12-07 | 2007-06-18 | 엘지전자 주식회사 | Mobile communications terminal for supporting extended link adaptation techniques and method thereof |
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US9397706B1 (en) * | 2013-10-09 | 2016-07-19 | Avago Technologies General Ip (Singapore) Pte. Ltd. | System and method for irregular multiple dimension decoding and encoding |
US9553611B2 (en) * | 2014-11-27 | 2017-01-24 | Apple Inc. | Error correction coding with high-degree overlap among component codes |
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- 2003-12-30 AU AU2003288782A patent/AU2003288782A1/en not_active Abandoned
- 2003-12-30 WO PCT/KR2003/002919 patent/WO2004077296A1/en active Application Filing
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Also Published As
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AU2003288782A1 (en) | 2004-09-17 |
JP4087384B2 (en) | 2008-05-21 |
KR20040077049A (en) | 2004-09-04 |
EP1602032A1 (en) | 2005-12-07 |
US20060190271A1 (en) | 2006-08-24 |
JP2006514801A (en) | 2006-05-11 |
KR100461544B1 (en) | 2004-12-18 |
EP1602032A4 (en) | 2011-09-21 |
US7546509B2 (en) | 2009-06-09 |
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