CN101150378A

CN101150378A - Interleaving scheme of 32APSK system for low-density checksum coding

Info

Publication number: CN101150378A
Application number: CNA2006101537599A
Authority: CN
Inventors: 张军坦; 吴智勇; 高鹏; 孙凤文
Original assignee: Academy of Broadcasting Science of SAPPRFT
Current assignee: Academy of Broadcasting Science of SAPPRFT
Priority date: 2006-09-18
Filing date: 2006-09-18
Publication date: 2008-03-26
Anticipated expiration: 2026-09-18
Also published as: CN101150378B

Abstract

This invention provides a method for interleaving bits through low density odd-even check coding (LDPC), which can get wanted compromise between error performance and error flat-bottom provided by the LDPC effectively.

Description

Interleaving scheme of 32APSK system of low-density parity check coding

Technical Field

The present invention relates to interleaving low density parity check ("LDPC") coded bits in a 32APSK modulation system. In particular, by allocating bits determining modulation symbols based on different bitdegrees (bit degrees), it is possible to effectively find a required compromise between error performance and error floor (error floor) provided by the LDPC code used.

Background

The authors investigated the performance of Modulation systems employing LDPC coding of 8PSK, as published in "Bit-Reliability Mapping in LDPC-Codes Modulation systems" (Bit-Reliability Mapping in LDPC code Modulation systems) by Yan Li and William Ryan, IEEE Communications Letters, vol.9, no.1, january 2005. With the proposed bit reliability mapping strategy, a performance improvement of about 0.15dB over the non-interleaved scheme is achieved. The authors also explain the reason for this improvement using an analysis tool called the EXIT chart. In the interleaving scheme, an interleaving method is considered, and the result shows that the method provides better performance than a non-interleaving system, that is, in a bit reliability mapping scheme, LDPC code bits with low reliability are mapped to modulation bits with low order, and bits with higher reliability are mapped to bits with high order.

Forward Error Control (FEC) coding is important to ensure reliable transmission of data over noisy channels in communication systems. Based on Shannon's theory, these channels have a certain capacity in bits per symbol at a certain signal-to-noise ratio (SNR), which is defined as Shannon limit (Shannon limit). One of the most important research areas in communication and coding theory is to design coding schemes that provide performance approaching the shannon limit with reasonable complexity. LDPC codes using Belief Propagation (BP) decoding have been shown to have controllable encoding and decoding complexity and can provide performance approaching the shannon limit.

LDPC codes were originally described by Gallager in 1960. The performance of LDPC codes is very close to the shannon limit. An (N, K) binary LDPC code having a code length N and a dimension K is defined by a parity check matrix H of (N-K) rows and N columns. Most elements of the matrix H are 0 and only a small part of the elements are 1, so the matrix H is sparse. Each row of the matrix H represents a checksum and each column represents a variable, e.g., a bit or a symbol. The LDPC code described by Gallager is regular, that is, the parity check matrix H has a constant row weight and column weight.

Regular LDPC codes can be extended to irregular LDPC codes where the row and column weights vary. The irregular LDPC code is specified by degree distribution polynomials (x) and c (x) that define degree distributions of variable nodes and check nodes, respectively. More specifically, make

And

wherein the variable d _vmax And d _cmax Respectively, a maximum variable node degree and a check node degree, and v _j (c _j ) Represents the fraction (fraction) of an edge (edge) emanating from a variable (check) node of degree j.

While irregular LDPC codes are more complex to represent and/or implement, it has been shown theoretically and empirically that irregular LDPC codes with appropriately selected degree distributions are superior to regular LDPC codes. FIG. 1 illustrates a parity check matrix diagram for an exemplary irregular LDPC code having a codeword length of six.

LDPC codes may also be represented by bipartite graphs, or Tanner graphs. In the Tanner graph, one set of nodes, called variable nodes (or bit nodes), corresponds to the bits of the codeword, while another set of nodes, called constraint nodes (or check nodes), corresponds to a set of parity check constraints defining the LDPC code. There are connecting edges between the bit nodes and the check nodes. Bit nodes and check nodes are considered to be adjacent or neighboring if they have connecting edges. In general, it is assumed that a pair of nodes is connected by no more than one edge.

FIG. 2 illustrates a bipartite graph representation of an irregular LDPC code as shown in FIG. 1. The codeword length of the LDPC code represented by fig. 1 is 6 and has 4 parities. As shown in fig. 1, there are a total of 9 1's in the parity check matrix representation of the LDPC code. Thus in the Tanner graph representation as in fig. 2, 6 bit nodes 201 are connected by 9 edges 203 to 4 check nodes 202.

LDPC codes can be decoded in a variety of ways, such as majority logic decoding and iterative decoding. LDPC codes are mostly logically decodable because of the structure of their parity check matrix. While most logical decoding requires minimal complexity and exhibits reasonably good decoding performance for some types of LDPC codes (e.g., euclidean geometry LDPC and projection geometry LDPC codes) that have relatively high column weights in the parity check matrix, iterative decoding methods gain more attention because they can achieve a better tradeoff between complexity and performance. Unlike most logical decoding, iterative decoding improves the reliability of each symbol by backtracking the received symbol based on constraints that define the pattern. In the first iteration, the iterative decoder uses only the channel output as input, producing a reliability output for each symbol. The reliability measure output for the decoded symbol at the end of each decoding iteration is then used as an input for the next iteration. The decoding process is terminated until a certain stop condition is satisfied. A final decision is then made based on the reliability measure of the decoded symbol output for the last iteration. Iterative decoding algorithms can be further divided into hard decision, soft decision and hybrid decision algorithms, depending on the different characteristics of the reliability metric used at each iteration. The corresponding common algorithms are iterative Bit Flipping (BF), belief Propagation (BP), and Weighted Bit Flipping (WBF) decoding algorithms, respectively. It has been demonstrated that the BP algorithm is capable of maximum likelihood decoding when the corresponding Tanner graph is acyclic, and thus the algorithm becomes the most popular decoding method. Only BP decoding of the LDPC code will be discussed in the present invention described below.

BP of LDPC codes is a type of information-passing decoding. The information sent along the edges of the graph is the log-likelihood ratios associated with the variable nodes corresponding to the codeword bits

In this expression, p ₀ And p ₁ Representing the probability of the relevant

bit taking values

0 and 1, respectively. BP decoding comprises two steps: a horizontal step and a vertical step. In the horizontal step, each check node c _m Will be based on dividing from bit b _n All but entry into check c _m The 'check-to-bit' information calculated from the 'bit-to-check' information is transmitted to the adjacent node b _n . In the vertical step, each bit node b _n Will be based on the division from check node c _m All but the incoming bit b _n Is sent to the adjacent check node c _m . These two steps are repeated until a usable codeword is found or the maximum number of iterations is reached.

Because of the significant performance of BP decoding, irregular LDPC codes are one of the best choices for many applications. Many communication and storage standards, such as DVB-S2/DAB, wireline ADSL, IEEE802.11n and IEEE802.16[4] [5] have adopted or are under consideration for the use of irregular LDPC codes. When considering the application of irregular LDPC codes in video broadcast systems, one often encounters problems due to error floor.

The error floor performance region of an LDPC decoder can be described by the error performance curve of the system. LDPC decoder systems generally exhibit a rapid decrease in the probability of error as the quality of the input signal increases. The resulting fault performance curve is generally referred to as a waterfall curve, and the corresponding region is referred to as a waterfall region. However, when a certain point is reached, the rate of decrease in the error probability corresponding to the improvement in the quality of the input signal is reduced, and the resulting flat error performance curve is called an error floor. Fig. 3 exemplarily illustrates FER performance curves of an irregular LDPC code including a waterfall region 301 and an error floor region 302.

Disclosure of Invention

An interleaving method is disclosed in which, for LDPC code bits having an arbitrary level of reliability, a part of low order modulation bits and a part of high order modulation bits are mapped. For a particular LDPC code structure and modulation method, the optimal division of low-order and high-order modulation bits can be determined by a theoretical algorithm called density evolution.

In one embodiment of the present invention, there is provided a digital communication system interleaving bits in a 32APSK modulation system using an FEC code, including: a transmitter capable of generating a signal waveform to a receiver via a communication channel, the transmitter having an information source that generates a set of discrete bits with a corresponding signal waveform; and an LDPC encoder for generating a signal according to the character table and feeding the signal to a signal mapper, wherein interleaving in the mapper is a non-continuous mapping capable of generating a minimum threshold value of the corresponding LDPC code predicted by density evolution.

By carefully selecting the check sum bit node degree distribution and the Tannner graph structure, the LDPC code has good threshold characteristics and can reduce the transmission power under the requirement of specific FER performance.

The threshold value of the LDPC code is defined as a minimum SNR value at which the bit error probability can be made arbitrarily small as the codeword length tends to be infinite.

Different applications have different requirements on the threshold and error floor of LDPC codes. Therefore, there is a need to devise a decision method by which the determined mapping scheme in a 32APSK system can provide the required threshold while keeping the error floor below a certain standard.

Drawings

The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

FIG. 1 is a parity check matrix representation of an exemplary irregular LDPC code of codeword length six;

FIG. 2 illustrates a bipartite graph representation of an irregular LDPC code as shown in FIG. 1;

FIG. 3 illustrates an exemplary FER performance curve including waterfalls and error floor regions of irregular LDPC codes;

FIG. 4 is an exemplary communication system employing an LDPC code and an interleaver/deinterleaver in accordance with an embodiment of the present invention;

FIG. 5 illustrates an example of the transmitter of FIG. 4;

FIG. 6 illustrates an example of the receiver of FIG. 4;

fig. 7 illustrates the bit mapping function in 32APSK modulation;

fig. 8 illustrates bit mapping of a 32APSK symbol.

Detailed Description

A detailed description is given of an encoding bit mapping method using an LDPC code and a program for performing the method according to an embodiment of the present invention, with reference to the accompanying drawings.

Although the present invention is described in terms of LDPC codes, it should be appreciated that bit labeling approach (bit labeling approach) may be used in other codes as well. In addition, this method can be implemented in non-coded systems.

Fig. 4 is a diagram of a communication system with an interleaver employing LDPC codes, according to an embodiment of the present invention. The communication system includes a transmitter 401 that generates a signal waveform that is transmitted over a communication channel 402 to a receiver 403. The transmitter 401 includes an information source that generates a discrete set of possible information. Each of these pieces of information corresponds to a certain signal waveform. The waveform enters the channel 402 and is degraded by noise. LDPC codes are employed to reduce interference introduced by channel 402. For a particular LDPC code and desired level of error floor, an interleaver and deinterleaver are used in the transmitter 401 and receiver 403, respectively, based on some interleaving rule that yields a good threshold.

Fig. 5 depicts an exemplary transmitter in the communication system of fig. 4, in which an LDPC code and interleaver are employed. LDPC encoder 502 encodes information bits from source 501 into an LDPC codeword. The mapping from each information block to each LDPC codeword is specified by the parity check matrix (or equivalent generator matrix) of the LDPC code. The LDPC codeword is interleaved and modulated into a signal waveform by an interleaver/modulator 503. These signal waveforms are sent to the transmit antenna 504 and propagated to the receiver as shown in fig. 6.

Fig. 6 depicts the exemplary receiver of fig. 4, in which an LDPC code and deinterleaver are employed. The signal waveform is received by a receiving antenna 601 and distributed to a demodulator/deinterleaver 602. The signal waveform is demodulated by a demodulator and deinterleaved by a deinterleaver, and then distributed to an LDPC decoder 603 that iteratively decodes the received message, and outputs an estimate of the transmitted codeword. The de-interleaving rules employed by the demodulator/de-interleaver 602 should match the interleaving rules employed by the interleaver/modulator 503. That is, the deinterleaving scheme should satisfy an anti-rule (anti-rule) of the interleaving scheme.

For a specific LDPC code and a 32APSK modulation scheme, optimal interleaving is defined as a non-continuous mapping means, and an optimal threshold value of the corresponding LDPC code predicted by density evolution can be generated.

As shown in FIG. 7, theThe 32APSK bit-to-symbol mapping circuit acquires five bits at a time (b) _5i ，b _5i+1 ，b _5i+2 ，b _5i+3 ，b _5i+4 ) And mapping them to I and Q values, where I =0,1, 2. The mapping logic is shown in fig. 8.

In 32APSK, for i ∈ i |0 ≦ i ≦ N _{ldpc_bits} -1, and imod5=0}, let

Is 5 bits that determine the ith symbol. We specify N _offset To define the number of bit maps for each coding efficiency. Given the level of LDPC codes and error floor, an optimal interleaving scheme is obtained through density evolution analysis. For a material with an efficiency of 2/3, ³ / ₄ 4/5, 5/6, 13/15, and 9/10 LDPC codes for i e { i |0 ≦ i ≦ N _{ldpc_bits} -1, and imod5=0} and j =0,1,2,3,4, the 32APSK interleaving rule is:

the number of bit offsets is listed in table 1 "interleave offset value in 32apsk": .

TABLE 1 interlace offset values in 32APSK

Efficiency of	N _offset
Efficiency of	N _offset	3/4	72
4/5	80	3/4	72
4/5	80	5/6	120
13/15	160	5/6	120
13/15	160	9/10	192

Although the present invention has been described by way of examples of preferred embodiments, it is to be understood that numerous other variations and modifications are possible within the spirit and scope of the invention. Therefore, it is the object of the appended claims to cover all such modifications and variations as come within the true spirit and scope of the invention.

Claims

1. A digital communication transmitter for interleaving LDPC coded bits in a 32APSK modulation system based on the following rules:

for i e { i |0 ≦ i ≦ N _{ldpc_bits} -1, and imod5=0} and j =0,1,2,3,4, where _ x _ is a rounding function that returns a maximum integer less than or equal to x, N _{ldpc_bits} =15360 codeword length of LDPC code used, and N _Offset Is an offset value for different coding efficiencies defined as:

efficiency of N _offset 3/4 72 4/5 80 5/6 120 13/15 160 9/10 192

。

2. A digital communication receiver employing an LDPC decoder, the receiver decoding interleaved LDPC coded bits in a 32APSK modulation mode based on the following rules:

for i e { i |0 ≦ i ≦ N _{ldpc_bits} -1, and imod5=0} and j =0,1,2,3,4, where _ x _ is the largest integer returned less than or equal to xRounding function, N _{ldpc_bits} =15360 codeword length of LDPC code used, and N _Offset Is an offset value for different coding efficiencies defined as:

efficiency of N _offset 3/4 72 4/5 80 5/6 120 13/15 160 9/10 192

。

3. A computer readable medium storing a computer program for executing a method of enabling interleaving of LDPC coded bit schemes based on the following rules in a 32APSK modulation system:

for i e { i |0 ≦ i ≦ N _{ldpc_bits} -1,qie2imod5=0} and j =0,1,2,3,4, where _ x _ is a rounding function that returns the largest integer less than or equal to x, N _{ldpc_bits} =15360 codeword length of LDPC code used, and N _Offset Is an offset value for different coding efficiencies defined as:

efficiency of N _offset 3/4 72 4/5 80 5/6 120 13/15 160 9/10 192

。