JP2001134455A - Error correcting and decoding device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-order dimensional torus node code for realizing error correction by preventing the generation of any erroneous correction due to the deterioration of an error rate ranging from 10-2 to 10-1 as much as possible. SOLUTION: A high-order dimensional torus node code is constituted as a high-order dimensional parity check code so that an error detecting function can be maintained as it is even after correction. Thus, it is possible to repeat decoding by gradually decreasing an identification value for the majority decision logic decoding of the code from the higher value. Therefore, it is possible to improve correcting capability by successively correcting an error while preventing the generation of any erroneous correction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention is used for correcting an error code. The present invention is suitable for use in digital communication systems and information processing and information storage systems. INDUSTRIAL APPLICABILITY The present invention is suitable for use in a semiconductor chip, circuit, device, or system having a function of correcting and removing an error generated by various factors.
The present invention can be used for a very wide range of digital information systems.

[0002]

2. Description of the Related Art Conventionally, many error correction codes have been developed and used. However, most error correction codes have an error rate of up to about 10 ^-3 and an error rate of 10 ^{-2 or} more. It is generally known that corrections increase errors as they worsen to 10 ^-1 .

[0003] The quality of conventional public communication is good, and the error rate rarely deteriorates below 10 ^-3 . However, today, as seen in mobile phones and mobile communications, there are many conditions under which communication quality deteriorates, and the quality during a call fluctuates greatly. In particular, recently, the transmission and use of digital information by radio have been advanced, but in many cases, poor communication quality often occurs due to the complicatedly changing characteristics of the propagation path of radio waves.

[0004] When digital information is transmitted under such poor conditions, there is a high possibility that a data packet or a data block contains an error, and if there are many errors, it may not be possible to correct the error with an error correction code. It happens that data packets have to be discarded. In order to avoid such a situation, there is a method of requesting retransmission of an erroneous packet. However, the system becomes complicated, and if there are many errors, the retransmitted packet may be erroneous again. Is limited.

[0005] In addition, the processing delay due to retransmission increases, which may not be practical. Therefore, even when the error rate is low, an error correction code having a good correction capability becomes important. Further, if the error can be corrected sufficiently, it becomes possible to make the retransmission system function effectively.

[0006] Or, in the future, there will be more cases of transmission and storage with encryption processing added for information security. In this case, errors in encryption / decryption will further increase significantly. Even if a 1-bit error exists in a data block, there is an error ripple effect that the error increases to almost half of the block in encryption / decryption. For this reason, a demand for a high-performance error correction code is increasing.

[0007]

As a code for extending the operation of the conventional code to a worse error rate, a high-dimensional torus knot code has been proposed. It has been clarified by theory and simulation that the high-dimensional torus knot code has a good error correction capability in a bad region having an error rate of 10 ^-2 to 10 ^-1 . However, its implementation method has not been realized until now.

[0008] Further, although realization by a software program is possible, there are the following problems. The error correction capability of the high-dimensional torus knot code changes depending on the number of dimensions and the size. In general, as the number of dimensions increases, the error correction capability also increases, but at the same time, the size of the code block also increases, and the number of code bits to be operated increases. When this is processed by software on the CPU, a plurality of code bits in the storage device cannot be accessed at the same time, so that it is necessary to repeat the access sequentially. As a result, there is a problem that as the error correction capability is increased, the processing speed is reduced.

Further, even when the number of dimensions is reduced and the error correction capability is relatively reduced, the encoding / decoding processing speed (throughput) per unit time is required due to the structure of performing the processing sequentially. Speed range may not be reached. Or high performance even when the required speed range is reached
There is a problem that the use of a CPU (processor: central processing unit) is required.

The present invention relates to a method of realizing high-speed encoding and decoding of a high-dimensional torus knot code by a hardware configuration such as an LSI, and particularly to a method of realizing a high-performance decoding apparatus. The realization by the hardware configuration is described in detail in another patent specification.

Further, as the error rate deteriorates to 10 ^-2 to 10 ^-1 , phenomena such as some errors not being corrected or non-error bits being erroneously corrected as errors appear.
Problems such as an increase in errors due to correction occur in general codes.

In order to solve this problem, in the present invention, by repeating majority logic decoding used for decoding and by optimally controlling the discrimination value, errors are gradually corrected without making erroneous corrections. We propose to improve the decoding performance to realize the error correction function.

[0013]

In a conventional code, a correction is made at the time of decoding in accordance with the rules or algorithms of the code. Therefore, even if an erroneous correction is made and an error is added and remains, However, there is a problem that a determination result that an error does not exist is output as long as the rule is met, and that subsequent error detection and correction cannot be performed.

On the other hand, since the high-dimensional torus knot code is constructed by increasing the parity check code, the error detection function is not lost even after error correction. That is, the parity check code used as the basis for error detection is not lost even if the bit is inverted many times.

Using this characteristic, a great feature that a decoding operation can be performed any number of times is present in a high-dimensional torus knot code. Even if an erroneous correction occurs, it is possible to detect erroneously corrected bits in the next repetition of decoding, and there is a possibility that correction will be performed together with correction of a new error. An improved error rate is realized.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. First, the structure of the high-dimensional torus knot code will be briefly described, and then the operation will be described in detail for one embodiment having three dimensions and three sizes. The case does not change even in the case of a large size.

The parity check is a code for detecting a 1-bit error by adding a 1-bit parity check bit to an m-1 bit binary code string to form an m-bit code string as a whole. Yes, and does not itself have correction capabilities. When the rule is an even parity rule, the value of the parity bit is determined and coded so that the number of codes indicating “1” in the m bits is an even number. In parity decoding, it is determined whether or not the number of codes indicating “1” is an even number for every predetermined m bits. If it is even, it is considered that the data has been transmitted correctly, and if it is odd, it is considered that there is an error of one bit or odd number of bits. In addition,
When two or even-bit errors are present at the same time, the number of 1s becomes the original even number, so that there is no error detection capability. However, when the number m of bits forming the parity is small, the error rate is often smaller than m, so that usually one-bit errors are almost common. Therefore, an error detection function can be realized. Since the parity check code has such a configuration, even if the number of bits in the parity check code is corrected several times, the parity check code has a property of continuing to have the parity check function. This is a property not found in general error correction codes.

Next, an m-bit code string can be considered in two dimensions. For example, consider a plane in which m-bit codes obtained by adding a 1-bit parity code to an m-1 bit code string are arranged in one row and m-1 columns are arranged in parallel. As a parity code in the column direction. Then, a two-dimensional code composed of m × m code arrays is configured. In this two-dimensional code, a parity check line is formed in each of the row and column directions, and m + m = 2m check lines can be employed. In the two-dimensional code, when an error is detected in a set of intersecting parity check lines, it is determined that there is an error at the intersection of the check lines, and one error is corrected by inverting the sign of the intersection. be able to.

If m-m two-dimensional codes based on parity check codes are further stacked m levels in a new direction, a three-dimensional code is formed. In the 3-dimensional codes, m ^3-bit code is located. Furthermore this m-bit generalizes parity check code string can be arranged in a n-dimensional consider code block of m ⁿ bits.

When the ^mn- bit code string configured as described above is arbitrarily transmitted to the transmission line in a serial format, adjacent bits in the n-dimensional three-dimensional code configuration are located close to each other on the transmission line. The case that comes out comes out. When burst-like errors are continuously mixed in such a code string, errors concentrate on a specific parity check line, so that error detection does not function and correction cannot be performed. Therefore, the important feature of the high-dimensional torus knot code is that when transmitting a ^mn- bit code string to the transmission line in a serial format, the transmission order is oblique to each dimension axis. It is. In other words, the code bits are sequentially transmitted diagonally to the code structure so that a plurality of bits adjacent at close intervals on the transmission path are not located on the same inspection line in each dimension. As a result, the burst errors on the transmission path are almost randomly distributed over the entire code block, and both the random errors and the burst errors can be corrected as random errors. The process of rearranging the transmission order is hereinafter referred to as an interleave process, and the process of restoring the rearrangement is referred to as a de-interleave process.

FIG. 2 shows a conceptual diagram of the code when the number of dimensions is 3 and the size is 3 for simplicity. In the case of this code, the information bits before coding are (3-1) ³ = 8 bits, and the code bits after coding are 3 ³ = 27 bits.
In an actual embodiment, a slightly larger value of m is used in consideration of transmission efficiency. Numerals 0 to 26 in FIG. 2 represent an example of the arrangement position (number) of each bit on the memory cell in the three-dimensional code structure. The shaded portion indicates the place where the information bit is arranged, and the place corresponding to the parity is not shaded.

FIG. 3 shows an example in which the binary information bit (0, 1) is stored. The information bits are stored only in the shaded portions in FIG.

FIG. 4 shows the information bits shown in FIG.
This shows the state (value) of all bits at the time when the value of the parity bit is determined and the coding is completed after performing the coding process according to the even parity rule. Parity bits are stored in places without shading, and it can be seen that the even-number parity rule is applied to all the check axes in three directions.

FIG. 5 shows the arrangement of bits after performing the interleaving process using the high-dimensional torus knot of the three-dimensional code shown in FIG. Note that there are several ways to form a torus knot, and FIG. 5 shows one example. Numerals 0 to 26 in FIG. 5 represent the sort destinations of the numerals 0 to 26 in FIG. 2 using the same three-dimensional code structure. The transmission of serial bits is performed according to the numbers in FIG.

FIG. 6 shows the configuration of the decoding apparatus as a processing flow diagram. A decoding unit configured to store input code data and perform deinterleaving processing;
E, a parity calculation unit F that performs parity calculation on the code data, an error detection unit G that determines whether there is an error in the code data bits from the result of the parity calculation by majority logic, and a result of the error detection unit It comprises an error correction unit H for correcting bits, an output unit J for outputting corrected information, and a control unit K for controlling the entire decoding device.

FIG. 7 shows the configuration of the input section E. Under the control of the control unit K, the input unit E serially receives the code data input from the outside to the memory cell C3 from the terminal T3.
At this time, the 27 memory cells constituting C3 are configured as a shift register serially connected by a connection group of the input unit, and are input from outside of one block.
Stores code data. The connection between the memory cells of the shift register is adjusted to the order of rearrangement of the code bits rearranged and rearranged at the time of transmission in the encoder, so that the deinterleave processing is completed at the same time as the end of data input. Has become. FIG. 8 shows a state (an example) of the value of the memory cell at the end of the input. That is, it is returned to the code arrangement of the high-dimensional three-dimensional structure in the encoding device (FIG. 4). In FIG. 8, 1 is added to the shaded portion.
It shows the case where one error exists. The data stored in the memory cell C3 is output as data L9 in a parallel format. Output L9 of C3 has the same contents as parity calculation unit
F and the error correction unit H are supplied in parallel. The outline of these operations will be described later.

FIG. 9 shows a configuration example of the parity calculation unit F.
The numbers in the squares at the top of FIG. 9 represent the cell numbers of the memory cell C3. The parity calculator F receives the contents of the memory cell output L9 of the input unit E in parallel, and calculates 27 exclusive ORs arranged in parallel to calculate the parity.
(EXOR) The corresponding contents are supplied to the arithmetic element X2, and the parity calculation result is output in parallel as L10. The EXOR operation element X2, which is a parity calculator, is supplied with the contents for the code bits on the check line required for parity calculation from the memory cell C3 through multiple connections, and performs parity calculation for all check lines simultaneously. ing. 9 and 10 show the parity check result for each check line number.

FIG. 8 shows an example of the result of the parity calculation. In this embodiment, since the even parity rule is adopted, a check result in which a parity error has occurred is shown when the calculation result is “1”. In FIG. 8, a check line in which a numeral is surrounded by a circle corresponds to an error parity check line. From these,
It is found that the position where the error has occurred is detected and can be corrected.

FIG. 10 shows a configuration example of the error detection unit G. The error detector G has a configuration in which 27 majority logic circuits M1 are arranged in parallel. One majority logic circuit M1 is
There is a number corresponding to one of the bits to be checked and the same number as the block length. In the majority logic circuit corresponding to the bit for which an error is detected, three corresponding parity calculation results of the number of dimensions are added as an input L10 from the parity calculation unit F, and whether the bit is an error or not is determined. Judge. Here, the operation of the majority logic circuit M1 will be described. The bit is detected as an error by a three-axis parity check line of the number of dimensions passing through the position.
The number of parity check line results input to the majority logic circuit M1 is the same as the number of dimensions, ie, number 3. Therefore, the number of errors in the parity check line for a certain bit is a number between 0 and 3. Here, the majority logic circuit M1 is based on a predetermined 2
Is compared with the number of parity check line errors with respect to the threshold value of 3 or 3. If the number of parity errors equal to or greater than the threshold value is input, the bit is determined to be erroneous and the error detection result corresponding to the bit is set to " 1 ”. If no error is detected, the detection result is set to “0”. This inspection output is indicated by a triangle in FIG.

The 27 majority logic circuits M1 are arranged in parallel and operate in parallel, so that error detection for all code bits is performed simultaneously with one time clock.

As shown in FIG. 8, when there is one error in the code data block, all three check lines passing through the corresponding bit detect a parity error. Therefore, the number of input errors from the parity calculation unit F to the majority logic circuit M1 is 3, and the majority logic circuit M1 determines that the bit is an error, and the detection result “1” is output as a correction signal to the error correction unit H.
Is output as L11. When a plurality of errors exist in a code block, a plurality of errors may exist on the same check line at the same time. For example, if an even number of errors occur on the same check line, the check line cannot detect an error, and the number of error check lines may be two instead of three.

FIG. 11 shows the relationship between the error correction section H, the input section E and the error detection section G. In the error correction section H, the input section E
And two outputs from the error detection unit G to perform error correction, and 27 exclusive-OR (EXOR) operation elements X3 are arranged in parallel. The error correction unit H includes the code data L9 input from the input unit E under the control of the control unit and the error detection unit G
By performing an EXOR operation on the error detection result L11, the error is corrected, and the corrected data is output to L12. 27 E
Since the XOR operation elements X3 are arranged in parallel and operated in parallel, error correction for all code bits can be performed simultaneously here.

The output section J is composed of 27 memory cells C4 and has a function of storing code data after error correction has been performed. Under the control of the control unit K, the output L12 from the error correction unit H is received in parallel and stored in the memory cell C4. Of the code data stored in C4, memory cells corresponding to information bits are serially connected. The output unit J outputs only the corrected information bit data serially as L13 from the terminal T4. This is the corrected code block.

The control unit K is connected to the input unit E via a control line L14.
And the parity calculation unit F via the control line L15 and the control line L16
And an error correction unit H via a control line L17.
Is controlled through the control line L18. Specifically, the parity calculation is started after confirming that all the code data has been stored, the error detection is started after the parity calculation is completed, and the error correction is started after the error detection is completed. After that, confirm that the error correction has been completed,
It has a function to make the output unit J ready for output.

The above description has been given of a case of a simple three-dimensional size 3, but it is to be noted that the structure of the description is similarly applied to a code having a higher dimension and a larger size. It should be noted that, other than the basic configuration of the description, there are many other variations similar to those of the description with respect to the specific parts.

However, the present invention employs a configuration and operation for repeating decoding in order to improve decoding characteristics.

FIG. 12 shows an error other than the bit in s out of n check lines passing through the bit for the bit to be checked and determined when the error increases in the code block. Show the case. Here, the identification value of the majority logic circuit is I.

In FIG. 12, the number of error detection check lines is s as shown in FIG. 12 for two cases, that is, a correct bit and an error bit, regardless of the same error arrangement in the code configuration. And (ns). This is because if the bit is an error, two other error-free test lines are not detected because they are two errors, and n-s test lines with no error are detected as parity errors. Here, when the number of error detection test lines is equal to or greater than I, it is determined that an error has occurred, and otherwise, it is determined to be correct. FIG. 13 shows the result of such a determination in which the number of erroneous parity check lines with respect to the identification value I is represented on the vertical axis. A correct bit is determined as an error (erroneous correction) with reference to FIG. 12 when the n test lines penetrating the bit include an error test line of I or more,
In FIG. 13, the area above the straight line satisfying s ≧ I is incorrectly corrected.

The error bit is not correctly determined as an error, but is determined to be correct (missing an error) when n−s ≦ I−1. The region in this case is also shown in FIG. 13, but is a region on a straight line opposite to the direction of the erroneous correction.

The remaining error is the sum of the error caused by the erroneous correction and the missed error. However, the average probability that the bit is erroneous is the error rate p of the input data.
Therefore, if p = 10 ^-2 to 10 ^-1 , if the relevant bit is correct, it is much more numerous than if it is an error, so that the number of errors remaining due to erroneous correction is much greater than the number of errors due to oversight Will be.

FIG. 13 shows the number Se of error check lines which is erroneously corrected and the number Sm of check lines due to oversight for a certain identification value It. Using Se and Sm, the probability of erroneous correction and the probability of being overlooked are obtained from the occurrence distribution of the number of errors. Assuming that errors are sufficiently diffused by the interleaving by the torus knot, the occurrence of errors in one check line is independent of each other, and the probability of occurrence of errors is smaller than 1 as follows. Expressed as a distribution. The average error probability of each test line is (m−1) bits on one test line excluding the bit concerned, and is the average error probability p of each bit.
The average probability that one test line is an error test line is (m-1) p
(≪1). Therefore, the probability of the s inspection lines being erroneous is indicated by the Poisson distribution shown on the left side of FIG. The sum of the probabilities of the number of occurrences larger than Se and Sm in this distribution is given as an erroneous correction and a missed probability.

In consideration of the correct probability (1−p) of the bit and the error probability p, the residual error to which both errors are added becomes minimum at a certain discrimination value as shown in the lower diagram of FIG. This value gives the optimal identification value. This value is smaller than the discrimination value at which the error correction and the oversight error at the intersection of the two straight lines are equal.
As a result, the higher the discrimination value depends.

By the way, according to the embodiment of the present code, the decoding operation of each stage is executed in a bit-parallel manner for each time clock, so that high-speed decoding with a small number of time clocks compared to the code block length is realized. Is done. Therefore, it is possible to repeat the decoding operation without causing a practical obstacle. In this iterative decoding, the identification value is initially set to a high value, error correction is reduced, and the error bit correction operation proceeds little by little. If the number of erroneous corrections is small, the probability of oversight is increased. However, since erroneous correction causes a larger number of errors, such setting leads to better decoding characteristics.

As the number of errors decreases, that is, as the decoding is repeated, the true decision probability increases and the false decision probability decreases, so that the correction operation improves. FIG. 14 shows a true decision probability [] and a false decision probability [F] for a five-dimensional size 5 code with the error rate p as a parameter. This shows that when the error rate increases, the discrimination value can be reduced to about I = 2 to achieve a large error correction.

FIG. 15 shows how the error rate is improved by repeating decoding of a code of four-dimensional size 5. Here, the pattern of the change of the discrimination value at each repetition is shown as a parameter on the right side of the figure, but by setting an appropriate change of the discrimination value, the improvement of the error rate over several digits or the improvement of zero error can be realized. Is shown to gain. In addition, it is shown that a good result can be obtained by returning to the maximum identification value (the number of dimensions) in the middle and sequentially performing correction while erasing the erroneous correction that has occurred.

In the case where the initial error rate is as poor as about 0.05 or more, there is a case where even if the identification value is changed, the improvement of the error is saturated and limited. This means that if there are many mistakes,
This is because a case where errors are arranged in the same high-dimensional rectangular parallelepiped as the code appears and cannot be detected. That is, two errors are present on each check line, resulting in an error pattern that cannot be seen on the parity check line. Also,
It is also shown that the error arrangement of a structure obtained by dividing the invisible error rectangular parallelepiped structure into two is a pattern in which an error is detected but cannot be corrected. For these reasons, error correction is limited.

In the specific circuit configuration, FIG.
As shown in the figure, the information of the corrected bit, which is the output L12 of the error correction unit, is fed back to the memory cell C3 of the input unit E, and the input code block is corrected by rewriting the contents thereof. The decoding characteristics are improved by repeating the operation.

L19 is a signal for setting an identification value of the majority logic circuit. The identification value control unit Q outputs an identification value designated each time by controlling the decoding repetition from the control unit K. Using the L10 parity check line information, Q incorporates a function algorithm that sets the identification value in accordance with the number of errors in the code block and the state of the change in the improvement of the error at each iteration. Realization becomes possible.

[0049]

As described above, according to the present invention,
For a high-dimensional torus knot code that can correct a bad code block with an error rate of about 10 ^-2 to 10 ^-1 , add a method for repeatedly executing decoding and a method for controlling the identification value of the majority logic circuit related to the decoding. Thus, it is possible to greatly improve the code error rate at a high speed only by sacrificing a small processing time as compared with inputting / outputting a code block to / from a decoding device. According to the present invention, a great improvement in communication quality and an improvement in the performance of a device system are expected in various applications such as a mobile wireless device, which have been difficult in the past.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of an improved decoding device.

FIG. 2 is a conceptual diagram of a high-dimensional torus knot code having three dimensions and a size of three.

FIG. 3 is a conceptual diagram of a code to which information data before encoding is input.

FIG. 4 is a diagram showing an example of all code bits including parity after encoding;

FIG. 5 is a diagram showing a transmission order of code bits after interleaving.

FIG. 6 is a functional block diagram of a decoding device.

FIG. 7 is a diagram showing a decoding device input unit;

FIG. 8 is a diagram showing a state of a parity check line when an error is mixed;

FIG. 9 is a diagram illustrating an example of a decoding device parity calculator.

FIG. 10 is a diagram illustrating an example of a decoding device error detection unit.

FIG. 11 is a diagram illustrating an example of a decoding device error correction unit and an output unit.

FIG. 12 is a diagram showing the number of detection inspection lines s and detection characteristics with respect to an identification value I;

FIG. 13 is a diagram showing a parity check line error s and a majority logic decoding characteristic for an identification value I;

FIG. 14 is a diagram showing a probability of being true and a probability of being false in majority logic judgment for an identification value I;

FIG. 15 is a diagram showing an improvement in an error rate by repeating decoding.

[Explanation of symbols]

 E Decoder input unit F Decoder parity calculator G Decoder error detector H Decoder error correction unit J Decoder output unit K Decoder control unit Q Decoder identification value control unit

Claims (4)

[Claims] 1. A high-dimensional torus knot, wherein the parity function is preserved irrespective of any correction of bits in the parity check line, since the high-dimensional torus knot code is a code obtained by increasing the parity check code. A decoding device for a high-dimensional torus knot code, characterized in that the code itself is a code that retains the correction function even after correction, thereby improving the correction capability by repeated correction. 2. In the iterative correction operation, the identification value of majority logic decoding is repeated and the correction is repeated while gradually changing the identification value from a higher value to a lower value. A decoding device for a high-dimensional torus knot code, wherein the decoding capability is improved. 3. The decoding operation according to claim 1, wherein the identification value is returned to a higher value halfway, and the decoding operation is performed while erasing errors caused by erroneous correction, thereby realizing higher correction capability. A decoding device for a high-dimensional torus knot code. 4. An appropriate identification value changes depending on a remaining error (error rate). Therefore, a remaining error is detected and evaluated based on the number of error parity check lines, and the identification value is controlled based on a result of the determination. A decoding device for a high-dimensional torus knot code.