JP2001136077A - Error correction encoder and decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit method that realizes high-speed encoding and decoding processing by means of large scale circuit integration with respect to proposals of a higher dimensional torus knot code that can correct errors at a deteriorated error rate of 10-2 to 10-1 whose realization having conventionally been difficult. SOLUTION: Bits of the higher dimensional torus knot code configure serial blocks and the higher dimensional torus knot code maintains independence of the errors in each bit. A high-speed operation can be realized by utilizing a circuit configuration arranging serial bit strings into parallel that is characterized in a configuration to realize the encoding and decoding processing for each of parallel bits within one time clock at the same time. Concretely, this invention contrives a means that uses wiring connection for arrangement conversion of a plurality of the bits and supply of arithmetic results among memory elements and logic circuits in the large scale integrated circuit so as to realize the simplified circuit and the parallel operations.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention is used for correcting an error code. The present invention is suitable for use in digital communication systems and information processing and information storage systems. INDUSTRIAL APPLICABILITY The present invention is suitable for use in a semiconductor chip, circuit, device, or system having a function of correcting and removing an error generated by various factors.
The present invention can be used for a very wide range of digital information systems.

[0002]

2. Description of the Related Art Conventionally, many error correction codes have been developed and used. However, most error correction codes have an error rate of up to about 10 ^-3 and an error rate of 10 ^{-2 or} more. It is generally known that corrections increase errors as they worsen to 10 ^-1 .

[0003] The quality of conventional public communication is good, and the error rate rarely deteriorates below 10 ^-3 . However, today, as seen in mobile phones and mobile communications, there are many conditions under which communication quality deteriorates, and the quality during a call fluctuates greatly. In particular, recently, the transmission and use of digital information by radio have been advanced, but in many cases, poor communication quality often occurs due to the complicatedly changing characteristics of the propagation path of radio waves.

[0004] When digital information is transmitted under such poor conditions, there is a high possibility that a data packet or a data block contains an error, and if there are many errors, it may not be possible to correct the error with an error correction code. It happens that data packets have to be discarded. In order to avoid such a situation, there is a method of requesting retransmission of an erroneous packet. However, the system becomes complicated, and if there are many errors, the retransmitted packet may be erroneous again. Is limited.

[0005] In addition, the processing delay due to retransmission increases, which may not be practical. Therefore, even when the error rate is low, an error correction code having a good correction capability becomes important. Further, if the error can be corrected sufficiently, it becomes possible to make the retransmission system function effectively.

[0006] Or, in the future, there will be more cases of transmission and storage with encryption processing added for information security. In this case, errors in encryption / decryption will further increase significantly. Even if a 1-bit error exists in a data block, there is an error ripple effect that the error increases to almost half of the block in encryption / decryption. For this reason, a demand for a high-performance error correction code is increasing.

[0007]

As a code for extending the operation of the conventional code to a worse error rate, a high-dimensional torus knot code has been proposed. It has been clarified by theory and simulation that the high-dimensional torus knot code has a good error correction capability in a bad region having an error rate of 10 ^-2 to 10 ^-1 . However, its implementation method has not been realized until now.

[0008] Further, although realization by a software program is possible, there are the following problems. The error correction capability of the high-dimensional torus knot code changes depending on the number of dimensions and the size. In general, as the number of dimensions increases, the error correction capability also increases, but at the same time, the size of the code block also increases, and the number of code bits to be operated increases. When this is processed by software on the CPU, a plurality of code bits in the storage device cannot be accessed at the same time, so that it is necessary to repeat the access sequentially. As a result, there is a problem that as the error correction capability is increased, the processing speed is reduced.

Further, even when the number of dimensions is reduced and the error correction capability is relatively reduced, the encoding / decoding processing speed (throughput) per unit time is required due to the structure of performing the processing sequentially. Speed range may not be reached. Or high performance even when the required speed range is reached
There is a problem that the use of a CPU (processor: central processing unit) is required.

The present invention relates to a means for mounting a high-performance high-dimensional torus knot code at a high speed and in a limited number of logic elements. The present invention performs an encoding process and a decoding process not in a sequential process but in a parallel process, so that an error rate is 10 ⁻² to 10 ^−1.
High performance that can be used in the poor area, and
An object of the present invention is to provide an error correction device that operates at high speed. An object of the present invention is to provide an LSI chip, circuit, and device that can perform encoding and decoding processing in real time without requiring a high-performance CPU in devices such as mobile phones and mobile communication devices. And

[0011]

As previously proposed, in order to correct a bad error rate, a parity check line is combined with a high dimension to form a high-dimensional three-dimensional structure. A method for improving the correction capability is shown.

It is known that randomizing the occurrence of errors by scrambling or spreading them is important for both random errors and burst errors.

For this reason, in the proposed code, the transmission order is formed such that the code order to be transmitted for the code bits of the high-dimensional three-dimensional structure is diagonal to all of the three-dimensional axes. This is similar to a string of sign bits forming a high-dimensional torus knot and wrapping around the sign of a high-dimensional three-dimensional structure.

[0014] Many random and burst errors generated in the transmission or accumulation process, or many errors composed of both, are generated at the stage where the transmission code block is reconstructed on the decoding side as the original high-dimensional three-dimensional structure code. The parity check lines composed of axes are randomly distributed. For this reason, this code has a very good spreading and interleaving function. Therefore, errors on each parity check line on the decoding side are regarded as random and independent. This effect is more effective for a high-dimensional code having a longer block length.

The determination as to whether each bit is erroneous or not is made by majority logic determination using n independent parity check lines penetrating each bit. When a large number of parity check lines out of n are determined to be erroneous, it is determined that there is a high possibility that the bit is erroneous. Therefore, the value of the bit can be inverted and corrected.

As described above, the means for implementing error correction coding is characterized by a high-dimensional cubic structure, and the transmission order of the codes is a torus-like knot wound around the diagonal direction of the cube. And Sign dimension n
If the size m of one side of the code is determined, the position of each information bit and parity check bit and the position in transmission clearly correspond to each other and are determined. By utilizing this fact and realizing the LSI, if the arrangement order is converted by connection, the circuit operation is simplified, and the parallel operation of each bit becomes possible, and the operation speed is increased.

In the decoding, the same circuit configuration can be used to convert the arrangement of codes in the original three-dimensional structure from the transmission bit string. In addition, each parity check can be performed simultaneously by a multiple (m) input exclusive OR circuit by wiring. An inspection output is obtained, and the subsequent error detection determination is simultaneously determined in one time cycle by configuring the n-input majority logic circuit by wiring.

In comparison with the case of realizing with software using a CPU as described above, the hardware configuration on the LSI
A remarkable improvement in operating speed is realized by the parallel operation.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described with reference to FIGS. First, the configuration of the high-dimensional torus knot code will be briefly described, and then the operation will be described in detail for one embodiment in which the number of dimensions is three and the size is three. The same is true for large sizes.

The parity check is a code for detecting a 1-bit error by adding a 1-bit parity check bit to an m-1 bit binary code string to form an m-bit code string as a whole. Yes, and does not itself have correction capabilities. When the rule is an even parity rule, the value of the parity bit is determined and coded so that the number of codes indicating “1” in the m bits is an even number. In parity decoding, it is determined whether or not the number of codes indicating “1” is an even number for every predetermined m bits. If it is even, it is considered that the data has been transmitted correctly, and if it is odd, it is considered that there is an error of one bit or odd number of bits. In addition,
When two or even-bit errors are present at the same time, the number of 1s becomes the original even number, so that there is no error detection capability. However, when the number m of bits forming the parity is small, the error rate is often smaller than m, so that usually one-bit errors are almost common. Therefore, an error detection function can be realized.

Next, an m-bit code string can be considered in two dimensions. For example, consider a plane in which m-bit codes obtained by adding a 1-bit parity code to an m-1 bit code string are arranged in one row and m-1 columns are arranged in parallel. As a parity code in the column direction. Then, a two-dimensional code composed of m × m code arrays is configured. In this two-dimensional code, a parity check line is formed in each of the row and column directions, and m + m = 2m check lines can be employed. In the two-dimensional code, when an error is detected in a set of intersecting parity check lines, it is determined that there is an error at the intersection of the check lines, and one error is corrected by inverting the sign of the intersection. be able to.

If m-m two-dimensional codes based on the parity check codes are further stacked m levels in a new direction, a three-dimensional code is formed. In the 3-dimensional codes, m ^3-bit code is located. Furthermore this m-bit generalizes parity check code string can be arranged in a n-dimensional consider code block of m ⁿ bits.

When the ^mn- bit code string configured as described above is arbitrarily transmitted to the transmission path in a serial format, adjacent bits in the n-dimensional three-dimensional code configuration are located close to each other on the transmission path. The case that comes out comes out. When burst-like errors are continuously mixed in such a code string, errors concentrate on a specific parity check line, so that error detection does not function and correction cannot be performed. Therefore, the important feature of the high-dimensional torus knot code is that when transmitting a ^mn- bit code string to the transmission line in a serial format, the transmission order is oblique to each dimension axis. It is. In other words, the code bits are sequentially transmitted diagonally to the code structure so that a plurality of bits adjacent at close intervals on the transmission path are not located on the same inspection line in each dimension. As a result, the burst errors on the transmission path are almost randomly distributed over the entire code block, and both the random errors and the burst errors can be corrected as random errors. The process of rearranging the transmission order is hereinafter referred to as an interleave process, and the process of restoring the rearrangement is referred to as a de-interleave process.

FIG. 2 is a conceptual diagram showing the configuration of the code when the number of dimensions is 3 and the size is 3 for simplicity. In the case of this code, the information bits before coding are (3-1) ³ = 8 bits, and the code bits after coding are 3 ³ = 27 bits.
In an actual embodiment, a slightly larger value of m is used in consideration of transmission efficiency. Numerals 0 to 26 in FIG. 2 represent an example of the arrangement position (number) of each bit on the memory cell in the three-dimensional code structure. The shaded portion indicates the place where the information bit is arranged, and the place corresponding to the parity is not shaded.

FIG. 3 shows an example in which the binary information bit (0, 1) is stored. The information bits are stored only in the shaded portions in FIG.

FIG. 4 shows the information bits shown in FIG.
This shows the state (value) of all bits at the time when the value of the parity bit is determined and the coding is completed after performing the coding process according to the even parity rule. Parity bits are stored in places without shading, and it can be seen that the even-number parity rule is applied to all the check axes in three directions.

FIG. 5 shows the arrangement of bits after performing the interleaving process using the high-dimensional torus knot of the three-dimensional code shown in FIG. Note that there are several ways to form a torus knot, and FIG. 5 shows one example. Numerals 0 to 26 in FIG. 5 represent the sort destinations of the numerals 0 to 26 in FIG. 2 using the same three-dimensional code structure. The transmission of serial bits is performed according to the numbers in FIG.

FIG. 1 shows the configuration of the encoding apparatus. As shown in FIG. 1, the encoding apparatus receives an information bit group, which is data before encoding, by an input unit A for inputting and storing the information bit group, a parity generation unit B for outputting a parity bit from the information bit group, and an information bit and a parity bit. Storing the added sign bit group,
Output unit that performs output while performing interleave processing
C, and a control unit D that controls the entire encoding device.

The input section A will be described. Under the control of the control unit, the input unit A serially receives data from the terminal T1 connected to the outside. The input unit A is configured as a shift register in which eight memory cells C1 are serially connected, and sequentially stores data input from the outside. FIG. 3 shows a state at the time when the input is completed. FIG.
The data is stored in the shaded portion in the middle. The stored data is output as data L2 in a parallel format. The output L2 of the input unit A has the same contents as the parity generation unit B.
And the output unit C. The connection to the parity generation unit B will be described later. Input part A to part of output part C
Information content is connected as it is.

The parity generator B will be described. The parity generation unit B receives the output L2 of the input unit A in parallel from the memory cell C1 under the control of the control unit D, and arranges 19 multi-input exclusive-OR (EXOR) operation elements X1 for calculating parity in parallel. Then, the corresponding input is added. Each logical element outputs a logical sum modulo 2, and the output indicates a parity operation result. The parity operation result is output in parallel to the corresponding memory cell of the output memory cell C2 of the output unit C as L3. As shown in FIG. 1, each signal of the output L2 of the input unit A is connected to a plurality of EXOR operation elements X1.
, And inputs necessary for all the EXOR operation elements X1 are supplied from the memory cell C1 by connection in a corresponding order. Therefore, it is possible to output all parity bits at the same time. The parity bits output here are stored in the corresponding positions of the unshaded memory cells in FIG.

The output section C will be described. The output section C is composed of 27 memory cells C2 corresponding to the code block length. Under the control of the control unit D, the output L2 from the input unit A and the parity operation result L3 output from the parity generation unit B are written and stored in the corresponding memory cell C2 in parallel. The output of the memory cell C2 is also connected as a shift register, and is sent out through the terminal T2 of the encoding device. When a code block is transmitted, it is output serially. The connection of the memory cells as the shift register is adapted to the order of rearrangement of the code bits, thereby contributing to high-speed operation as a structure in which the interleave processing is performed simultaneously with the transmission of the bits.

The control unit D controls the input unit A via a control line L5,
The parity generation unit B is controlled via a control line L6, and the output unit C is controlled via a control line L7. Specifically, after confirming that all the data has been input to the input unit A, an instruction is issued to the parity generation unit B, and after the parity generation is completed, the output unit C is set to an output-enabled state. .

Next, the configuration of the decoding apparatus is shown in FIG. 6 as a process flow diagram. The decoding device stores an input code data and performs de-interleaving processing on an input unit E, performs a parity calculation on the code data, and a parity calculation unit F. An error detection unit G that determines whether there is any data by majority logic, an error correction unit H that corrects bits according to the result of the error detection unit, an output unit J that outputs corrected information, and controls the entire decoding device It is composed of a control unit K.

FIG. 7 shows the configuration of the input section E. Under the control of the control unit K, the input unit E serially receives the code data input from the outside to the memory cell C3 from the terminal T3.
At this time, the 27 memory cells constituting C3 are configured as a shift register serially connected by a connection group of the input unit, and are input from outside of one block.
Stores code data. The connection between the memory cells of the shift register is adjusted to the order of rearrangement of the code bits rearranged and rearranged at the time of transmission in the encoder, so that the deinterleave processing is completed at the same time as the end of data input. Has become. FIG. 8 shows a state (an example) of the value of the memory cell at the end of the input. That is, it is returned to the code arrangement of the high-dimensional three-dimensional structure in the encoding device (FIG. 4). In FIG. 8, 1 is added to the shaded portion.
It shows the case where one error exists. The data stored in the memory cell C3 is output as data L9 in a parallel format. Output L9 of C3 has the same contents as parity calculation unit
F and the error correction unit H are supplied in parallel. The outline of these operations will be described later.

FIG. 9 shows a configuration example of the parity calculation unit F.
The numbers in the squares at the top of FIG. 9 represent the cell numbers of the memory cell C3. The parity calculator F receives the contents of the memory cell output L9 of the input unit E in parallel, and calculates 27 exclusive ORs arranged in parallel to calculate the parity.
(EXOR) The corresponding contents are supplied to the arithmetic element X2, and the parity calculation result is output in parallel as L10. The EXOR operation element X2, which is a parity calculator, is supplied with the contents for the code bits on the check line required for parity calculation from the memory cell C3 through multiple connections, and performs parity calculation for all check lines simultaneously. ing. The diamonds in FIG. 9 indicate the parity check results for each check line number.

FIG. 8 shows an example of the result of the parity calculation. In this embodiment, since the even parity rule is adopted, a check result in which a parity error has occurred is shown when the calculation result is “1”. In FIG. 8, a check line in which a numeral is surrounded by a circle corresponds to an error parity check line. From these,
It is found that the position where the error has occurred is detected and can be corrected.

FIG. 10 shows a configuration example of the error detection unit G. The error detector G has a configuration in which 27 majority logic circuits M1 are arranged in parallel. One majority logic circuit M1 is
There is a number corresponding to one of the bits to be checked and the same number as the block length. In the majority logic circuit corresponding to the bit for which an error is detected, three corresponding parity calculation results of the number of dimensions are added as an input L10 from the parity calculation unit F, and whether the bit is an error or not is determined. Judge. Here, the operation of the majority logic circuit M1 will be described. The bit is detected as an error by a three-axis parity check line of the number of dimensions passing through the position.
The number of parity check line results input to the majority logic circuit M1 is the same as the number of dimensions, ie, number 3. Therefore, the number of errors in the parity check line for a certain bit is a number between 0 and 3. Here, the majority logic circuit M1 compares the number of parity check line errors with a predetermined threshold value of 2 or 3, and when the number of parity errors equal to or greater than the threshold value is input, the bit is determined to be erroneous. If there is, the error detection result corresponding to the bit is set to “1”. If no error is detected, the detection result is set to “0”. This inspection output is indicated by a triangle in FIG.

The 27 majority logic circuits M1 are arranged in parallel and operate in parallel, so that error detection for all code bits is performed simultaneously with one time clock.

As shown in FIG. 8, when there is one error in the code data block, all three check lines passing through the corresponding bit detect a parity error. Therefore, the number of input errors from the parity calculation unit F to the majority logic circuit M1 is 3, and the majority logic circuit M1 determines that the bit is an error, and the detection result “1” is output as a correction signal to the error correction unit H.
Is output as L11. When a plurality of errors exist in a code block, a plurality of errors may exist on the same check line at the same time. For example, if an even number of errors occur on the same check line, the check line cannot detect an error, and the number of error check lines may be two instead of three. As for the problem of correction when there are multiple errors, special consideration and ingenuity are required, so another patent is assigned.

FIG. 11 shows the relationship between the error correction section H, the input section E and the error detection section G. In the error correction section H, the input section E
And two outputs from the error detection unit G to perform error correction, and 27 exclusive-OR (EXOR) operation elements X3 are arranged in parallel. The error correction unit H includes the code data L9 input from the input unit E under the control of the control unit and the error detection unit G
By performing an EXOR operation on the error detection result L11, the error is corrected, and the corrected data is output to L12. 27 E
Since the XOR operation elements X3 are arranged in parallel and operated in parallel, error correction for all code bits can be performed simultaneously here.

The output section J is composed of 27 memory cells C4 and has a function of storing code data after error correction. Under the control of the control unit K, the output L12 from the error correction unit H is received in parallel and stored in the memory cell C4. Of the code data stored in C4, memory cells corresponding to information bits are serially connected. The output unit J outputs only the corrected information bit data serially as L13 from the terminal T4. This is the corrected code block.

The control section K is connected to the input section E via a control line L14.
And the parity calculation unit F via the control line L15 and the control line L16
And an error correction unit H via a control line L17.
Is controlled through the control line L18. Specifically, the parity calculation is started after confirming that all the code data has been stored, the error detection is started after the parity calculation is completed, and the error correction is started after the error detection is completed. After that, confirm that the error correction has been completed,
It has a function to make the output unit J ready for output.

Although the above description has been given of the case of a simple three-dimensional size 3, it is to be noted that the structure of the description is similarly applied to a code having a higher dimension and a larger size. It should be noted that, other than the basic configuration of the description, there are many other variations similar to those of the description with respect to the specific parts.

[0044]

As described above, according to the present invention,
It is possible to realize a high-speed encoding device and a high-speed decoding device having a good correction capability even at a bad error rate of about 10 ^-2 to 10 ^{-1 at} a high speed of about several clock cycles. In addition, it is possible to realize an encoding device and a decoding device having higher correction capability in a high dimension, which have been difficult to use in sequential encoding and decoding processes by a CPU and software, using an LSI. In addition, since a structure that does not use a CPU is employed, error correction in a state in which the error rate is poor can be performed using a small-sized LSI. Small LS that can be mounted in various applications such as mobile wireless devices
With the device configuration such as I, high-performance encoding and decoding can be performed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration example of an encoding device.

FIG. 2 is a conceptual diagram of a high-dimensional torus knot code having three dimensions and a size of three.

FIG. 3 is a conceptual diagram of a code to which information data before encoding is input.

FIG. 4 is a diagram showing an example of all code bits including parity after encoding;

FIG. 5 is a diagram showing a transmission order of code bits after interleaving.

FIG. 6 is a functional block diagram of a decoding device.

FIG. 7 is a diagram showing a decoding device input unit;

FIG. 8 is a diagram showing a state of a parity check line when an error is mixed;

FIG. 9 is a diagram illustrating an example of a decoding device parity calculator.

FIG. 10 is a diagram illustrating an example of a decoding device error detection unit.

FIG. 11 is a diagram illustrating an example of a decoding device error correction unit and an output unit.

[Explanation of symbols]

 A Encoder input unit B Encoder parity generator C Encoder output unit D Encoder controller E Decoder input unit F Decoder parity calculator G Decoder error detector H Decoder error Correction unit J Decoding device output unit K Decoding device control unit

Claims (7)

[Claims] In an encoding apparatus, information bits input serially or in parallel are stored in an input memory cell, and the information bits are supplied in parallel to a parity generating circuit comprising a multi-input exclusive OR circuit, Outputting all necessary parity results in one time cycle, and simultaneously storing them in the output memory cells together with the information bits stored in the input memory cells, to configure the output encoding block at high speed and in a simple manner. An encoding device for a high-dimensional torus knot code. 2. The encoding apparatus according to claim 1, wherein when the bits from the parity generating circuit and the input memory cell are combined to form a bit arrangement having a high-dimensional structure, the connection to the output memory cell is made by connection. Thus, an encoding apparatus characterized in that simplification of a circuit and high-speed operation are realized. 3. In order to arrange each bit of the high-dimensional code constituted by the above-mentioned means in an output memory cell in the order of connection of a high-dimensional torus knot, the determined order of the memory cells is changed. It is characterized by realizing the coding of a high-dimensional torus knot structure with a simple structure by arranging and arranging by specifying the connection, and then operating and transmitting a series of memory cells as a shift register. Encoding device. 4. A decoding apparatus wherein one code block, which is transmitted or stored and then serially input, is configured so that the order of the bit arrangement is added by coding to the order opposite to that of coding. A decoding apparatus characterized in that a shift register circuit is used, and an original arrangement of a high-dimensional three-dimensional code is restored and formed simply and simultaneously with completion of input of one block. 5. A high-dimensional three-dimensional code re-arranged on the code side, wherein an exclusive OR circuit having m ⁿ (m: code size, n: number of dimensions) m input terminals is arranged in the decoding device. It has a connection structure to transfer the contents of m cells corresponding to the parity check line from the memory cell (cell size: ^mn ) of the structure to each exclusive OR circuit, and ^mn parity check results for each required dimension direction Are simultaneously output in one time cycle. 6. The decoding apparatus according to claim 1, wherein ^mn majority logic circuits are arranged, and the parity check result is inputted by connection so that one bit corresponds to each circuit. In order to determine the
A decoding device for high-speed operation, characterized in that, by making a decision based on a majority decision of (dimensional) parity check results, errors of all bits can be processed in parallel at once. 7. The decoding apparatus according to claim 1, wherein the value of the input bit is inverted and corrected by an exclusive OR circuit for each bit using the error determination result.
The output-side memory cells are operated as shift registers in the order determined by the wiring so that the data is transferred in parallel to the memory cells provided on the output side and only the necessary information bits are output in the order, simplifying and speeding up the operation. A decoding device characterized by being realized.