WO2004073171A3 - Carry-ripple addierer - Google Patents

Carry-ripple addierer Download PDF

Info

Publication number
WO2004073171A3
WO2004073171A3 PCT/EP2004/000796 EP2004000796W WO2004073171A3 WO 2004073171 A3 WO2004073171 A3 WO 2004073171A3 EP 2004000796 W EP2004000796 W EP 2004000796W WO 2004073171 A3 WO2004073171 A3 WO 2004073171A3
Authority
WO
WIPO (PCT)
Prior art keywords
carry
totalled
valence
bits
output
Prior art date
Application number
PCT/EP2004/000796
Other languages
English (en)
French (fr)
Other versions
WO2004073171A2 (de
Inventor
Marc Bernhardt
Joel Hatsch
Winfried Kamp
Siegmar Koeppe
Original Assignee
Infineon Technologies Ag
Marc Bernhardt
Joel Hatsch
Winfried Kamp
Siegmar Koeppe
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Marc Bernhardt, Joel Hatsch, Winfried Kamp, Siegmar Koeppe filed Critical Infineon Technologies Ag
Priority to JP2006500019A priority Critical patent/JP4157141B2/ja
Priority to EP04706161A priority patent/EP1593035A2/de
Publication of WO2004073171A2 publication Critical patent/WO2004073171A2/de
Publication of WO2004073171A3 publication Critical patent/WO2004073171A3/de
Priority to US11/203,445 priority patent/US20060294178A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/607—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers number-of-ones counters, i.e. devices for counting the number of input lines set to ONE among a plurality of input lines, also called bit counters or parallel counters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3872—Precharge of output to prevent leakage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5318—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with column wise addition of partial products, e.g. using Wallace tree, Dadda counters

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Logic Circuits (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

Die vorliegende Erfindung stellt einen Carry-Ripple Addierer (10) bereit, mit: drei ersten Eingängen (i0, i1, i2) zum Zuführen dreier zu summierender Eingangs-Bits (i0<n>, i1<n>, i2<n>) gleicher Wertigkeit 2n; zwei zweiten Eingängen (ci1, ci2) zum Zuführen zweier ebenfalls zu summierender Übertrags-/Carry-Bits (ci1<n>, ci2<n>) gleicher Wertigkeit 2n; einem Ausgang (s) zum Ausgeben eines berechneten Summen-Bits (s&lowbar;n) der gleichen Wertigkeit 2n; und zwei Ausgängen (co1, co2) zum Ausgeben zweier berechneter Übertrags-/Carry-Bits (co1<n+1>, co2<n+1>) einer gleichen Wertigkeit 2n+1, die höher ist als die Wertigkeit 2n des Summen-Bits (s&lowbar;n).
PCT/EP2004/000796 2003-02-12 2004-01-29 Carry-ripple addierer WO2004073171A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2006500019A JP4157141B2 (ja) 2003-02-12 2004-01-29 桁上げリップル加算器
EP04706161A EP1593035A2 (de) 2003-02-12 2004-01-29 Carry-ripple addierer
US11/203,445 US20060294178A1 (en) 2003-02-12 2005-08-12 Carry-ripple adder

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10305849A DE10305849B3 (de) 2003-02-12 2003-02-12 Carry-Ripple Addierer
DE10305849.4 2003-02-12

Publications (2)

Publication Number Publication Date
WO2004073171A2 WO2004073171A2 (de) 2004-08-26
WO2004073171A3 true WO2004073171A3 (de) 2005-03-10

Family

ID=32520140

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2004/000796 WO2004073171A2 (de) 2003-02-12 2004-01-29 Carry-ripple addierer

Country Status (6)

Country Link
US (1) US20060294178A1 (de)
EP (1) EP1593035A2 (de)
JP (1) JP4157141B2 (de)
CN (1) CN100541417C (de)
DE (1) DE10305849B3 (de)
WO (1) WO2004073171A2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005011666B3 (de) 2005-03-14 2006-06-29 Infineon Technologies Ag Carry-Ripple-Addierer
RU2469381C1 (ru) * 2011-11-08 2012-12-10 Общество с ограниченной ответственностью "СибИС" Сумматор
CN103345378B (zh) * 2013-07-03 2016-08-24 刘杰 三加数二进制并行同步加法器
US10073677B2 (en) * 2015-06-16 2018-09-11 Microsoft Technology Licensing, Llc Mixed-radix carry-lookahead adder architecture
CN109154944A (zh) * 2016-04-29 2019-01-04 微软技术许可有限责任公司 集合预测器
US10402165B2 (en) * 2017-08-30 2019-09-03 Gsi Technology Inc. Concurrent multi-bit adder
CN110597485B (zh) * 2019-09-10 2022-04-22 北京嘉楠捷思信息技术有限公司 模块化多位加法器及计算系统

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5493524A (en) * 1993-11-30 1996-02-20 Texas Instruments Incorporated Three input arithmetic logic unit employing carry propagate logic
US20020147756A1 (en) * 2001-04-05 2002-10-10 Joel Hatsch Carry ripple adder

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3535502A (en) * 1967-11-15 1970-10-20 Ibm Multiple input binary adder
DE69206604T2 (de) * 1992-05-27 1996-05-09 Sgs Thomson Microelectronics Schnelle Addierkette.
DE19521089C1 (de) * 1995-06-09 1996-08-08 Siemens Ag Schaltungsanordnung zur Realisierung von durch Schwellenwertgleichungen darstellbaren Logikelementen
US6065033A (en) * 1997-02-28 2000-05-16 Digital Equipment Corporation Wallace-tree multipliers using half and full adders
US5805491A (en) * 1997-07-11 1998-09-08 International Business Machines Corporation Fast 4-2 carry save adder using multiplexer logic
US6345286B1 (en) * 1998-10-30 2002-02-05 International Business Machines Corporation 6-to-3 carry-save adder
US6515534B2 (en) * 1999-12-30 2003-02-04 Intel Corporation Enhanced conductivity body biased PMOS driver
US6584485B1 (en) * 2000-04-14 2003-06-24 International Business Machines Corporation 4 to 2 adder
US7085796B1 (en) * 2000-06-08 2006-08-01 International Business Machines Corporation Dynamic adder with reduced logic
EP1178397B1 (de) * 2000-08-01 2006-10-04 STMicroelectronics S.A. Übertragsicherstellungsaddierer
US6701339B2 (en) * 2000-12-08 2004-03-02 Intel Corporation Pipelined compressor circuit
DE10139099C2 (de) * 2001-08-09 2003-06-18 Infineon Technologies Ag Carry-Ripple Addierer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5493524A (en) * 1993-11-30 1996-02-20 Texas Instruments Incorporated Three input arithmetic logic unit employing carry propagate logic
US20020147756A1 (en) * 2001-04-05 2002-10-10 Joel Hatsch Carry ripple adder

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
KORNERUP P: "Reviewing 4-to-2 adders for multi-operand addition", PROCEEDINGS OF THE IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, 17 July 2002 (2002-07-17), pages 218 - 229, XP010601474 *
PARHAMI B ED - SINGH A: "Variations on multioperand addition for faster logarithmic-time tree multipliers", SIGNALS, SYSTEMS AND COMPUTERS, 1996. CONFERENCE RECORD OF THE THIRTIETH ASILOMAR CONFERENCE ON PACIFIC GROVE, CA, USA 3-6 NOV. 1996, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 3 November 1996 (1996-11-03), pages 899 - 903, XP010231278, ISBN: 0-8186-7646-9 *

Also Published As

Publication number Publication date
DE10305849B3 (de) 2004-07-15
WO2004073171A2 (de) 2004-08-26
EP1593035A2 (de) 2005-11-09
JP4157141B2 (ja) 2008-09-24
JP2006517700A (ja) 2006-07-27
CN1748200A (zh) 2006-03-15
US20060294178A1 (en) 2006-12-28
CN100541417C (zh) 2009-09-16

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