WO2004049339A2 - Echantillonneur-bloqueur - Google Patents
Echantillonneur-bloqueur Download PDFInfo
- Publication number
- WO2004049339A2 WO2004049339A2 PCT/IB2003/005330 IB0305330W WO2004049339A2 WO 2004049339 A2 WO2004049339 A2 WO 2004049339A2 IB 0305330 W IB0305330 W IB 0305330W WO 2004049339 A2 WO2004049339 A2 WO 2004049339A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- sample
- hold
- sub
- circuits
- signal
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/02—Sample-and-hold arrangements
- G11C27/024—Sample-and-hold arrangements using a capacitive memory element
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/02—Sample-and-hold arrangements
Definitions
- the invention relates to a sample & hold circuit comprising a plurality of sample & hold sub-circuits each of said sub-circuits having a signal input connected to a common input for receiving a signal to be sampled, a switching input for receiving clock-controlled switch signals for switching the sample & hold subcircuit between a sample mode and a hold mode and a signal output for delivering samples of the input signal during the hold mode.
- the invention also relates to an analog-to-digital conversion arrangement comprising a sample & hold circuit for sampling an input signal operatively connected to quantizing means for quantizing samples of the input signal, the sample-and-hold circuit having a plurality of sample-and-hold sub-circuits each sample-and-hold sub-circuit having a signal input connected to a common input for receiving a signal to be sampled, a switch for receiving clock-controlled switch signals for switching the sample-and-hold sub-circuit between a sample mode and a hold mode and a signal output for delivering samples of the input signal to the quantizing means during the hold mode.
- the invention also relates to a method of sampling an input signal comprising a step of sampling the input signal by means of a sample-and-hold circuit comprising a plurality of sample-and-hold sub-circuits whereby each of the sample-and-hold sub-circuits is connected to a common input where the input signal is received, has a switch to switch the sample-and-hold sub-circuit between a sample mode and a hold mode, and has a signal output for delivering samples of the input signal during the hold mode.
- the invention also relates to a method for analog-to-digital conversion comprising a step of sampling an input signal by means of a sample-and-hold circuit followed by a step of quantizing samples of the input signal, whereby a sample-and-hold circuit samples the input signal and quantizing means quantize the samples of the input signal, whereby the sample-and-hold circuit has a plurality of sample-and-hold sub-circuits whereby each sample-and-hold sub-circuit is connected to a common input where the input signal is received, has a switch to switch the sample-and-hold sub-circuit between a sample mode and a hold mode, and has a signal output to deliver samples of the input signal to the quantizing means during the hold mode.
- Such sample & hold circuit is e.g.
- Sample & hold circuits comprising a plurality of sample & hold sub-circuits are well known in the art. In such circuits the sample & hold operation is divided over a plurality of sub-circuits, which therefore each have to perform only a part of the task.
- the main object is that with relatively slow sub-circuits faster sample & hold operations with more samples per second can be executed. For instance from the above mentioned prior art it is known that during the sample period of one of the sub-circuits, another subcircuit operates in the hold mode. It is also possible to evaluate the sample generated by one subcircuit simultaneously with the evaluation of another sample generated by another subcircuit.
- Another sample & hold circuit with a plurality of sample & hold sub-circuits is disclosed in European patent application EP 1160797. hi this document the sample mode of one of the sample & hold sub-circuits is executed simultaneously with the successive hold modes of the other of the sample & hold sub-circuits.
- a problem with the above-defined type of sample & hold circuits is that frequency dependent spurious components appear in the sampled signal.
- the sub-circuits require perfectly matched different clock phases to switch the respective sub-circuits and the spurious components occur when the clock phases are not sufficiently matched with each other.
- Another cause is that the input signal arrives at the sub-circuits at different instants.
- the sample & hold circuit according to the present invention is therefore characterized in that a clock controlled master switch is connected between the common input and the signal inputs of the plurality of sub-circuits and that said master switch is open when each of the sub-circuits is switched into its hold mode.
- An analog-to-digital arrangement as described in the opening paragraph is characterized in that a clock controlled master switch is connected between the common input and the signal inputs of the plurality of sub-circuits and that said master switch is open when each of the sub-circuits is switched into its hold mode.
- a method of sampling an input signal as described in the opening paragraph is characterized in that a clock controlled master switch connects the common input and the signal inputs of the plurality of sub-circuits and that said master switch is opened when each of the sub-circuits is switched into its hold mode.
- a method for analog-to-digital conversion as described in the opening paragraph is characterized in that a clock controlled master switch connects the common input and the signal inputs of the plurality of sub-circuits and that said master switch is opened when each of the sub-circuits is switched into its hold mode.
- FIG. 1 shows circuit diagram of a prior art sample & hold circuit
- Fig. 2 shows timing diagrams to explain the operation of the prior art sample & hold circuit of Fig. 1,
- Fig. 3 shows circuit diagram of a sample & hold circuit according to the invention and Fig. 4 shows timing diagrams to explain the operation of the sample & hold circuit of Fig. 3.
- the sample & hold circuit of Fig. 1 comprises a plurality of sub-circuits Si ...S n , each of which has a signal input Ii ...I n , a switching input ] ⁇ ... J n and a sample output Oi ...O n .
- the signal inputs Ii ...I n are connected to a common input I for receiving the input signal Nj to be sampled.
- the sample & hold sub-circuits are well known per se and each of them basically comprises a sampling-switch between the signal input and the sample-output and a hold-capacitance between the sample-output and a reference voltage, in this example ground.
- the switches of the sample & hold sub-circuits are controlled through the respective switching input Ji ... J n by clock-phases C ⁇ ...C n . These clock phases are generated from a master-clock C L in a clock-phase generator G.
- the sample-outputs of the sub-circuits are connected to n-1 sample-handling stages ⁇ ...N n through a switch matrix M whose operation will be explained hereafter.
- the sample & hold subcircuit Si samples the input signal Vj.
- the signal value, hold in the sample & hold subcircuit Si is applied by the switch matrix to the sample handling stage N 2 that performs e.g. a course evaluation of the sample for providing the coarse (i.e. most significant) bits of the converted digital signal.
- a new sample of the input signal Vj is taken by the sample & hold subcircuit S 2 .
- the signal hold in the sample & hold subcircuit Si is applied, through the switch matrix M to the sample-handling stage N 3 , which may be an AD-converter for deriving bits of intermediate significance.
- the sample hold in the sample & hold subcircuit S 2 is applied to the coarse sample-handling stage N 2 and the sample & hold subcircuit S 3 takes a new sample from the input signal Vj.
- This operation cyclically continues with the further sample-handling stages N ...N n performing increasingly finer AD- conversion operations.
- the last subcircuit S n has sampled the input signal, the operation continues with the sampling of the input signal by the first subcircuit in a cyclic manner.
- An important advantage of the arrangement of Fig. 1 is that for the successive operations on one sample the input signal Ni need not to be resampled.
- Fig. 2 shows the n clock phases for switching the n sample & hold sub-circuits.
- clock-phase Ci switches the subcircuit Si
- clock phase C 2 switches the subcircuit S 2 etcetera.
- This Figure also shows, by shaded areas, the time uncertainties of the edges of the different clock phases.
- These time uncertainties mainly originate from the asymmetrical circuit layout in the clock- phase generator G and of the connections between the clock-phase generator and the sample & hold sub-circuits Si ...S n . It will be apparent that these time uncertainties will cause incorrect signal samples and therefore amplitude errors in the digital output of the converter.
- the AD converter of Fig. 3 comprises a master switch P before the circuit i.e. in the input lead that applies the input signal Nj to the plurality of sample & hold subcircuit inputs Ii ...I n .
- the master switch P is controlled by the master- clock C .
- the clock-phase generator G is arranged such that the switch P is opened prior to the opening of each of the sampling switches of the sample & hold sub-circuits and closed after the opening of each of these switches. This measure is based on the recognition that the critical moment of a sample & hold circuit is the sampling moment that occurs when the sampling-switch of the sample & hold circuit opens and that, with two switches in series, the switch that opens first defines the sampling moment.
- Fig. 4 shows the timing diagram of the arrangement of Fig. 3. The vertical dashed lines indicate the new sampling moments, which are now equal for all the sub-circuits.
- the master switch P prolongs the time that the sample & hold sub-circuits are in the hold mode and consequently shortens the time that they are in the sample mode.
- the individual sampling switches in the sub-circuits have to be kept as small as reasonably possible.
- Si ...S n could be considered to be part of the switch matrix M and that, consequently, the sub- circuits Si ...S n only contain the required hold capacitances.
- the input signal Nj is then applied, through a stage ⁇ i (not shown), to said sampling switches and the master switch P is included in the stage ⁇ i. It will be apparent that the sampling switches in the matrix M and the hold capacitances in the units Si ...S n , still together constitute sample & hold sub-circuits in accordance with the scope of the present invention.
Landscapes
- Analogue/Digital Conversion (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2003280128A AU2003280128A1 (en) | 2002-11-25 | 2003-11-21 | Sample and hold circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02079885 | 2002-11-25 | ||
EP02079885.6 | 2002-11-25 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2004049339A2 true WO2004049339A2 (fr) | 2004-06-10 |
WO2004049339A3 WO2004049339A3 (fr) | 2004-09-16 |
Family
ID=32338100
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2003/005330 WO2004049339A2 (fr) | 2002-11-25 | 2003-11-21 | Echantillonneur-bloqueur |
Country Status (2)
Country | Link |
---|---|
AU (1) | AU2003280128A1 (fr) |
WO (1) | WO2004049339A2 (fr) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4823027A (en) * | 1985-04-10 | 1989-04-18 | Matsushita Electric Industrial Co., Ltd. | Sample and hold circuit |
EP1043839A2 (fr) * | 1999-04-08 | 2000-10-11 | Texas Instruments Incorporated | Réduction de distorsion d'ouverture aux convertisseurs A/N parallèles |
US20020105339A1 (en) * | 2001-02-07 | 2002-08-08 | Krishnasawamy Nagaraj | On-line cancellation of sampling mismatch in interleaved sample-and-hold circuits |
-
2003
- 2003-11-21 AU AU2003280128A patent/AU2003280128A1/en not_active Abandoned
- 2003-11-21 WO PCT/IB2003/005330 patent/WO2004049339A2/fr not_active Application Discontinuation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4823027A (en) * | 1985-04-10 | 1989-04-18 | Matsushita Electric Industrial Co., Ltd. | Sample and hold circuit |
EP1043839A2 (fr) * | 1999-04-08 | 2000-10-11 | Texas Instruments Incorporated | Réduction de distorsion d'ouverture aux convertisseurs A/N parallèles |
US20020105339A1 (en) * | 2001-02-07 | 2002-08-08 | Krishnasawamy Nagaraj | On-line cancellation of sampling mismatch in interleaved sample-and-hold circuits |
Non-Patent Citations (2)
Title |
---|
MASON R ET AL: "High-speed electro-optic analogue to digital converters" PROCEEDINGS OF THE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS. (ISCS). CHICAGO, MAY 3 - 6, 1993, NEW YORK, IEEE, US, vol. VOL. 2, 3 May 1993 (1993-05-03), pages 1081-1084, XP010115299 ISBN: 0-7803-1281-3 * |
PATENT ABSTRACTS OF JAPAN vol. 0162, no. 22 (P-1359), 25 May 1992 (1992-05-25) & JP 4 044700 A (SONY CORP), 14 February 1992 (1992-02-14) * |
Also Published As
Publication number | Publication date |
---|---|
WO2004049339A3 (fr) | 2004-09-16 |
AU2003280128A8 (en) | 2004-06-18 |
AU2003280128A1 (en) | 2004-06-18 |
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